include/configs/pf5200.h

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*************************************************************************
  25  * (c) 2005 esd gmbh Hannover
  26  *
  27  *
  28  * from IceCube.h file
  29  * by Reinhard Arlt reinhard.arlt@esd-electronics.com
  30  *
  31  *************************************************************************/
  32
  33 #ifndef __CONFIG_H
  34 #define __CONFIG_H
  35
  36 /*
  37  * High Level Configuration Options
  38  * (easy to change)
  39  */
  40
  41 #define CONFIG_MPC5200          1       /* This is an MPC5xxx CPU */
  42 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  43 #define CONFIG_ICECUBE          1       /* ... on IceCube board */
  44 #define CONFIG_PF5200           1       /* ... on PF5200  board */
  45 #define CONFIG_MPC5200_DDR      1       /* ... use DDR RAM      */
  46
  47 #ifndef CONFIG_SYS_TEXT_BASE
  48 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  49 #endif
  50
  51 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000        /* ... running at 33.000000MHz */
  52
  53 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  54 /*
  55  * Serial console configuration
  56  */
  57 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  58 #if 0                           /* test-only */
  59 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  60 #else
  61 #define CONFIG_BAUDRATE         9600    /* ... at 115200 bps */
  62 #endif
  63 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  64
  65 /*
  66  * PCI Mapping:
  67  * 0x40000000 - 0x4fffffff - PCI Memory
  68  * 0x50000000 - 0x50ffffff - PCI IO Space
  69  */
  70 #define CONFIG_PCI              1
  71 #define CONFIG_PCI_PNP          1
  72 #define CONFIG_PCI_SCAN_SHOW    1
  73 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  74
  75 #define CONFIG_PCI_MEM_BUS      0x40000000
  76 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  77 #define CONFIG_PCI_MEM_SIZE     0x10000000
  78
  79 #define CONFIG_PCI_IO_BUS       0x50000000
  80 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  81 #define CONFIG_PCI_IO_SIZE      0x01000000
  82
  83 #define CONFIG_MII              1
  84 #if 0                           /* test-only !!! */
  85 #define CONFIG_NET_MULTI        1
  86 #define CONFIG_EEPRO100         1
  87 #define CONFIG_SYS_RX_ETH_BUFFER        8       /* use 8 rx buffer on eepro100  */
  88 #define CONFIG_NS8382X          1
  89 #endif
  90
  91 /* Partitions */
  92 #define CONFIG_MAC_PARTITION
  93 #define CONFIG_DOS_PARTITION
  94
  95 /* USB */
  96 #if 0
  97 #define CONFIG_USB_OHCI
  98 #define CONFIG_USB_STORAGE
  99 #endif
 100
 101
 102 /*
 103  * BOOTP options
 104  */
 105 #define CONFIG_BOOTP_BOOTFILESIZE
 106 #define CONFIG_BOOTP_BOOTPATH
 107 #define CONFIG_BOOTP_GATEWAY
 108 #define CONFIG_BOOTP_HOSTNAME
 109
 110
 111 /*
 112  * Command line configuration.
 113  */
 114 #include <config_cmd_default.h>
 115
 116 #define CONFIG_CMD_BSP
 117 #define CONFIG_CMD_EEPROM
 118 #define CONFIG_CMD_ELF
 119 #define CONFIG_CMD_FAT
 120 #define CONFIG_CMD_I2C
 121 #define CONFIG_CMD_IDE
 122
 123 #define CONFIG_CMD_PCI
 124
 125
 126 #if (CONFIG_SYS_TEXT_BASE == 0xFF000000)        /* Boot low with 16 MB Flash */
 127 #   define CONFIG_SYS_LOWBOOT           1
 128 #   define CONFIG_SYS_LOWBOOT16 1
 129 #endif
 130 #if (CONFIG_SYS_TEXT_BASE == 0xFF800000)        /* Boot low with  8 MB Flash */
 131 #   define CONFIG_SYS_LOWBOOT           1
 132 #   define CONFIG_SYS_LOWBOOT08 1
 133 #endif
 134
 135 /*
 136  * Autobooting
 137  */
 138 #define CONFIG_BOOTDELAY        3       /* autoboot after 5 seconds */
 139
 140 #define CONFIG_PREBOOT  "echo;" \
 141         "echo Welcome to ParaFinder pf5200;" \
 142         "echo"
 143
 144 #undef  CONFIG_BOOTARGS
 145
 146 #define CONFIG_EXTRA_ENV_SETTINGS \
 147         "netdev=eth0\0" \
 148         "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
 149         "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
 150         "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
 151         "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
 152         "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
 153         "loadaddr=01000000\0" \
 154         "serverip=192.168.2.99\0" \
 155         "gatewayip=10.0.0.79\0" \
 156         "user=mu\0" \
 157         "target=pf5200.esd\0" \
 158         "script=pf5200.bat\0" \
 159         "image=/tftpboot/vxWorks_pf5200\0" \
 160         "ipaddr=10.0.13.196\0" \
 161         "netmask=255.255.0.0\0" \
 162         ""
 163
 164 #define CONFIG_BOOTCOMMAND      "run flash_vxworks0"
 165
 166 /*
 167  * IPB Bus clocking configuration.
 168  */
 169 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK          /* define for 133MHz speed */
 170 /*
 171  * I2C configuration
 172  */
 173 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 174 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #1 or #2 */
 175
 176 #define CONFIG_SYS_I2C_SPEED            86000   /* 100 kHz */
 177 #define CONFIG_SYS_I2C_SLAVE            0x7F
 178
 179 /*
 180  * EEPROM configuration
 181  */
 182 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 183 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 184 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5
 185 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   20
 186 #define CONFIG_SYS_I2C_MULTI_EEPROMS            1
 187 /*
 188  * Flash configuration
 189  */
 190 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 191 #define CONFIG_SYS_FLASH_SIZE           0x02000000
 192 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00000000)
 193 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 194 #define CONFIG_SYS_MAX_FLASH_SECT       512
 195
 196 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 197 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 198
 199 /*
 200  * Environment settings
 201  */
 202 #if 1                           /* test-only */
 203 #define CONFIG_ENV_IS_IN_FLASH
 204 #define CONFIG_ENV_SIZE         0x10000
 205 #define CONFIG_ENV_SECT_SIZE    0x10000
 206 #define CONFIG_ENV_OVERWRITE    1
 207 #else
 208 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 209 #define CONFIG_ENV_OFFSET               0x0000  /* environment starts at the beginning of the EEPROM */
 210 #define CONFIG_ENV_SIZE         0x0400  /* 8192 bytes may be used for env vars */
 211                                    /* total size of a CAT24WC32 is 8192 bytes */
 212 #define CONFIG_ENV_OVERWRITE    1
 213 #endif
 214
 215 /*
 216  * Memory map
 217  */
 218 #define CONFIG_SYS_MBAR         0xF0000000
 219 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 220 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 221
 222 /* Use SRAM until RAM will be available */
 223 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 224 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE       /* Size of used area in DPRAM */
 225
 226 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 227 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 228
 229 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 230 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 231 #   define CONFIG_SYS_RAMBOOT           1
 232 #endif
 233
 234 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 235 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 236 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 237
 238 /*
 239  * Ethernet configuration
 240  */
 241 #define CONFIG_MPC5xxx_FEC      1
 242 #define CONFIG_MPC5xxx_FEC_MII100
 243 /*
 244  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 245  */
 246 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 247 #define CONFIG_PHY_ADDR         0x00
 248 #define CONFIG_UDP_CHECKSUM     1
 249
 250 /*
 251  * GPIO configuration
 252  */
 253 #define CONFIG_SYS_GPS_PORT_CONFIG      0x01052444
 254
 255 /*
 256  * Miscellaneous configurable options
 257  */
 258 #define CONFIG_SYS_LONGHELP             /* undef to save memory     */
 259 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 260 #if defined(CONFIG_CMD_KGDB)
 261 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 262 #else
 263 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 264 #endif
 265 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 266 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 267 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 268
 269 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 270 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 271
 272 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 273
 274 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 275
 276 #define CONFIG_SYS_VXWORKS_MAC_PTR      0x00000000      /* Pass Ethernet MAC to VxWorks */
 277
 278 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 279 #if defined(CONFIG_CMD_KGDB)
 280 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 281 #endif
 282
 283 /*
 284  * Various low-level settings
 285  */
 286 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 287 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 288
 289 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 290 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 291 #define CONFIG_SYS_BOOTCS_CFG           0x0004DD00
 292
 293 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 294 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 295
 296 #define CONFIG_SYS_CS1_START            0xfd000000
 297 #define CONFIG_SYS_CS1_SIZE             0x00010000
 298 #define CONFIG_SYS_CS1_CFG              0x10101410
 299
 300 #define CONFIG_SYS_CS_BURST             0x00000000
 301 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 302
 303 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 304
 305 /*-----------------------------------------------------------------------
 306  * USB stuff
 307  *-----------------------------------------------------------------------
 308  */
 309 #define CONFIG_USB_CLOCK        0x0001BBBB
 310 #define CONFIG_USB_CONFIG       0x00001000
 311
 312 /*-----------------------------------------------------------------------
 313  * IDE/ATA stuff Supports IDE harddisk
 314  *-----------------------------------------------------------------------
 315  */
 316
 317 #undef  CONFIG_IDE_8xx_PCCARD   /* Use IDE with PC Card Adapter */
 318
 319 #undef  CONFIG_IDE_8xx_DIRECT   /* Direct IDE    not supported  */
 320 #undef  CONFIG_IDE_LED          /* LED   for ide not supported  */
 321
 322 #define CONFIG_IDE_RESET        /* reset for ide supported      */
 323 #define CONFIG_IDE_PREINIT
 324
 325 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 326 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 327
 328 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 329
 330 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 331
 332 /* Offset for data I/O                  */
 333 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 334
 335 /* Offset for normal register accesses  */
 336 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 337
 338 /* Offset for alternate registers       */
 339 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 340
 341 /* Interval between registers                                                */
 342 #define CONFIG_SYS_ATA_STRIDE           4
 343
 344 /*-----------------------------------------------------------------------
 345  * CPLD stuff
 346  */
 347 #define CONFIG_SYS_FPGA_XC95XL          1       /* using Xilinx XC95XL CPLD      */
 348 #define CONFIG_SYS_FPGA_MAX_SIZE        32*1024 /* 32kByte is enough for CPLD    */
 349
 350 /* CPLD program pin configuration */
 351 #define CONFIG_SYS_FPGA_PRG             0x20000000      /* JTAG TMS pin (ppc output)           */
 352 #define CONFIG_SYS_FPGA_CLK             0x10000000      /* JTAG TCK pin (ppc output)           */
 353 #define CONFIG_SYS_FPGA_DATA            0x20000000      /* JTAG TDO->TDI data pin (ppc output) */
 354 #define CONFIG_SYS_FPGA_DONE            0x10000000      /* JTAG TDI->TDO pin (ppc input)       */
 355
 356 #define JTAG_GPIO_ADDR_TMS      (CONFIG_SYS_MBAR + 0xB10)       /* JTAG TMS pin (GPS data out value reg.)      */
 357 #define JTAG_GPIO_ADDR_TCK      (CONFIG_SYS_MBAR + 0xC0C)       /* JTAG TCK pin (GPW data out value reg.)      */
 358 #define JTAG_GPIO_ADDR_TDI      (CONFIG_SYS_MBAR + 0xC0C)       /* JTAG TDO->TDI pin (GPW data out value reg.) */
 359 #define JTAG_GPIO_ADDR_TDO      (CONFIG_SYS_MBAR + 0xB14)       /* JTAG TDI->TDO pin (GPS data in value reg.)  */
 360
 361 #define JTAG_GPIO_ADDR_CFG      (CONFIG_SYS_MBAR + 0xB00)
 362 #define JTAG_GPIO_CFG_SET       0x00000000
 363 #define JTAG_GPIO_CFG_RESET     0x00F00000
 364
 365 #define JTAG_GPIO_ADDR_EN_TMS   (CONFIG_SYS_MBAR + 0xB04)
 366 #define JTAG_GPIO_TMS_EN_SET    0x20000000      /* Enable for GPIO */
 367 #define JTAG_GPIO_TMS_EN_RESET  0x00000000
 368 #define JTAG_GPIO_ADDR_DDR_TMS  (CONFIG_SYS_MBAR + 0xB0C)
 369 #define JTAG_GPIO_TMS_DDR_SET   0x20000000      /* Set as output   */
 370 #define JTAG_GPIO_TMS_DDR_RESET 0x00000000
 371
 372 #define JTAG_GPIO_ADDR_EN_TCK   (CONFIG_SYS_MBAR + 0xC00)
 373 #define JTAG_GPIO_TCK_EN_SET    0x20000000      /* Enable for GPIO */
 374 #define JTAG_GPIO_TCK_EN_RESET  0x00000000
 375 #define JTAG_GPIO_ADDR_DDR_TCK  (CONFIG_SYS_MBAR + 0xC08)
 376 #define JTAG_GPIO_TCK_DDR_SET   0x20000000      /* Set as output   */
 377 #define JTAG_GPIO_TCK_DDR_RESET 0x00000000
 378
 379 #define JTAG_GPIO_ADDR_EN_TDI   (CONFIG_SYS_MBAR + 0xC00)
 380 #define JTAG_GPIO_TDI_EN_SET    0x10000000      /* Enable as GPIO  */
 381 #define JTAG_GPIO_TDI_EN_RESET  0x00000000
 382 #define JTAG_GPIO_ADDR_DDR_TDI  (CONFIG_SYS_MBAR + 0xC08)
 383 #define JTAG_GPIO_TDI_DDR_SET   0x10000000      /* Set as output   */
 384 #define JTAG_GPIO_TDI_DDR_RESET 0x00000000
 385
 386 #define JTAG_GPIO_ADDR_EN_TDO   (CONFIG_SYS_MBAR + 0xB04)
 387 #define JTAG_GPIO_TDO_EN_SET    0x10000000      /* Enable as GPIO  */
 388 #define JTAG_GPIO_TDO_EN_RESET  0x00000000
 389 #define JTAG_GPIO_ADDR_DDR_TDO  (CONFIG_SYS_MBAR + 0xB0C)
 390 #define JTAG_GPIO_TDO_DDR_SET   0x00000000
 391 #define JTAG_GPIO_TDO_DDR_RESET 0x10000000      /* Set as input    */
 392
 393 #endif                          /* __CONFIG_H */