include/configs/pf5200.h

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*************************************************************************
   9  * (c) 2005 esd gmbh Hannover
  10  *
  11  *
  12  * from IceCube.h file
  13  * by Reinhard Arlt reinhard.arlt@esd-electronics.com
  14  *
  15  *************************************************************************/
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 /*
  21  * High Level Configuration Options
  22  * (easy to change)
  23  */
  24
  25 #define CONFIG_MPC5200          1       /* This is an MPC5200 CPU */
  26 #define CONFIG_ICECUBE          1       /* ... on IceCube board */
  27 #define CONFIG_PF5200           1       /* ... on PF5200  board */
  28 #define CONFIG_MPC5200_DDR      1       /* ... use DDR RAM      */
  29
  30 #ifndef CONFIG_SYS_TEXT_BASE
  31 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  32 #endif
  33
  34 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000        /* ... running at 33.000000MHz */
  35
  36 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  37 /*
  38  * Serial console configuration
  39  */
  40 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  41 #if 0                           /* test-only */
  42 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  43 #else
  44 #define CONFIG_BAUDRATE         9600    /* ... at 115200 bps */
  45 #endif
  46 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  47
  48 /*
  49  * PCI Mapping:
  50  * 0x40000000 - 0x4fffffff - PCI Memory
  51  * 0x50000000 - 0x50ffffff - PCI IO Space
  52  */
  53 #define CONFIG_PCI              1
  54 #define CONFIG_PCI_PNP          1
  55 #define CONFIG_PCI_SCAN_SHOW    1
  56 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  57
  58 #define CONFIG_PCI_MEM_BUS      0x40000000
  59 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  60 #define CONFIG_PCI_MEM_SIZE     0x10000000
  61
  62 #define CONFIG_PCI_IO_BUS       0x50000000
  63 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  64 #define CONFIG_PCI_IO_SIZE      0x01000000
  65
  66 #define CONFIG_MII              1
  67 #if 0                           /* test-only !!! */
  68 #define CONFIG_EEPRO100         1
  69 #define CONFIG_SYS_RX_ETH_BUFFER        8       /* use 8 rx buffer on eepro100  */
  70 #define CONFIG_NS8382X          1
  71 #endif
  72
  73 /* Partitions */
  74 #define CONFIG_MAC_PARTITION
  75 #define CONFIG_DOS_PARTITION
  76
  77 /* USB */
  78 #if 0
  79 #define CONFIG_USB_OHCI
  80 #define CONFIG_USB_STORAGE
  81 #endif
  82
  83
  84 /*
  85  * BOOTP options
  86  */
  87 #define CONFIG_BOOTP_BOOTFILESIZE
  88 #define CONFIG_BOOTP_BOOTPATH
  89 #define CONFIG_BOOTP_GATEWAY
  90 #define CONFIG_BOOTP_HOSTNAME
  91
  92
  93 /*
  94  * Command line configuration.
  95  */
  96 #include <config_cmd_default.h>
  97
  98 #define CONFIG_CMD_BSP
  99 #define CONFIG_CMD_EEPROM
 100 #define CONFIG_CMD_ELF
 101 #define CONFIG_CMD_FAT
 102 #define CONFIG_CMD_I2C
 103 #define CONFIG_CMD_IDE
 104
 105 #define CONFIG_CMD_PCI
 106
 107
 108 #if (CONFIG_SYS_TEXT_BASE == 0xFF000000)        /* Boot low with 16 MB Flash */
 109 #   define CONFIG_SYS_LOWBOOT           1
 110 #   define CONFIG_SYS_LOWBOOT16 1
 111 #endif
 112 #if (CONFIG_SYS_TEXT_BASE == 0xFF800000)        /* Boot low with  8 MB Flash */
 113 #   define CONFIG_SYS_LOWBOOT           1
 114 #   define CONFIG_SYS_LOWBOOT08 1
 115 #endif
 116
 117 /*
 118  * Autobooting
 119  */
 120 #define CONFIG_BOOTDELAY        3       /* autoboot after 5 seconds */
 121
 122 #define CONFIG_PREBOOT  "echo;" \
 123         "echo Welcome to ParaFinder pf5200;" \
 124         "echo"
 125
 126 #undef  CONFIG_BOOTARGS
 127
 128 #define CONFIG_EXTRA_ENV_SETTINGS \
 129         "netdev=eth0\0" \
 130         "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
 131         "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
 132         "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
 133         "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
 134         "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
 135         "loadaddr=01000000\0" \
 136         "serverip=192.168.2.99\0" \
 137         "gatewayip=10.0.0.79\0" \
 138         "user=mu\0" \
 139         "target=pf5200.esd\0" \
 140         "script=pf5200.bat\0" \
 141         "image=/tftpboot/vxWorks_pf5200\0" \
 142         "ipaddr=10.0.13.196\0" \
 143         "netmask=255.255.0.0\0" \
 144         ""
 145
 146 #define CONFIG_BOOTCOMMAND      "run flash_vxworks0"
 147
 148 /*
 149  * IPB Bus clocking configuration.
 150  */
 151 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK          /* define for 133MHz speed */
 152 /*
 153  * I2C configuration
 154  */
 155 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 156 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #1 or #2 */
 157
 158 #define CONFIG_SYS_I2C_SPEED            86000   /* 100 kHz */
 159 #define CONFIG_SYS_I2C_SLAVE            0x7F
 160
 161 /*
 162  * EEPROM configuration
 163  */
 164 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 165 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 166 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5
 167 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   20
 168 #define CONFIG_SYS_I2C_MULTI_EEPROMS            1
 169 /*
 170  * Flash configuration
 171  */
 172 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 173 #define CONFIG_SYS_FLASH_SIZE           0x02000000
 174 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00000000)
 175 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 176 #define CONFIG_SYS_MAX_FLASH_SECT       512
 177
 178 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 179 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 180
 181 /*
 182  * Environment settings
 183  */
 184 #if 1                           /* test-only */
 185 #define CONFIG_ENV_IS_IN_FLASH
 186 #define CONFIG_ENV_SIZE         0x10000
 187 #define CONFIG_ENV_SECT_SIZE    0x10000
 188 #define CONFIG_ENV_OVERWRITE    1
 189 #else
 190 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 191 #define CONFIG_ENV_OFFSET               0x0000  /* environment starts at the beginning of the EEPROM */
 192 #define CONFIG_ENV_SIZE         0x0400  /* 8192 bytes may be used for env vars */
 193                                    /* total size of a CAT24WC32 is 8192 bytes */
 194 #define CONFIG_ENV_OVERWRITE    1
 195 #endif
 196
 197 /*
 198  * Memory map
 199  */
 200 #define CONFIG_SYS_MBAR         0xF0000000
 201 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 202 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 203
 204 /* Use SRAM until RAM will be available */
 205 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 206 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE       /* Size of used area in DPRAM */
 207
 208 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 209 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 210
 211 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 212 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 213 #   define CONFIG_SYS_RAMBOOT           1
 214 #endif
 215
 216 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 217 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 218 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 219
 220 /*
 221  * Ethernet configuration
 222  */
 223 #define CONFIG_MPC5xxx_FEC      1
 224 #define CONFIG_MPC5xxx_FEC_MII100
 225 /*
 226  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 227  */
 228 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 229 #define CONFIG_PHY_ADDR         0x00
 230 #define CONFIG_UDP_CHECKSUM     1
 231
 232 /*
 233  * GPIO configuration
 234  */
 235 #define CONFIG_SYS_GPS_PORT_CONFIG      0x01052444
 236
 237 /*
 238  * Miscellaneous configurable options
 239  */
 240 #define CONFIG_SYS_LONGHELP             /* undef to save memory     */
 241 #if defined(CONFIG_CMD_KGDB)
 242 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 243 #else
 244 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 245 #endif
 246 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 247 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 248 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 249
 250 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 251 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 252
 253 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 254
 255 #define CONFIG_SYS_VXWORKS_MAC_PTR      0x00000000      /* Pass Ethernet MAC to VxWorks */
 256
 257 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 258 #if defined(CONFIG_CMD_KGDB)
 259 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 260 #endif
 261
 262 /*
 263  * Various low-level settings
 264  */
 265 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 266 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 267
 268 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 269 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 270 #define CONFIG_SYS_BOOTCS_CFG           0x0004DD00
 271
 272 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 273 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 274
 275 #define CONFIG_SYS_CS1_START            0xfd000000
 276 #define CONFIG_SYS_CS1_SIZE             0x00010000
 277 #define CONFIG_SYS_CS1_CFG              0x10101410
 278
 279 #define CONFIG_SYS_CS_BURST             0x00000000
 280 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 281
 282 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 283
 284 /*-----------------------------------------------------------------------
 285  * USB stuff
 286  *-----------------------------------------------------------------------
 287  */
 288 #define CONFIG_USB_CLOCK        0x0001BBBB
 289 #define CONFIG_USB_CONFIG       0x00001000
 290
 291 /*-----------------------------------------------------------------------
 292  * IDE/ATA stuff Supports IDE harddisk
 293  *-----------------------------------------------------------------------
 294  */
 295
 296 #undef  CONFIG_IDE_8xx_PCCARD   /* Use IDE with PC Card Adapter */
 297
 298 #undef  CONFIG_IDE_8xx_DIRECT   /* Direct IDE    not supported  */
 299 #undef  CONFIG_IDE_LED          /* LED   for ide not supported  */
 300
 301 #define CONFIG_IDE_RESET        /* reset for ide supported      */
 302 #define CONFIG_IDE_PREINIT
 303
 304 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 305 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 306
 307 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 308
 309 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 310
 311 /* Offset for data I/O                  */
 312 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 313
 314 /* Offset for normal register accesses  */
 315 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 316
 317 /* Offset for alternate registers       */
 318 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 319
 320 /* Interval between registers                                                */
 321 #define CONFIG_SYS_ATA_STRIDE           4
 322
 323 /*-----------------------------------------------------------------------
 324  * CPLD stuff
 325  */
 326 #define CONFIG_SYS_FPGA_XC95XL          1       /* using Xilinx XC95XL CPLD      */
 327 #define CONFIG_SYS_FPGA_MAX_SIZE        32*1024 /* 32kByte is enough for CPLD    */
 328
 329 /* CPLD program pin configuration */
 330 #define CONFIG_SYS_FPGA_PRG             0x20000000      /* JTAG TMS pin (ppc output)           */
 331 #define CONFIG_SYS_FPGA_CLK             0x10000000      /* JTAG TCK pin (ppc output)           */
 332 #define CONFIG_SYS_FPGA_DATA            0x20000000      /* JTAG TDO->TDI data pin (ppc output) */
 333 #define CONFIG_SYS_FPGA_DONE            0x10000000      /* JTAG TDI->TDO pin (ppc input)       */
 334
 335 #define JTAG_GPIO_ADDR_TMS      (CONFIG_SYS_MBAR + 0xB10)       /* JTAG TMS pin (GPS data out value reg.)      */
 336 #define JTAG_GPIO_ADDR_TCK      (CONFIG_SYS_MBAR + 0xC0C)       /* JTAG TCK pin (GPW data out value reg.)      */
 337 #define JTAG_GPIO_ADDR_TDI      (CONFIG_SYS_MBAR + 0xC0C)       /* JTAG TDO->TDI pin (GPW data out value reg.) */
 338 #define JTAG_GPIO_ADDR_TDO      (CONFIG_SYS_MBAR + 0xB14)       /* JTAG TDI->TDO pin (GPS data in value reg.)  */
 339
 340 #define JTAG_GPIO_ADDR_CFG      (CONFIG_SYS_MBAR + 0xB00)
 341 #define JTAG_GPIO_CFG_SET       0x00000000
 342 #define JTAG_GPIO_CFG_RESET     0x00F00000
 343
 344 #define JTAG_GPIO_ADDR_EN_TMS   (CONFIG_SYS_MBAR + 0xB04)
 345 #define JTAG_GPIO_TMS_EN_SET    0x20000000      /* Enable for GPIO */
 346 #define JTAG_GPIO_TMS_EN_RESET  0x00000000
 347 #define JTAG_GPIO_ADDR_DDR_TMS  (CONFIG_SYS_MBAR + 0xB0C)
 348 #define JTAG_GPIO_TMS_DDR_SET   0x20000000      /* Set as output   */
 349 #define JTAG_GPIO_TMS_DDR_RESET 0x00000000
 350
 351 #define JTAG_GPIO_ADDR_EN_TCK   (CONFIG_SYS_MBAR + 0xC00)
 352 #define JTAG_GPIO_TCK_EN_SET    0x20000000      /* Enable for GPIO */
 353 #define JTAG_GPIO_TCK_EN_RESET  0x00000000
 354 #define JTAG_GPIO_ADDR_DDR_TCK  (CONFIG_SYS_MBAR + 0xC08)
 355 #define JTAG_GPIO_TCK_DDR_SET   0x20000000      /* Set as output   */
 356 #define JTAG_GPIO_TCK_DDR_RESET 0x00000000
 357
 358 #define JTAG_GPIO_ADDR_EN_TDI   (CONFIG_SYS_MBAR + 0xC00)
 359 #define JTAG_GPIO_TDI_EN_SET    0x10000000      /* Enable as GPIO  */
 360 #define JTAG_GPIO_TDI_EN_RESET  0x00000000
 361 #define JTAG_GPIO_ADDR_DDR_TDI  (CONFIG_SYS_MBAR + 0xC08)
 362 #define JTAG_GPIO_TDI_DDR_SET   0x10000000      /* Set as output   */
 363 #define JTAG_GPIO_TDI_DDR_RESET 0x00000000
 364
 365 #define JTAG_GPIO_ADDR_EN_TDO   (CONFIG_SYS_MBAR + 0xB04)
 366 #define JTAG_GPIO_TDO_EN_SET    0x10000000      /* Enable as GPIO  */
 367 #define JTAG_GPIO_TDO_EN_RESET  0x00000000
 368 #define JTAG_GPIO_ADDR_DDR_TDO  (CONFIG_SYS_MBAR + 0xB0C)
 369 #define JTAG_GPIO_TDO_DDR_SET   0x00000000
 370 #define JTAG_GPIO_TDO_DDR_RESET 0x10000000      /* Set as input    */
 371
 372 #endif                          /* __CONFIG_H */