include/configs/pm9g45.h

   1 /*
   2  * (C) Copyright 2010
   3  * Ilko Iliev <iliev@ronetix.at>
   4  * Asen Dimov <dimov@ronetix.at>
   5  * Ronetix GmbH <www.ronetix.at>
   6  *
   7  * (C) Copyright 2007-2008
   8  * Stelian Pop <stelian@popies.net>
   9  * Lead Tech Design <www.leadtechdesign.com>
  10  *
  11  * Configuation settings for the PM9G45 board.
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * SoC must be defined first, before hardware.h is included.
  21  * In this case SoC is defined in boards.cfg.
  22  */
  23 #include <asm/hardware.h>
  24
  25 #define CONFIG_PM9G45           1       /* It's an Ronetix PM9G45 */
  26 #define CONFIG_SYS_AT91_CPU_NAME        "AT91SAM9G45"
  27
  28 #define CONFIG_MACH_TYPE        MACH_TYPE_PM9G45
  29
  30 /* ARM asynchronous clock */
  31 #define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
  32 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock xtal */
  33 #define CONFIG_SYS_TEXT_BASE            0x73f00000
  34
  35 #define CONFIG_ARCH_CPU_INIT
  36
  37 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs */
  38 #define CONFIG_SETUP_MEMORY_TAGS 1
  39 #define CONFIG_INITRD_TAG       1
  40
  41 #define CONFIG_SKIP_LOWLEVEL_INIT
  42
  43 /*
  44  * Hardware drivers
  45  */
  46 #define CONFIG_AT91_GPIO        1
  47 #define CONFIG_ATMEL_USART      1
  48 #define CONFIG_USART_BASE               ATMEL_BASE_DBGU
  49 #define CONFIG_USART_ID                 ATMEL_ID_SYS
  50
  51 #define CONFIG_SYS_USE_NANDFLASH        1
  52
  53 /* LED */
  54 #define CONFIG_AT91_LED
  55 #define CONFIG_RED_LED          GPIO_PIN_PD(31) /* this is the user1 led */
  56 #define CONFIG_GREEN_LED        GPIO_PIN_PD(0)  /* this is the user2 led */
  57
  58
  59 /*
  60  * BOOTP options
  61  */
  62 #define CONFIG_BOOTP_BOOTFILESIZE       1
  63 #define CONFIG_BOOTP_BOOTPATH           1
  64 #define CONFIG_BOOTP_GATEWAY            1
  65 #define CONFIG_BOOTP_HOSTNAME           1
  66
  67 /*
  68  * Command line configuration.
  69  */
  70 #define CONFIG_CMD_NAND         1
  71
  72 #define CONFIG_CMD_JFFS2                1
  73 #define CONFIG_JFFS2_CMDLINE            1
  74 #define CONFIG_JFFS2_NAND               1
  75 #define CONFIG_JFFS2_DEV                "nand0" /* NAND dev jffs2 lives on */
  76 #define CONFIG_JFFS2_PART_OFFSET        0       /* start of jffs2 partition */
  77 #define CONFIG_JFFS2_PART_SIZE          (256 * 1024 * 1024) /* partition */
  78
  79 /* SDRAM */
  80 #define CONFIG_NR_DRAM_BANKS            1
  81 #define PHYS_SDRAM                      0x70000000
  82 #define PHYS_SDRAM_SIZE                 0x08000000      /* 128 megs */
  83
  84 /* NOR flash, not available */
  85 #define CONFIG_SYS_NO_FLASH             1
  86
  87 /* NAND flash */
  88 #ifdef CONFIG_CMD_NAND
  89 #define CONFIG_NAND_ATMEL
  90 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  91 #define CONFIG_SYS_NAND_BASE            0x40000000
  92 #define CONFIG_SYS_NAND_DBW_8           1
  93 /* our ALE is AD21 */
  94 #define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
  95 /* our CLE is AD22 */
  96 #define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
  97 #define CONFIG_SYS_NAND_ENABLE_PIN      GPIO_PIN_PC(14)
  98 #define CONFIG_SYS_NAND_READY_PIN       GPIO_PIN_PD(3)
  99
 100 #endif
 101
 102 /* Ethernet */
 103 #define CONFIG_MACB                     1
 104 #define CONFIG_RMII                     1
 105 #define CONFIG_NET_RETRY_COUNT          20
 106 #define CONFIG_RESET_PHY_R              1
 107
 108 /* USB */
 109 #define CONFIG_USB_ATMEL
 110 #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
 111 #define CONFIG_USB_OHCI_NEW             1
 112 #define CONFIG_SYS_USB_OHCI_CPU_INIT    1
 113 #define CONFIG_SYS_USB_OHCI_REGS_BASE   0x00700000 /* _UHP_OHCI_BASE */
 114 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "at91sam9g45"
 115 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 116
 117 /* board specific(not enough SRAM) */
 118 #define CONFIG_AT91SAM9G45_LCD_BASE     PHYS_SDRAM + 0xE00000
 119
 120 #define CONFIG_SYS_LOAD_ADDR            PHYS_SDRAM + 0x2000000 /* load addr */
 121
 122 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM
 123 #define CONFIG_SYS_MEMTEST_END          CONFIG_AT91SAM9G45_LCD_BASE
 124
 125 /* bootstrap + u-boot + env + linux in nandflash */
 126 #define CONFIG_ENV_IS_IN_NAND           1
 127 #define CONFIG_ENV_OFFSET               0x60000
 128 #define CONFIG_ENV_OFFSET_REDUND        0x80000
 129 #define CONFIG_ENV_SIZE                 0x20000         /* 1 sector = 128 kB */
 130 #define CONFIG_BOOTCOMMAND      "nand read 0x72000000 0x200000 0x200000; bootm"
 131 #define CONFIG_BOOTARGS         "fbcon=rotate:3 console=tty0 " \
 132                                 "console=ttyS0,115200 " \
 133                                 "root=/dev/mtdblock4 " \
 134                                 "mtdparts=atmel_nand:128k(bootstrap)ro," \
 135                                 "256k(uboot)ro,1664k(env)," \
 136                                 "2M(linux)ro,-(root) rw " \
 137                                 "rootfstype=jffs2"
 138
 139 #define CONFIG_BAUDRATE                 115200
 140
 141 #define CONFIG_SYS_CBSIZE               256
 142 #define CONFIG_SYS_MAXARGS              16
 143 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 144                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 145 #define CONFIG_SYS_LONGHELP             1
 146 #define CONFIG_CMDLINE_EDITING          1
 147 #define CONFIG_AUTO_COMPLETE
 148
 149 /*
 150  * Size of malloc() pool
 151  */
 152 #define CONFIG_SYS_MALLOC_LEN           ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\
 153                                         0x1000)
 154
 155 #define CONFIG_SYS_SDRAM_BASE   PHYS_SDRAM
 156 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 157                                 GENERATED_GBL_DATA_SIZE)
 158
 159 #endif