include/configs/porter.h

   1 /*
   2  * include/configs/porter.h
   3  *     This file is Porter board configuration.
   4  *
   5  * Copyright (C) 2015 Renesas Electronics Corporation
   6  * Copyright (C) 2015 Cogent Embedded, Inc.
   7  *
   8  * SPDX-License-Identifier: GPL-2.0
   9  */
  10
  11 #ifndef __PORTER_H
  12 #define __PORTER_H
  13
  14 #undef DEBUG
  15 #define CONFIG_ARCH_RMOBILE_BOARD_STRING "Porter"
  16
  17 #include "rcar-gen2-common.h"
  18
  19 #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
  20 #define CONFIG_SYS_TEXT_BASE    0x70000000
  21 #else
  22 #define CONFIG_SYS_TEXT_BASE    0xE6304000
  23 #endif
  24
  25 #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
  26 #define CONFIG_SYS_INIT_SP_ADDR         0x7003FFFC
  27 #else
  28 #define CONFIG_SYS_INIT_SP_ADDR         0xE633fffC
  29 #endif
  30 #define STACK_AREA_SIZE                 0xC000
  31 #define LOW_LEVEL_MERAM_STACK \
  32                 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
  33
  34 /* MEMORY */
  35 #define RCAR_GEN2_SDRAM_BASE            0x40000000
  36 #define RCAR_GEN2_SDRAM_SIZE            (2048u * 1024 * 1024)
  37 #define RCAR_GEN2_UBOOT_SDRAM_SIZE      (1024u * 1024 * 1024)
  38
  39 /* SCIF */
  40
  41 /* FLASH */
  42 #define CONFIG_SPI
  43 #define CONFIG_SH_QSPI
  44 #define CONFIG_SPI_FLASH_QUAD
  45
  46 /* SH Ether */
  47 #define CONFIG_SH_ETHER_USE_PORT        0
  48 #define CONFIG_SH_ETHER_PHY_ADDR        0x1
  49 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
  50 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
  51 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
  52 #define CONFIG_SH_ETHER_ALIGNE_SIZE     64
  53 #define CONFIG_BITBANGMII
  54 #define CONFIG_BITBANGMII_MULTI
  55
  56 /* Board Clock */
  57 #define RMOBILE_XTAL_CLK        20000000u
  58 #define CONFIG_SYS_CLK_FREQ     RMOBILE_XTAL_CLK
  59 #define CONFIG_SH_TMU_CLK_FREQ  (CONFIG_SYS_CLK_FREQ / 2)
  60 #define CONFIG_PLL1_CLK_FREQ    (CONFIG_SYS_CLK_FREQ * 156 / 2)
  61 #define CONFIG_P_CLK_FREQ       (CONFIG_PLL1_CLK_FREQ / 24)
  62
  63 #define CONFIG_SYS_TMU_CLK_DIV  4
  64
  65 /* i2c */
  66 #define CONFIG_SYS_I2C
  67 #define CONFIG_SYS_I2C_SH
  68 #define CONFIG_SYS_I2C_SLAVE            0x7F
  69 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS       3
  70 #define CONFIG_SYS_I2C_SH_SPEED0        400000
  71 #define CONFIG_SYS_I2C_SH_SPEED1        400000
  72 #define CONFIG_SYS_I2C_SH_SPEED2        400000
  73 #define CONFIG_SH_I2C_DATA_HIGH         4
  74 #define CONFIG_SH_I2C_DATA_LOW          5
  75 #define CONFIG_SH_I2C_CLOCK             10000000
  76
  77 #define CONFIG_SYS_I2C_POWERIC_ADDR     0x58 /* da9063 */
  78
  79 /* USB */
  80 #define CONFIG_USB_EHCI_RMOBILE
  81 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  82
  83 /* SD */
  84 #define CONFIG_SH_SDHI_FREQ     97500000
  85
  86 /* Module stop status bits */
  87 /* INTC-RT */
  88 #define CONFIG_SMSTP0_ENA       0x00400000
  89 /* MSIF */
  90 #define CONFIG_SMSTP2_ENA       0x00002000
  91 /* INTC-SYS, IRQC */
  92 #define CONFIG_SMSTP4_ENA       0x00000180
  93 /* SCIF0 */
  94 #define CONFIG_SMSTP7_ENA       0x00200000
  95
  96 #endif /* __PORTER_H */