include/configs/porter.h

   1 /*
   2  * include/configs/porter.h
   3  *     This file is Porter board configuration.
   4  *
   5  * Copyright (C) 2015 Renesas Electronics Corporation
   6  * Copyright (C) 2015 Cogent Embedded, Inc.
   7  *
   8  * SPDX-License-Identifier: GPL-2.0
   9  */
  10
  11 #ifndef __PORTER_H
  12 #define __PORTER_H
  13
  14 #undef DEBUG
  15 #define CONFIG_R8A7791
  16 #define CONFIG_ARCH_RMOBILE_BOARD_STRING "Porter"
  17
  18 #include "rcar-gen2-common.h"
  19
  20 #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
  21 #define CONFIG_SYS_TEXT_BASE    0x70000000
  22 #else
  23 #define CONFIG_SYS_TEXT_BASE    0xE6304000
  24 #endif
  25
  26 #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
  27 #define CONFIG_SYS_INIT_SP_ADDR         0x7003FFFC
  28 #else
  29 #define CONFIG_SYS_INIT_SP_ADDR         0xE633fffC
  30 #endif
  31 #define STACK_AREA_SIZE                 0xC000
  32 #define LOW_LEVEL_MERAM_STACK \
  33                 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
  34
  35 /* MEMORY */
  36 #define RCAR_GEN2_SDRAM_BASE            0x40000000
  37 #define RCAR_GEN2_SDRAM_SIZE            (2048u * 1024 * 1024)
  38 #define RCAR_GEN2_UBOOT_SDRAM_SIZE      (1024u * 1024 * 1024)
  39
  40 /* SCIF */
  41
  42 /* FLASH */
  43 #define CONFIG_SPI
  44 #define CONFIG_SH_QSPI
  45 #define CONFIG_SPI_FLASH_QUAD
  46
  47 /* SH Ether */
  48 #define CONFIG_SH_ETHER_USE_PORT        0
  49 #define CONFIG_SH_ETHER_PHY_ADDR        0x1
  50 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
  51 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
  52 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
  53 #define CONFIG_SH_ETHER_ALIGNE_SIZE     64
  54 #define CONFIG_BITBANGMII
  55 #define CONFIG_BITBANGMII_MULTI
  56
  57 /* Board Clock */
  58 #define RMOBILE_XTAL_CLK        20000000u
  59 #define CONFIG_SYS_CLK_FREQ     RMOBILE_XTAL_CLK
  60 #define CONFIG_SH_TMU_CLK_FREQ  (CONFIG_SYS_CLK_FREQ / 2)
  61 #define CONFIG_PLL1_CLK_FREQ    (CONFIG_SYS_CLK_FREQ * 156 / 2)
  62 #define CONFIG_P_CLK_FREQ       (CONFIG_PLL1_CLK_FREQ / 24)
  63
  64 #define CONFIG_SYS_TMU_CLK_DIV  4
  65
  66 /* i2c */
  67 #define CONFIG_SYS_I2C
  68 #define CONFIG_SYS_I2C_SH
  69 #define CONFIG_SYS_I2C_SLAVE            0x7F
  70 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS       3
  71 #define CONFIG_SYS_I2C_SH_SPEED0        400000
  72 #define CONFIG_SYS_I2C_SH_SPEED1        400000
  73 #define CONFIG_SYS_I2C_SH_SPEED2        400000
  74 #define CONFIG_SH_I2C_DATA_HIGH         4
  75 #define CONFIG_SH_I2C_DATA_LOW          5
  76 #define CONFIG_SH_I2C_CLOCK             10000000
  77
  78 #define CONFIG_SYS_I2C_POWERIC_ADDR     0x58 /* da9063 */
  79
  80 /* USB */
  81 #define CONFIG_USB_EHCI_RMOBILE
  82 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  83
  84 /* SD */
  85 #define CONFIG_SH_SDHI_FREQ     97500000
  86
  87 /* Module stop status bits */
  88 /* INTC-RT */
  89 #define CONFIG_SMSTP0_ENA       0x00400000
  90 /* MSIF */
  91 #define CONFIG_SMSTP2_ENA       0x00002000
  92 /* INTC-SYS, IRQC */
  93 #define CONFIG_SMSTP4_ENA       0x00000180
  94 /* SCIF0 */
  95 #define CONFIG_SMSTP7_ENA       0x00200000
  96
  97 #endif /* __PORTER_H */