include/configs/ppmc8260.h

   1 /*
   2  * (C) Copyright 2000
   3  * Murray Jensen <Murray.Jensen@cmst.csiro.au>
   4  *
   5  * (C) Copyright 2000
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * (C) Copyright 2001
  10  * Advent Networks, Inc. <http://www.adventnetworks.com>
  11  * Jay Monkman <jtm@smoothsmoothie.com>
  12  *
  13  * Configuation settings for the WindRiver PPMC8260 board.
  14  *
  15  * See file CREDITS for list of people who contributed to this
  16  * project.
  17  *
  18  * This program is free software; you can redistribute it and/or
  19  * modify it under the terms of the GNU General Public License as
  20  * published by the Free Software Foundation; either version 2 of
  21  * the License, or (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  31  * MA 02111-1307 USA
  32  */
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 /*****************************************************************************
  38  *
  39  * These settings must match the way _your_ board is set up
  40  *
  41  *****************************************************************************/
  42
  43 /* What is the oscillator's (UX2) frequency in Hz? */
  44 #define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
  45
  46 /*-----------------------------------------------------------------------
  47  * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
  48  *-----------------------------------------------------------------------
  49  * What should MODCK_H be? It is dependent on the oscillator
  50  * frequency, MODCK[1-3], and desired CPM and core frequencies.
  51  * Here are some example values (all frequencies are in MHz):
  52  *
  53  * MODCK_H   MODCK[1-3]  Osc    CPM    Core  S2-6   S2-7   S2-8
  54  * -------   ----------  ---    ---    ----  -----  -----  -----
  55  * 0x2       0x2         33     133    133   Close  Open   Close
  56  * 0x2       0x3         33     133    166   Close  Open   Open
  57  * 0x2       0x4         33     133    200   Open   Close  Close
  58  * 0x2       0x5         33     133    233   Open   Close  Open
  59  * 0x2       0x6         33     133    266   Open   Open   Close
  60  *
  61  * 0x5       0x5         66     133    133   Open   Close  Open
  62  * 0x5       0x6         66     133    166   Open   Open   Close
  63  * 0x5       0x7         66     133    200   Open   Open   Open
  64  * 0x6       0x0         66     133    233   Close  Close  Close
  65  * 0x6       0x1         66     133    266   Close  Close  Open
  66  * 0x6       0x2         66     133    300   Close  Open   Close
  67  */
  68 #define CONFIG_SYS_PPMC_MODCK_H 0x05
  69
  70 /* Define this if you want to boot from 0x00000100. If you don't define
  71  * this, you will need to program the bootloader to 0xfff00000, and
  72  * get the hardware reset config words at 0xfe000000. The simplest
  73  * way to do that is to program the bootloader at both addresses.
  74  * It is suggested that you just let U-Boot live at 0x00000000.
  75  */
  76 #define CONFIG_SYS_PPMC_BOOT_LOW 1
  77
  78 /* What should the base address of the main FLASH be and how big is
  79  * it (in MBytes)? This must contain TEXT_BASE from board/ppmc8260/config.mk
  80  * The main FLASH is whichever is connected to *CS0. U-Boot expects
  81  * this to be the SIMM.
  82  */
  83 #define CONFIG_SYS_FLASH0_BASE 0xFE000000
  84 #define CONFIG_SYS_FLASH0_SIZE 16
  85
  86 /* What should be the base address of the first SDRAM DIMM and how big is
  87  * it (in Mbytes)?
  88 */
  89 #define CONFIG_SYS_SDRAM0_BASE 0x00000000
  90 #define CONFIG_SYS_SDRAM0_SIZE 128
  91
  92 /* What should be the base address of the second SDRAM DIMM and how big is
  93  * it (in Mbytes)?
  94 */
  95 #define CONFIG_SYS_SDRAM1_BASE 0x08000000
  96 #define CONFIG_SYS_SDRAM1_SIZE 128
  97
  98 /* What should be the base address of the on board SDRAM and how big is
  99  * it (in Mbytes)?
 100 */
 101 #define CONFIG_SYS_SDRAM2_BASE 0x38000000
 102 #define CONFIG_SYS_SDRAM2_SIZE 16
 103
 104 /* What should be the base address of the MAILBOX  and how big is it
 105  * (in Bytes)
 106  * The eeprom lives at CONFIG_SYS_MAILBOX_BASE + 0x80000000
 107  */
 108 #define CONFIG_SYS_MAILBOX_BASE 0x32000000
 109 #define CONFIG_SYS_MAILBOX_SIZE 8192
 110
 111 /* What is the base address of the I/O select lines and how big is it
 112  * (In Mbytes)?
 113  */
 114
 115 #define CONFIG_SYS_IOSELECT_BASE 0xE0000000
 116 #define CONFIG_SYS_IOSELECT_SIZE 32
 117
 118
 119 /* What should be the base address of the LEDs and switch S0?
 120  * If you don't want them enabled, don't define this.
 121  */
 122 #define CONFIG_SYS_LED_BASE 0xF1000000
 123
 124 /*
 125  * PPMC8260 with 256 16 MB DIMM:
 126  *
 127  *     0x0000 0000     Exception Vector code, 8k
 128  *           :
 129  *     0x0000 1FFF
 130  *     0x0000 2000     Free for Application Use
 131  *           :
 132  *           :
 133  *
 134  *           :
 135  *           :
 136  *     0x0FF5 FF30     Monitor Stack (Growing downward)
 137  *                     Monitor Stack Buffer (0x80)
 138  *     0x0FF5 FFB0     Board Info Data
 139  *     0x0FF6 0000     Malloc Arena
 140  *           :              CONFIG_ENV_SECT_SIZE, 256k
 141  *           :              CONFIG_SYS_MALLOC_LEN,    128k
 142  *     0x0FFC 0000     RAM Copy of Monitor Code
 143  *           :              CONFIG_SYS_MONITOR_LEN,   256k
 144  *     0x0FFF FFFF     [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
 145  */
 146
 147
 148 /*
 149  * select serial console configuration
 150  *
 151  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 152  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 153  * for SCC).
 154  *
 155  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 156  * defined elsewhere.
 157  * The console can be on SMC1 or SMC2
 158  */
 159 #define CONFIG_CONS_ON_SMC      1       /* define if console on SMC */
 160 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
 161 #undef  CONFIG_CONS_NONE                /* define if console on neither */
 162 #define CONFIG_CONS_INDEX       1       /* which SMC/SCC channel for console */
 163
 164 /*
 165  * select ethernet configuration
 166  *
 167  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 168  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 169  * for FCC)
 170  *
 171  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 172  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 173  */
 174
 175 #undef  CONFIG_ETHER_ON_SCC             /* define if ethernet on SCC    */
 176 #define CONFIG_ETHER_ON_FCC             /* define if ethernet on FCC    */
 177 #undef  CONFIG_ETHER_NONE               /* define if ethernet on neither */
 178 #define CONFIG_ETHER_INDEX      2       /* which SCC/FCC channel for ethernet */
 179 #define CONFIG_MII                      /* MII PHY management   */
 180 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
 181 /*
 182  * Port pins used for bit-banged MII communictions (if applicable).
 183  */
 184 #define MDIO_PORT       2       /* Port C */
 185 #define MDIO_DECLARE    volatile ioport_t *iop = ioport_addr ( \
 186                                 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 187 #define MDC_DECLARE     MDIO_DECLARE
 188
 189 #define MDIO_ACTIVE     (iop->pdir |=  0x00400000)
 190 #define MDIO_TRISTATE   (iop->pdir &= ~0x00400000)
 191 #define MDIO_READ       ((iop->pdat &  0x00400000) != 0)
 192
 193 #define MDIO(bit)       if(bit) iop->pdat |=  0x00400000; \
 194                         else    iop->pdat &= ~0x00400000
 195
 196 #define MDC(bit)        if(bit) iop->pdat |=  0x00200000; \
 197                         else    iop->pdat &= ~0x00200000
 198
 199 #define MIIDELAY        udelay(1)
 200
 201
 202 /* Define this to reserve an entire FLASH sector (256 KB) for
 203  * environment variables. Otherwise, the environment will be
 204  * put in the same sector as U-Boot, and changing variables
 205  * will erase U-Boot temporarily
 206  */
 207 #define CONFIG_ENV_IN_OWN_SECT  1
 208
 209 /* Define to allow the user to overwrite serial and ethaddr */
 210 #define CONFIG_ENV_OVERWRITE
 211
 212 /* What should the console's baud rate be? */
 213 #define CONFIG_BAUDRATE         9600
 214
 215 /* Ethernet MAC address */
 216
 217 #define CONFIG_ETHADDR          00:a0:1e:90:2b:00
 218
 219 /* Define this to set the last octet of the ethernet address
 220  * from the DS0-DS7 switch and light the leds with the result
 221  * The DS0-DS7 switch and the leds are backwards with respect
 222  * to each other. DS7 is on the board edge side of both the
 223  * led strip and the DS0-DS7 switch.
 224  */
 225 #define CONFIG_MISC_INIT_R
 226
 227 /* Set to a positive value to delay for running BOOTCOMMAND */
 228 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 229
 230 #if 0
 231 /* Be selective on what keys can delay or stop the autoboot process
 232  *     To stop  use: " "
 233  */
 234 # define CONFIG_AUTOBOOT_KEYED
 235 # define CONFIG_AUTOBOOT_PROMPT \
 236         "Autobooting in %d seconds, press \" \" to stop\n", bootdelay
 237 # define CONFIG_AUTOBOOT_STOP_STR       " "
 238 # undef CONFIG_AUTOBOOT_DELAY_STR
 239 # define DEBUG_BOOTKEYS         0
 240 #endif
 241
 242 /* Define a command string that is automatically executed when no character
 243  * is read on the console interface withing "Boot Delay" after reset.
 244  */
 245 #undef  CONFIG_BOOT_ROOT_INITRD         /* Use ram disk for the root file system */
 246 #define CONFIG_BOOT_ROOT_NFS            /* Use a NFS mounted root file system */
 247
 248 #ifdef CONFIG_BOOT_ROOT_INITRD
 249 #define CONFIG_BOOTCOMMAND \
 250         "version;" \
 251         "echo;" \
 252         "bootp;" \
 253         "setenv bootargs root=/dev/ram0 rw " \
 254         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
 255         "bootm"
 256 #endif /* CONFIG_BOOT_ROOT_INITRD */
 257
 258 #ifdef CONFIG_BOOT_ROOT_NFS
 259 #define CONFIG_BOOTCOMMAND \
 260         "version;" \
 261         "echo;" \
 262         "bootp;" \
 263         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
 264         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
 265         "bootm"
 266 #endif /* CONFIG_BOOT_ROOT_NFS */
 267
 268
 269 /*
 270  * BOOTP options
 271  */
 272 #define CONFIG_BOOTP_SUBNETMASK
 273 #define CONFIG_BOOTP_GATEWAY
 274 #define CONFIG_BOOTP_HOSTNAME
 275 #define CONFIG_BOOTP_BOOTPATH
 276 #define CONFIG_BOOTP_BOOTFILESIZE
 277 #define CONFIG_BOOTP_DNS
 278
 279
 280 /* undef this to save memory */
 281 #define CONFIG_SYS_LONGHELP
 282
 283 /* Monitor Command Prompt */
 284 #define CONFIG_SYS_PROMPT               "=> "
 285
 286
 287 /*
 288  * Command line configuration.
 289  */
 290 #include <config_cmd_default.h>
 291
 292 #define CONFIG_CMD_ELF
 293 #define CONFIG_CMD_ASKENV
 294 #define CONFIG_CMD_REGINFO
 295 #define CONFIG_CMD_MEMTEST
 296 #define CONFIG_CMD_MII
 297 #define CONFIG_CMD_IMMAP
 298
 299 #undef CONFIG_CMD_KGDB
 300
 301
 302 /* Where do the internal registers live? */
 303 #define CONFIG_SYS_IMMR         0xf0000000
 304
 305 /*****************************************************************************
 306  *
 307  * You should not have to modify any of the following settings
 308  *
 309  *****************************************************************************/
 310
 311 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
 312 #define CONFIG_PPMC8260         1       /* on an Wind River PPMC8260 Board  */
 313 #define CONFIG_CPM2             1       /* Has a CPM2 */
 314
 315 /*
 316  * Miscellaneous configurable options
 317  */
 318 #if defined(CONFIG_CMD_KGDB)
 319 #  define CONFIG_SYS_CBSIZE             1024    /* Console I/O Buffer Size           */
 320 #else
 321 #  define CONFIG_SYS_CBSIZE             256     /* Console I/O Buffer Size           */
 322 #endif
 323
 324 /* Print Buffer Size */
 325 #define CONFIG_SYS_PBSIZE         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
 326
 327 #define CONFIG_SYS_MAXARGS              32      /* max number of command args   */
 328
 329 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size     */
 330
 331 #define CONFIG_SYS_LOAD_ADDR            0x140000   /* default load address */
 332 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 333
 334 #define CONFIG_SYS_MEMTEST_START        0x2000  /* memtest works from the end of */
 335                                         /* the exception vector table */
 336                                         /* to the end of the DRAM  */
 337                                         /* less monitor and malloc area */
 338 #define CONFIG_SYS_STACK_USAGE          0x10000 /* Reserve 64k for the stack usage */
 339 #define CONFIG_SYS_MEM_END_USAGE        ( CONFIG_SYS_MONITOR_LEN \
 340                                 + CONFIG_SYS_MALLOC_LEN \
 341                                 + CONFIG_ENV_SECT_SIZE \
 342                                 + CONFIG_SYS_STACK_USAGE )
 343
 344 #define CONFIG_SYS_MEMTEST_END          ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
 345                                 - CONFIG_SYS_MEM_END_USAGE )
 346
 347 /* valid baudrates */
 348 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 349
 350 /*
 351  * Low Level Configuration Settings
 352  * (address mappings, register initial values, etc.)
 353  * You should know what you are doing if you make changes here.
 354  */
 355
 356 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
 357 /*
 358  *  Attention: This is board specific
 359  *  - RX clk is CLK11
 360  *  - TX clk is CLK12
 361  */
 362 #define CONFIG_SYS_CMXSCR_VALUE       (CMXSCR_RS1CS_CLK11  |\
 363                                 CMXSCR_TS1CS_CLK12)
 364
 365 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 366 /*
 367  * Attention: this is board-specific
 368  * - Rx-CLK is CLK13
 369  * - Tx-CLK is CLK14
 370  * - Select bus for bd/buffers (see 28-13)
 371  * - Enable Full Duplex in FSMR
 372  */
 373 #define CONFIG_SYS_CMXFCR_MASK          (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 374 #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 375 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
 376 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
 377 #endif  /* CONFIG_ETHER_INDEX */
 378
 379 #define CONFIG_SYS_FLASH_BASE   CONFIG_SYS_FLASH0_BASE
 380 #define CONFIG_SYS_FLASH_SIZE   CONFIG_SYS_FLASH0_SIZE
 381 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_SDRAM0_BASE
 382 #define CONFIG_SYS_SDRAM_SIZE   (CONFIG_SYS_SDRAM0_SIZE + CONFIG_SYS_SDRAM1_SIZE)
 383
 384 /*-----------------------------------------------------------------------
 385  * Hard Reset Configuration Words
 386  */
 387 #if defined(CONFIG_SYS_PPMC_BOOT_LOW)
 388 #  define  CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 389 #else
 390 #  define  CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS  (0)
 391 #endif /* defined(CONFIG_SYS_PPMC_BOOT_LOW) */
 392
 393 /* get the HRCW ISB field from CONFIG_SYS_IMMR */
 394 #define CONFIG_SYS_PPMC_HRCW_IMMR       ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
 395                                   ((CONFIG_SYS_IMMR & 0x01000000) >>  7) | \
 396                                   ((CONFIG_SYS_IMMR & 0x00100000) >>  4) )
 397
 398 #define CONFIG_SYS_HRCW_MASTER          ( HRCW_EBM                              | \
 399                                   HRCW_BPS11                            | \
 400                                   HRCW_L2CPC10                          | \
 401                                   HRCW_DPPC00                           | \
 402                                   CONFIG_SYS_PPMC_HRCW_IMMR                     | \
 403                                   HRCW_MMR00                            | \
 404                                   HRCW_LBPC00                           | \
 405                                   HRCW_APPC10                           | \
 406                                   HRCW_CS10PC00                         | \
 407                                   (CONFIG_SYS_PPMC_MODCK_H & HRCW_MODCK_H1111) | \
 408                                   CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS )
 409
 410 /* no slaves */
 411 #define CONFIG_SYS_HRCW_SLAVE1          0
 412 #define CONFIG_SYS_HRCW_SLAVE2          0
 413 #define CONFIG_SYS_HRCW_SLAVE3          0
 414 #define CONFIG_SYS_HRCW_SLAVE4          0
 415 #define CONFIG_SYS_HRCW_SLAVE5          0
 416 #define CONFIG_SYS_HRCW_SLAVE6          0
 417 #define CONFIG_SYS_HRCW_SLAVE7          0
 418
 419 /*-----------------------------------------------------------------------
 420  * Definitions for initial stack pointer and data area (in DPRAM)
 421  */
 422 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 423 #define CONFIG_SYS_INIT_RAM_END 0x4000  /* End of used area in DPRAM    */
 424 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* bytes reserved for initial data */
 425 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 426 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 427
 428 /*-----------------------------------------------------------------------
 429  * Start addresses for the final memory configuration
 430  * (Set up by the startup code)
 431  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 432  * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
 433  */
 434 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
 435
 436 #ifndef CONFIG_SYS_MONITOR_BASE
 437 #define CONFIG_SYS_MONITOR_BASE 0x0ff80000
 438 #endif
 439
 440 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 441 #  define CONFIG_SYS_RAMBOOT
 442 #endif
 443
 444 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 374 kB for Monitor   */
 445 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 446
 447 /*
 448  * For booting Linux, the board info and command line data
 449  * have to be in the first 8 MB of memory, since this is
 450  * the maximum mapped by the Linux kernel during initialization.
 451  */
 452 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 453
 454 /*-----------------------------------------------------------------------
 455  * FLASH and environment organization
 456  */
 457
 458 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant              */
 459 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver                */
 460 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max number of sectors on one chip    */
 461 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 462 #define CONFIG_SYS_FLASH_INCREMENT      0       /* there is only one bank               */
 463 #define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware protection              */
 464 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
 465
 466
 467 #ifndef CONFIG_SYS_RAMBOOT
 468
 469 #  define CONFIG_ENV_IS_IN_FLASH        1
 470 #  ifdef CONFIG_ENV_IN_OWN_SECT
 471 #    define CONFIG_ENV_ADDR     (CONFIG_SYS_MONITOR_BASE + 0x40000)
 472 #    define CONFIG_ENV_SECT_SIZE        0x40000
 473 #  else
 474 #    define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
 475 #    define CONFIG_ENV_SIZE     0x1000  /* Total Size of Environment Sector     */
 476 #    define CONFIG_ENV_SECT_SIZE        0x40000 /* see README - env sect real size      */
 477 #  endif /* CONFIG_ENV_IN_OWN_SECT */
 478
 479 #else
 480 #  define CONFIG_ENV_IS_IN_FLASH        1
 481 #  define CONFIG_ENV_ADDR               (CONFIG_SYS_FLASH_BASE + 0x40000)
 482 #define CONFIG_ENV_SIZE         0x1000
 483 #  define CONFIG_ENV_SECT_SIZE  0x40000
 484 #endif /* CONFIG_SYS_RAMBOOT */
 485
 486 /*-----------------------------------------------------------------------
 487  * Cache Configuration
 488  */
 489 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPU */
 490
 491 #if defined(CONFIG_CMD_KGDB)
 492 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 493 #endif
 494
 495 /*-----------------------------------------------------------------------
 496  * HIDx - Hardware Implementation-dependent Registers                    2-11
 497  *-----------------------------------------------------------------------
 498  * HID0 also contains cache control - initially enable both caches and
 499  * invalidate contents, then the final state leaves only the instruction
 500  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 501  * but Soft reset does not.
 502  *
 503  * HID1 has only read-only information - nothing to set.
 504  */
 505 #define CONFIG_SYS_HID0_INIT    (HID0_ICE  |\
 506                          HID0_DCE  |\
 507                          HID0_ICFI |\
 508                          HID0_DCI  |\
 509                          HID0_IFEM |\
 510                          HID0_ABE)
 511
 512 #define CONFIG_SYS_HID0_FINAL   (HID0_ICE  |\
 513                          HID0_IFEM |\
 514                          HID0_ABE  |\
 515                          HID0_EMCP)
 516 #define CONFIG_SYS_HID2 0
 517
 518 /*-----------------------------------------------------------------------
 519  * RMR - Reset Mode Register
 520  *-----------------------------------------------------------------------
 521  */
 522 #define CONFIG_SYS_RMR          0
 523
 524 /*-----------------------------------------------------------------------
 525  * BCR - Bus Configuration                                       4-25
 526  *-----------------------------------------------------------------------
 527  */
 528 #define CONFIG_SYS_BCR          (BCR_EBM      |\
 529                          0x30000000)
 530
 531 /*-----------------------------------------------------------------------
 532  * SIUMCR - SIU Module Configuration                             4-31
 533  * Ref Section 4.3.2.6  page 4-31
 534  *-----------------------------------------------------------------------
 535  */
 536
 537 #define CONFIG_SYS_SIUMCR       (SIUMCR_ESE      |\
 538                          SIUMCR_DPPC00   |\
 539                          SIUMCR_L2CPC10  |\
 540                          SIUMCR_LBPC00   |\
 541                          SIUMCR_APPC10   |\
 542                          SIUMCR_CS10PC00 |\
 543                          SIUMCR_BCTLC00  |\
 544                          SIUMCR_MMR00)
 545
 546
 547 /*-----------------------------------------------------------------------
 548  * SYPCR - System Protection Control                            11-9
 549  * SYPCR can only be written once after reset!
 550  *-----------------------------------------------------------------------
 551  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 552  */
 553 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC |\
 554                          SYPCR_BMT  |\
 555                          SYPCR_PBME |\
 556                          SYPCR_LBME |\
 557                          SYPCR_SWRI |\
 558                          SYPCR_SWP)
 559
 560 /*-----------------------------------------------------------------------
 561  * TMCNTSC - Time Counter Status and Control                     4-40
 562  *-----------------------------------------------------------------------
 563  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 564  * and enable Time Counter
 565  */
 566 #define CONFIG_SYS_TMCNTSC      (TMCNTSC_SEC |\
 567                          TMCNTSC_ALR |\
 568                          TMCNTSC_TCF |\
 569                          TMCNTSC_TCE)
 570
 571 /*-----------------------------------------------------------------------
 572  * PISCR - Periodic Interrupt Status and Control                 4-42
 573  *-----------------------------------------------------------------------
 574  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 575  * Periodic timer
 576  */
 577 #define CONFIG_SYS_PISCR        (PISCR_PS  |\
 578                          PISCR_PTF |\
 579                          PISCR_PTE)
 580
 581 /*-----------------------------------------------------------------------
 582  * SCCR - System Clock Control                                   9-8
 583  *-----------------------------------------------------------------------
 584  */
 585 #define CONFIG_SYS_SCCR 0
 586
 587 /*-----------------------------------------------------------------------
 588  * RCCR - RISC Controller Configuration                         13-7
 589  *-----------------------------------------------------------------------
 590  */
 591 #define CONFIG_SYS_RCCR 0
 592
 593 /*
 594  * Initialize Memory Controller:
 595  *
 596  * Bank Bus     Machine PortSz  Device
 597  * ---- ---     ------- ------  ------
 598  *  0   60x     GPCM    32 bit  FLASH (SIMM - 32MB) *
 599  *  1   unused
 600  *  2   60x     SDRAM   64 bit  SDRAM (DIMM - 128MB)
 601  *  3   60x     SDRAM   64 bit  SDRAM (DIMM - 128MB)
 602  *  4   Local   SDRAM   32 bit  SDRAM (on board - 16MB)
 603  *  5   60x     GPCM     8 bit  Mailbox/EEPROM (8KB)
 604  *  6   60x     GPCM     8 bit  FLASH  (on board - 2MB) *
 605  *  7   60x     GPCM     8 bit  LEDs, switches
 606  *
 607  *  (*) This configuration requires the PPMC8260 be configured
 608  *      so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
 609  *      the on board FLASH. In other words, JP24 should have
 610  *      pins 1 and 2 jumpered and pins 3 and 4 jumpered.
 611  *
 612  */
 613
 614 /*-----------------------------------------------------------------------
 615  * BR0,BR1 - Base Register
 616  *     Ref: Section 10.3.1 on page 10-14
 617  * OR0,OR1 - Option Register
 618  *     Ref: Section 10.3.2 on page 10-18
 619  *-----------------------------------------------------------------------
 620  */
 621
 622 /* Bank 0,1 - FLASH SIMM
 623  *
 624  * This expects the FLASH SIMM to be connected to *CS0
 625  * It consists of 4 AM29F080B parts.
 626  *
 627  * Note: For the 4 MB SIMM, *CS1 is unused.
 628  */
 629
 630 /* BR0 is configured as follows:
 631  *
 632  *     - Base address of 0xFE000000
 633  *     - 32 bit port size
 634  *     - Data errors checking is disabled
 635  *     - Read and write access
 636  *     - GPCM 60x bus
 637  *     - Access are handled by the memory controller according to MSEL
 638  *     - Not used for atomic operations
 639  *     - No data pipelining is done
 640  *     - Valid
 641  */
 642 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
 643                          BRx_PS_32                      |\
 644                          BRx_MS_GPCM_P                  |\
 645                          BRx_V)
 646
 647 /* OR0 is configured as follows:
 648  *
 649  *     - 32 MB
 650  *     - *BCTL0 is asserted upon access to the current memory bank
 651  *     - *CW / *WE are negated a quarter of a clock earlier
 652  *     - *CS is output at the same time as the address lines
 653  *     - Uses a clock cycle length of 5
 654  *     - *PSDVAL is generated internally by the memory controller
 655  *       unless *GTA is asserted earlier externally.
 656  *     - Relaxed timing is generated by the GPCM for accesses
 657  *       initiated to this memory region.
 658  *     - One idle clock is inserted between a read access from the
 659  *       current bank and the next access.
 660  */
 661 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE)      |\
 662                          ORxG_CSNT                      |\
 663                          ORxG_ACS_DIV1                  |\
 664                          ORxG_SCY_5_CLK                 |\
 665                          ORxG_TRLX                      |\
 666                          ORxG_EHTR)
 667
 668 /*-----------------------------------------------------------------------
 669  * BR2,BR3 - Base Register
 670  *     Ref: Section 10.3.1 on page 10-14
 671  * OR2,OR3 - Option Register
 672  *     Ref: Section 10.3.2 on page 10-16
 673  *-----------------------------------------------------------------------
 674  */
 675
 676 /*
 677  * Bank 2,3 - 128 MB SDRAM DIMM
 678  */
 679
 680 /* With a 128 MB DIMM, the BR2 is configured as follows:
 681  *
 682  *     - Base address of 0x00000000/0x08000000
 683  *     - 64 bit port size (60x bus only)
 684  *     - Data errors checking is disabled
 685  *     - Read and write access
 686  *     - SDRAM 60x bus
 687  *     - Access are handled by the memory controller according to MSEL
 688  *     - Not used for atomic operations
 689  *     - No data pipelining is done
 690  *     - Valid
 691  */
 692 #define CONFIG_SYS_BR2_PRELIM   ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
 693                          BRx_PS_64                      |\
 694                          BRx_MS_SDRAM_P                 |\
 695                          BRx_V)
 696
 697 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
 698                          BRx_PS_64                      |\
 699                          BRx_MS_SDRAM_P                 |\
 700                          BRx_V)
 701
 702 /* With a 128 MB DIMM, the OR2 is configured as follows:
 703  *
 704  *     - 128 MB
 705  *     - 4 internal banks per device
 706  *     - Row start address bit is A8 with PSDMR[PBI] = 0
 707  *     - 13 row address lines
 708  *     - Back-to-back page mode
 709  *     - Internal bank interleaving within save device enabled
 710  */
 711
 712 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE)      |\
 713                          ORxS_BPD_4                     |\
 714                          ORxS_ROWST_PBI0_A7             |\
 715                          ORxS_NUMR_13)
 716
 717 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE)      |\
 718                          ORxS_BPD_4                     |\
 719                          ORxS_ROWST_PBI0_A7             |\
 720                          ORxS_NUMR_13)
 721
 722
 723 /*-----------------------------------------------------------------------
 724  * PSDMR - 60x Bus SDRAM Mode Register
 725  *     Ref: Section 10.3.3 on page 10-21
 726  *-----------------------------------------------------------------------
 727  */
 728
 729 /* With a 128 MB DIMM, the PSDMR is configured as follows:
 730  *
 731  *     - Page Based Interleaving,
 732  *     - Refresh Enable,
 733  *     - Normal Operation
 734  *     - Address Multiplexing where A5 is output on A14 pin
 735  *       (A6 on A15, and so on),
 736  *     - use address pins A13-A15 as bank select,
 737  *     - A9 is output on SDA10 during an ACTIVATE command,
 738  *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
 739  *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
 740  *       is 3 clocks,
 741  *     - earliest timing for READ/WRITE command after ACTIVATE command is
 742  *       2 clocks,
 743  *     - earliest timing for PRECHARGE after last data was read is 1 clock,
 744  *     - earliest timing for PRECHARGE after last data was written is 1 clock,
 745  *     - External Address Multiplexing enabled
 746  *     - CAS Latency is 2.
 747  */
 748 #define CONFIG_SYS_PSDMR        (PSDMR_RFEN           |\
 749                          PSDMR_SDAM_A14_IS_A5 |\
 750                          PSDMR_BSMA_A13_A15   |\
 751                          PSDMR_SDA10_PBI0_A9  |\
 752                          PSDMR_RFRC_7_CLK     |\
 753                          PSDMR_PRETOACT_3W    |\
 754                          PSDMR_ACTTORW_2W     |\
 755                          PSDMR_LDOTOPRE_1C    |\
 756                          PSDMR_WRC_1C         |\
 757                          PSDMR_EAMUX          |\
 758                          PSDMR_CL_2)
 759
 760
 761 #define CONFIG_SYS_PSRT 0x0e
 762 #define CONFIG_SYS_MPTPR        MPTPR_PTP_DIV32
 763
 764
 765 /*-----------------------------------------------------------------------
 766  * BR4 - Base Register
 767  *     Ref: Section 10.3.1 on page 10-14
 768  * OR4 - Option Register
 769  *     Ref: Section 10.3.2 on page 10-16
 770  *-----------------------------------------------------------------------
 771  */
 772
 773 /*
 774  * Bank 4 - On board SDRAM
 775  *
 776  */
 777 /* With 16 MB of onboard SDRAM  BR4 is configured as follows
 778  *
 779  *     - Base address 0x38000000
 780  *     - 32 bit port size
 781  *     - Data error checking disabled
 782  *     - Read/Write access
 783  *     - SDRAM local bus
 784  *     - Not used for atomic operations
 785  *     - No data pipelining is done
 786  *     - Valid
 787  *
 788  */
 789
 790 #define CONFIG_SYS_BR4_PRELIM   ((CONFIG_SYS_SDRAM2_BASE & BRx_BA_MSK) |\
 791                          BRx_PS_32                      |\
 792                          BRx_DECC_NONE                  |\
 793                          BRx_MS_SDRAM_L                 |\
 794                          BRx_V)
 795
 796 /*
 797  * With 16MB SDRAM, OR4 is configured as follows
 798  *     - 4 internal banks per device
 799  *     - Row start address bit is A10 with LSDMR[PBI] = 0
 800  *     - 12 row address lines
 801  *     - Back-to-back page mode
 802  *     - Internal bank interleaving within save device enabled
 803  */
 804
 805 #define CONFIG_SYS_OR4_PRELIM   (MEG_TO_AM(CONFIG_SYS_SDRAM2_SIZE)      |\
 806                          ORxS_BPD_4                     |\
 807                          ORxS_ROWST_PBI0_A10            |\
 808                          ORxS_NUMR_12)
 809
 810
 811 /*-----------------------------------------------------------------------
 812  * LSDMR - Local Bus SDRAM Mode Register
 813  *     Ref: Section 10.3.4 on page 10-24
 814  *-----------------------------------------------------------------------
 815  */
 816
 817 /* With a 16 MB onboard SDRAM, the LSDMR is configured as follows:
 818  *
 819  *     - Page Based Interleaving,
 820  *     - Refresh Enable,
 821  *     - Normal Operation
 822  *     - Address Multiplexing where A5 is output on A13 pin
 823  *       (A6 on A15, and so on),
 824  *     - use address pins A15-A17 as bank select,
 825  *     - A11 is output on SDA10 during an ACTIVATE command,
 826  *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
 827  *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
 828  *       is 2 clocks,
 829  *     - earliest timing for READ/WRITE command after ACTIVATE command is
 830  *       2 clocks,
 831  *     - SDRAM burst length is 8
 832  *     - earliest timing for PRECHARGE after last data was read is 1 clock,
 833  *     - earliest timing for PRECHARGE after last data was written is 1 clock,
 834  *     - External Address Multiplexing disabled
 835  *     - CAS Latency is 2.
 836  */
 837 #define CONFIG_SYS_LSDMR        (PSDMR_RFEN           |\
 838                          PSDMR_SDAM_A13_IS_A5 |\
 839                          PSDMR_BSMA_A15_A17   |\
 840                          PSDMR_SDA10_PBI0_A11 |\
 841                          PSDMR_RFRC_7_CLK     |\
 842                          PSDMR_PRETOACT_2W    |\
 843                          PSDMR_ACTTORW_2W     |\
 844                          PSDMR_BL             |\
 845                          PSDMR_LDOTOPRE_1C    |\
 846                          PSDMR_WRC_1C         |\
 847                          PSDMR_CL_2)
 848
 849 #define CONFIG_SYS_LSRT 0x0e
 850
 851 /*-----------------------------------------------------------------------
 852  * BR5 - Base Register
 853  *     Ref: Section 10.3.1 on page 10-14
 854  * OR5 - Option Register
 855  *     Ref: Section 10.3.2 on page 10-16
 856  *-----------------------------------------------------------------------
 857  */
 858
 859 /*
 860  * Bank 5 EEProm and Mailbox
 861  *
 862  * The EEPROM and mailbox live on the same chip select.
 863  * the eeprom is selected if the MSb of the address is set and the mailbox is
 864  * selected if the MSb of the address is clear.
 865  *
 866  */
 867
 868 /* BR5 is configured as follows:
 869  *
 870  *     - Base address of 0x32000000/0xF2000000
 871  *     - 8 bit
 872  *     - Data error checking disabled
 873  *     - Read/Write access
 874  *     - GPCM 60x Bus
 875  *     - SDRAM local bus
 876  *     - No data pipelining is done
 877  *     - Valid
 878  */
 879
 880 #define CONFIG_SYS_BR5_PRELIM   ((CONFIG_SYS_MAILBOX_BASE & BRx_BA_MSK) |\
 881                          BRx_PS_8                        |\
 882                          BRx_DECC_NONE                   |\
 883                          BRx_MS_GPCM_P                   |\
 884                          BRx_V)
 885 /* OR5 is configured as follows
 886  *     - buffer control enabled
 887  *     - chip select negated normally
 888  *     - CS output 1/2 clock after address
 889  *     - 15 wait states
 890  *     - *PSDVAL is generated internally by the memory controller
 891  *       unless *GTA is asserted earlier externally.
 892  *     - Relaxed timing is generated by the GPCM for accesses
 893  *       initiated to this memory region.
 894  *     - One idle clock is inserted between a read access from the
 895  *       current bank and the next access.
 896  */
 897
 898 #define CONFIG_SYS_OR5_PRELIM ((P2SZ_TO_AM(CONFIG_SYS_MAILBOX_SIZE) & ~0x80000000) |\
 899                          ORxG_ACS_DIV2                               |\
 900                          ORxG_SCY_15_CLK                             |\
 901                          ORxG_TRLX                                   |\
 902                          ORxG_EHTR)
 903
 904 /*-----------------------------------------------------------------------
 905  * BR6 - Base Register
 906  *     Ref: Section 10.3.1 on page 10-14
 907  * OR6 - Option Register
 908  *     Ref: Section 10.3.2 on page 10-18
 909  *-----------------------------------------------------------------------
 910  */
 911
 912 /* Bank 6 - I/O select
 913  *
 914  */
 915
 916 /* BR6 is configured as follows:
 917  *
 918  *     - Base address of 0xE0000000
 919  *     - 16 bit port size
 920  *     - Data errors checking is disabled
 921  *     - Read and write access
 922  *     - GPCM 60x bus
 923  *     - Access are handled by the memory controller according to MSEL
 924  *     - Not used for atomic operations
 925  *     - No data pipelining is done
 926  *     - Valid
 927  */
 928 #define CONFIG_SYS_BR6_PRELIM   ((CONFIG_SYS_IOSELECT_BASE & BRx_BA_MSK) |\
 929                            BRx_PS_16                      |\
 930                            BRx_MS_GPCM_P                  |\
 931                            BRx_V)
 932
 933 /* OR6 is configured as follows
 934  *     - buffer control enabled
 935  *     - chip select negated normally
 936  *     - CS output 1/2 clock after address
 937  *     - 15 wait states
 938  *     - *PSDVAL is generated internally by the memory controller
 939  *       unless *GTA is asserted earlier externally.
 940  *     - Relaxed timing is generated by the GPCM for accesses
 941  *       initiated to this memory region.
 942  *     - One idle clock is inserted between a read access from the
 943  *       current bank and the next access.
 944  */
 945
 946 #define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_IOSELECT_SIZE) |\
 947                          ORxG_ACS_DIV2               |\
 948                          ORxG_SCY_15_CLK             |\
 949                          ORxG_TRLX                   |\
 950                          ORxG_EHTR)
 951
 952
 953 /*-----------------------------------------------------------------------
 954  * BR7 - Base Register
 955  *     Ref: Section 10.3.1 on page 10-14
 956  * OR7 - Option Register
 957  *     Ref: Section 10.3.2 on page 10-18
 958  *-----------------------------------------------------------------------
 959  */
 960
 961 /* Bank 7 - LEDs and switches
 962  *
 963  *  LEDs     are at 0x00001 (write only)
 964  *  switches are at 0x00001 (read only)
 965  */
 966 #ifdef CONFIG_SYS_LED_BASE
 967
 968 /* BR7 is configured as follows:
 969  *
 970  *     - Base address of 0xA0000000
 971  *     - 8 bit port size
 972  *     - Data errors checking is disabled
 973  *     - Read and write access
 974  *     - GPCM 60x bus
 975  *     - Access are handled by the memory controller according to MSEL
 976  *     - Not used for atomic operations
 977  *     - No data pipelining is done
 978  *     - Valid
 979  */
 980 #define CONFIG_SYS_BR7_PRELIM   ((CONFIG_SYS_LED_BASE & BRx_BA_MSK)      |\
 981                            BRx_PS_8                      |\
 982                            BRx_DECC_NONE                 |\
 983                            BRx_MS_GPCM_P                 |\
 984                            BRx_V)
 985
 986 /* OR7 is configured as follows:
 987  *
 988  *     - 1 byte
 989  *     - *BCTL0 is asserted upon access to the current memory bank
 990  *     - *CW / *WE are negated a quarter of a clock earlier
 991  *     - *CS is output at the same time as the address lines
 992  *     - Uses a clock cycle length of 15
 993  *     - *PSDVAL is generated internally by the memory controller
 994  *       unless *GTA is asserted earlier externally.
 995  *     - Relaxed timing is generated by the GPCM for accesses
 996  *       initiated to this memory region.
 997  *     - One idle clock is inserted between a read access from the
 998  *       current bank and the next access.
 999  */
1000 #define CONFIG_SYS_OR7_PRELIM   (ORxG_AM_MSK                   |\
1001                          ORxG_CSNT                     |\
1002                          ORxG_ACS_DIV1                 |\
1003                          ORxG_SCY_15_CLK               |\
1004                          ORxG_TRLX                     |\
1005                          ORxG_EHTR)
1006 #endif /* CONFIG_SYS_LED_BASE */
1007
1008 /*
1009  * Internal Definitions
1010  *
1011  * Boot Flags
1012  */
1013 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
1014 #define BOOTFLAG_WARM   0x02    /* Software reboot                   */
1015
1016 #endif  /* __CONFIG_H */