include/configs/ppmc8260.h

   1 /*
   2  * (C) Copyright 2000
   3  * Murray Jensen <Murray.Jensen@cmst.csiro.au>
   4  *
   5  * (C) Copyright 2000
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * (C) Copyright 2001
  10  * Advent Networks, Inc. <http://www.adventnetworks.com>
  11  * Jay Monkman <jtm@smoothsmoothie.com>
  12  *
  13  * Configuation settings for the WindRiver PPMC8260 board.
  14  *
  15  * See file CREDITS for list of people who contributed to this
  16  * project.
  17  *
  18  * This program is free software; you can redistribute it and/or
  19  * modify it under the terms of the GNU General Public License as
  20  * published by the Free Software Foundation; either version 2 of
  21  * the License, or (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  31  * MA 02111-1307 USA
  32  */
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 #define CONFIG_SYS_TEXT_BASE    0xfe000000
  38
  39 /*****************************************************************************
  40  *
  41  * These settings must match the way _your_ board is set up
  42  *
  43  *****************************************************************************/
  44
  45 /* What is the oscillator's (UX2) frequency in Hz? */
  46 #define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
  47
  48 /*-----------------------------------------------------------------------
  49  * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
  50  *-----------------------------------------------------------------------
  51  * What should MODCK_H be? It is dependent on the oscillator
  52  * frequency, MODCK[1-3], and desired CPM and core frequencies.
  53  * Here are some example values (all frequencies are in MHz):
  54  *
  55  * MODCK_H   MODCK[1-3]  Osc    CPM    Core  S2-6   S2-7   S2-8
  56  * -------   ----------  ---    ---    ----  -----  -----  -----
  57  * 0x2       0x2         33     133    133   Close  Open   Close
  58  * 0x2       0x3         33     133    166   Close  Open   Open
  59  * 0x2       0x4         33     133    200   Open   Close  Close
  60  * 0x2       0x5         33     133    233   Open   Close  Open
  61  * 0x2       0x6         33     133    266   Open   Open   Close
  62  *
  63  * 0x5       0x5         66     133    133   Open   Close  Open
  64  * 0x5       0x6         66     133    166   Open   Open   Close
  65  * 0x5       0x7         66     133    200   Open   Open   Open
  66  * 0x6       0x0         66     133    233   Close  Close  Close
  67  * 0x6       0x1         66     133    266   Close  Close  Open
  68  * 0x6       0x2         66     133    300   Close  Open   Close
  69  */
  70 #define CONFIG_SYS_PPMC_MODCK_H 0x05
  71
  72 /* Define this if you want to boot from 0x00000100. If you don't define
  73  * this, you will need to program the bootloader to 0xfff00000, and
  74  * get the hardware reset config words at 0xfe000000. The simplest
  75  * way to do that is to program the bootloader at both addresses.
  76  * It is suggested that you just let U-Boot live at 0x00000000.
  77  */
  78 #define CONFIG_SYS_PPMC_BOOT_LOW 1
  79
  80 /* What should the base address of the main FLASH be and how big is
  81  * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ppmc8260/config.mk
  82  * The main FLASH is whichever is connected to *CS0. U-Boot expects
  83  * this to be the SIMM.
  84  */
  85 #define CONFIG_SYS_FLASH0_BASE 0xFE000000
  86 #define CONFIG_SYS_FLASH0_SIZE 16
  87
  88 /* What should be the base address of the first SDRAM DIMM and how big is
  89  * it (in Mbytes)?
  90 */
  91 #define CONFIG_SYS_SDRAM0_BASE 0x00000000
  92 #define CONFIG_SYS_SDRAM0_SIZE 128
  93
  94 /* What should be the base address of the second SDRAM DIMM and how big is
  95  * it (in Mbytes)?
  96 */
  97 #define CONFIG_SYS_SDRAM1_BASE 0x08000000
  98 #define CONFIG_SYS_SDRAM1_SIZE 128
  99
 100 /* What should be the base address of the on board SDRAM and how big is
 101  * it (in Mbytes)?
 102 */
 103 #define CONFIG_SYS_SDRAM2_BASE 0x38000000
 104 #define CONFIG_SYS_SDRAM2_SIZE 16
 105
 106 /* What should be the base address of the MAILBOX  and how big is it
 107  * (in Bytes)
 108  * The eeprom lives at CONFIG_SYS_MAILBOX_BASE + 0x80000000
 109  */
 110 #define CONFIG_SYS_MAILBOX_BASE 0x32000000
 111 #define CONFIG_SYS_MAILBOX_SIZE 8192
 112
 113 /* What is the base address of the I/O select lines and how big is it
 114  * (In Mbytes)?
 115  */
 116
 117 #define CONFIG_SYS_IOSELECT_BASE 0xE0000000
 118 #define CONFIG_SYS_IOSELECT_SIZE 32
 119
 120
 121 /* What should be the base address of the LEDs and switch S0?
 122  * If you don't want them enabled, don't define this.
 123  */
 124 #define CONFIG_SYS_LED_BASE 0xF1000000
 125
 126 /*
 127  * PPMC8260 with 256 16 MB DIMM:
 128  *
 129  *     0x0000 0000     Exception Vector code, 8k
 130  *           :
 131  *     0x0000 1FFF
 132  *     0x0000 2000     Free for Application Use
 133  *           :
 134  *           :
 135  *
 136  *           :
 137  *           :
 138  *     0x0FF5 FF30     Monitor Stack (Growing downward)
 139  *                     Monitor Stack Buffer (0x80)
 140  *     0x0FF5 FFB0     Board Info Data
 141  *     0x0FF6 0000     Malloc Arena
 142  *           :              CONFIG_ENV_SECT_SIZE, 256k
 143  *           :              CONFIG_SYS_MALLOC_LEN,    128k
 144  *     0x0FFC 0000     RAM Copy of Monitor Code
 145  *           :              CONFIG_SYS_MONITOR_LEN,   256k
 146  *     0x0FFF FFFF     [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
 147  */
 148
 149
 150 /*
 151  * select serial console configuration
 152  *
 153  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 154  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 155  * for SCC).
 156  *
 157  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 158  * defined elsewhere.
 159  * The console can be on SMC1 or SMC2
 160  */
 161 #define CONFIG_CONS_ON_SMC      1       /* define if console on SMC */
 162 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
 163 #undef  CONFIG_CONS_NONE                /* define if console on neither */
 164 #define CONFIG_CONS_INDEX       1       /* which SMC/SCC channel for console */
 165
 166 /*
 167  * select ethernet configuration
 168  *
 169  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 170  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 171  * for FCC)
 172  *
 173  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 174  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 175  */
 176
 177 #undef  CONFIG_ETHER_ON_SCC             /* define if ethernet on SCC    */
 178 #define CONFIG_ETHER_ON_FCC             /* define if ethernet on FCC    */
 179 #undef  CONFIG_ETHER_NONE               /* define if ethernet on neither */
 180 #define CONFIG_ETHER_INDEX      2       /* which SCC/FCC channel for ethernet */
 181 #define CONFIG_MII                      /* MII PHY management   */
 182 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
 183 /*
 184  * Port pins used for bit-banged MII communictions (if applicable).
 185  */
 186 #define MDIO_PORT       2       /* Port C */
 187 #define MDIO_DECLARE    volatile ioport_t *iop = ioport_addr ( \
 188                                 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 189 #define MDC_DECLARE     MDIO_DECLARE
 190
 191 #define MDIO_ACTIVE     (iop->pdir |=  0x00400000)
 192 #define MDIO_TRISTATE   (iop->pdir &= ~0x00400000)
 193 #define MDIO_READ       ((iop->pdat &  0x00400000) != 0)
 194
 195 #define MDIO(bit)       if(bit) iop->pdat |=  0x00400000; \
 196                         else    iop->pdat &= ~0x00400000
 197
 198 #define MDC(bit)        if(bit) iop->pdat |=  0x00200000; \
 199                         else    iop->pdat &= ~0x00200000
 200
 201 #define MIIDELAY        udelay(1)
 202
 203
 204 /* Define this to reserve an entire FLASH sector (256 KB) for
 205  * environment variables. Otherwise, the environment will be
 206  * put in the same sector as U-Boot, and changing variables
 207  * will erase U-Boot temporarily
 208  */
 209 #define CONFIG_ENV_IN_OWN_SECT  1
 210
 211 /* Define to allow the user to overwrite serial and ethaddr */
 212 #define CONFIG_ENV_OVERWRITE
 213
 214 /* What should the console's baud rate be? */
 215 #define CONFIG_BAUDRATE         9600
 216
 217 /* Ethernet MAC address */
 218
 219 #define CONFIG_ETHADDR          00:a0:1e:90:2b:00
 220
 221 /* Define this to set the last octet of the ethernet address
 222  * from the DS0-DS7 switch and light the leds with the result
 223  * The DS0-DS7 switch and the leds are backwards with respect
 224  * to each other. DS7 is on the board edge side of both the
 225  * led strip and the DS0-DS7 switch.
 226  */
 227 #define CONFIG_MISC_INIT_R
 228
 229 /* Set to a positive value to delay for running BOOTCOMMAND */
 230 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 231
 232 #if 0
 233 /* Be selective on what keys can delay or stop the autoboot process
 234  *     To stop  use: " "
 235  */
 236 # define CONFIG_AUTOBOOT_KEYED
 237 # define CONFIG_AUTOBOOT_PROMPT \
 238         "Autobooting in %d seconds, press \" \" to stop\n", bootdelay
 239 # define CONFIG_AUTOBOOT_STOP_STR       " "
 240 # undef CONFIG_AUTOBOOT_DELAY_STR
 241 # define DEBUG_BOOTKEYS         0
 242 #endif
 243
 244 /* Define a command string that is automatically executed when no character
 245  * is read on the console interface withing "Boot Delay" after reset.
 246  */
 247 #undef  CONFIG_BOOT_ROOT_INITRD         /* Use ram disk for the root file system */
 248 #define CONFIG_BOOT_ROOT_NFS            /* Use a NFS mounted root file system */
 249
 250 #ifdef CONFIG_BOOT_ROOT_INITRD
 251 #define CONFIG_BOOTCOMMAND \
 252         "version;" \
 253         "echo;" \
 254         "bootp;" \
 255         "setenv bootargs root=/dev/ram0 rw " \
 256         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
 257         "bootm"
 258 #endif /* CONFIG_BOOT_ROOT_INITRD */
 259
 260 #ifdef CONFIG_BOOT_ROOT_NFS
 261 #define CONFIG_BOOTCOMMAND \
 262         "version;" \
 263         "echo;" \
 264         "bootp;" \
 265         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
 266         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
 267         "bootm"
 268 #endif /* CONFIG_BOOT_ROOT_NFS */
 269
 270
 271 /*
 272  * BOOTP options
 273  */
 274 #define CONFIG_BOOTP_SUBNETMASK
 275 #define CONFIG_BOOTP_GATEWAY
 276 #define CONFIG_BOOTP_HOSTNAME
 277 #define CONFIG_BOOTP_BOOTPATH
 278 #define CONFIG_BOOTP_BOOTFILESIZE
 279 #define CONFIG_BOOTP_DNS
 280
 281
 282 /* undef this to save memory */
 283 #define CONFIG_SYS_LONGHELP
 284
 285 /* Monitor Command Prompt */
 286 #define CONFIG_SYS_PROMPT               "=> "
 287
 288
 289 /*
 290  * Command line configuration.
 291  */
 292 #include <config_cmd_default.h>
 293
 294 #define CONFIG_CMD_ELF
 295 #define CONFIG_CMD_ASKENV
 296 #define CONFIG_CMD_REGINFO
 297 #define CONFIG_CMD_MEMTEST
 298 #define CONFIG_CMD_MII
 299 #define CONFIG_CMD_IMMAP
 300
 301 #undef CONFIG_CMD_KGDB
 302
 303
 304 /* Where do the internal registers live? */
 305 #define CONFIG_SYS_IMMR         0xf0000000
 306
 307 /*****************************************************************************
 308  *
 309  * You should not have to modify any of the following settings
 310  *
 311  *****************************************************************************/
 312
 313 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
 314 #define CONFIG_PPMC8260         1       /* on an Wind River PPMC8260 Board  */
 315 #define CONFIG_CPM2             1       /* Has a CPM2 */
 316
 317 /*
 318  * Miscellaneous configurable options
 319  */
 320 #if defined(CONFIG_CMD_KGDB)
 321 #  define CONFIG_SYS_CBSIZE             1024    /* Console I/O Buffer Size           */
 322 #else
 323 #  define CONFIG_SYS_CBSIZE             256     /* Console I/O Buffer Size           */
 324 #endif
 325
 326 /* Print Buffer Size */
 327 #define CONFIG_SYS_PBSIZE         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
 328
 329 #define CONFIG_SYS_MAXARGS              32      /* max number of command args   */
 330
 331 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size     */
 332
 333 #define CONFIG_SYS_LOAD_ADDR            0x140000   /* default load address */
 334 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 335
 336 #define CONFIG_SYS_MEMTEST_START        0x2000  /* memtest works from the end of */
 337                                         /* the exception vector table */
 338                                         /* to the end of the DRAM  */
 339                                         /* less monitor and malloc area */
 340 #define CONFIG_SYS_STACK_USAGE          0x10000 /* Reserve 64k for the stack usage */
 341 #define CONFIG_SYS_MEM_END_USAGE        ( CONFIG_SYS_MONITOR_LEN \
 342                                 + CONFIG_SYS_MALLOC_LEN \
 343                                 + CONFIG_ENV_SECT_SIZE \
 344                                 + CONFIG_SYS_STACK_USAGE )
 345
 346 #define CONFIG_SYS_MEMTEST_END          ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
 347                                 - CONFIG_SYS_MEM_END_USAGE )
 348
 349 /*
 350  * Low Level Configuration Settings
 351  * (address mappings, register initial values, etc.)
 352  * You should know what you are doing if you make changes here.
 353  */
 354
 355 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
 356 /*
 357  *  Attention: This is board specific
 358  *  - RX clk is CLK11
 359  *  - TX clk is CLK12
 360  */
 361 #define CONFIG_SYS_CMXSCR_VALUE       (CMXSCR_RS1CS_CLK11  |\
 362                                 CMXSCR_TS1CS_CLK12)
 363
 364 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 365 /*
 366  * Attention: this is board-specific
 367  * - Rx-CLK is CLK13
 368  * - Tx-CLK is CLK14
 369  * - Select bus for bd/buffers (see 28-13)
 370  * - Enable Full Duplex in FSMR
 371  */
 372 #define CONFIG_SYS_CMXFCR_MASK2         (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 373 #define CONFIG_SYS_CMXFCR_VALUE2        (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 374 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
 375 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
 376 #endif  /* CONFIG_ETHER_INDEX */
 377
 378 #define CONFIG_SYS_FLASH_BASE   CONFIG_SYS_FLASH0_BASE
 379 #define CONFIG_SYS_FLASH_SIZE   CONFIG_SYS_FLASH0_SIZE
 380 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_SDRAM0_BASE
 381 #define CONFIG_SYS_SDRAM_SIZE   (CONFIG_SYS_SDRAM0_SIZE + CONFIG_SYS_SDRAM1_SIZE)
 382
 383 /*-----------------------------------------------------------------------
 384  * Hard Reset Configuration Words
 385  */
 386 #if defined(CONFIG_SYS_PPMC_BOOT_LOW)
 387 #  define  CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 388 #else
 389 #  define  CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS  (0)
 390 #endif /* defined(CONFIG_SYS_PPMC_BOOT_LOW) */
 391
 392 /* get the HRCW ISB field from CONFIG_SYS_IMMR */
 393 #define CONFIG_SYS_PPMC_HRCW_IMMR       ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
 394                                   ((CONFIG_SYS_IMMR & 0x01000000) >>  7) | \
 395                                   ((CONFIG_SYS_IMMR & 0x00100000) >>  4) )
 396
 397 #define CONFIG_SYS_HRCW_MASTER          ( HRCW_EBM                              | \
 398                                   HRCW_BPS11                            | \
 399                                   HRCW_L2CPC10                          | \
 400                                   HRCW_DPPC00                           | \
 401                                   CONFIG_SYS_PPMC_HRCW_IMMR                     | \
 402                                   HRCW_MMR00                            | \
 403                                   HRCW_LBPC00                           | \
 404                                   HRCW_APPC10                           | \
 405                                   HRCW_CS10PC00                         | \
 406                                   (CONFIG_SYS_PPMC_MODCK_H & HRCW_MODCK_H1111) | \
 407                                   CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS )
 408
 409 /* no slaves */
 410 #define CONFIG_SYS_HRCW_SLAVE1          0
 411 #define CONFIG_SYS_HRCW_SLAVE2          0
 412 #define CONFIG_SYS_HRCW_SLAVE3          0
 413 #define CONFIG_SYS_HRCW_SLAVE4          0
 414 #define CONFIG_SYS_HRCW_SLAVE5          0
 415 #define CONFIG_SYS_HRCW_SLAVE6          0
 416 #define CONFIG_SYS_HRCW_SLAVE7          0
 417
 418 /*-----------------------------------------------------------------------
 419  * Definitions for initial stack pointer and data area (in DPRAM)
 420  */
 421 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 422 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM   */
 423 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 424 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 425
 426 /*-----------------------------------------------------------------------
 427  * Start addresses for the final memory configuration
 428  * (Set up by the startup code)
 429  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 430  * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
 431  */
 432 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
 433
 434 #ifndef CONFIG_SYS_MONITOR_BASE
 435 #define CONFIG_SYS_MONITOR_BASE 0x0ff80000
 436 #endif
 437
 438 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 439 #  define CONFIG_SYS_RAMBOOT
 440 #endif
 441
 442 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 374 kB for Monitor   */
 443 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 444
 445 /*
 446  * For booting Linux, the board info and command line data
 447  * have to be in the first 8 MB of memory, since this is
 448  * the maximum mapped by the Linux kernel during initialization.
 449  */
 450 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 451
 452 /*-----------------------------------------------------------------------
 453  * FLASH and environment organization
 454  */
 455
 456 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant              */
 457 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver                */
 458 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max number of sectors on one chip    */
 459 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 460 #define CONFIG_SYS_FLASH_INCREMENT      0       /* there is only one bank               */
 461 #define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware protection              */
 462 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
 463
 464
 465 #ifndef CONFIG_SYS_RAMBOOT
 466
 467 #  define CONFIG_ENV_IS_IN_FLASH        1
 468 #  ifdef CONFIG_ENV_IN_OWN_SECT
 469 #    define CONFIG_ENV_ADDR     (CONFIG_SYS_MONITOR_BASE + 0x40000)
 470 #    define CONFIG_ENV_SECT_SIZE        0x40000
 471 #  else
 472 #    define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
 473 #    define CONFIG_ENV_SIZE     0x1000  /* Total Size of Environment Sector     */
 474 #    define CONFIG_ENV_SECT_SIZE        0x40000 /* see README - env sect real size      */
 475 #  endif /* CONFIG_ENV_IN_OWN_SECT */
 476
 477 #else
 478 #  define CONFIG_ENV_IS_IN_FLASH        1
 479 #  define CONFIG_ENV_ADDR               (CONFIG_SYS_FLASH_BASE + 0x40000)
 480 #define CONFIG_ENV_SIZE         0x1000
 481 #  define CONFIG_ENV_SECT_SIZE  0x40000
 482 #endif /* CONFIG_SYS_RAMBOOT */
 483
 484 /*-----------------------------------------------------------------------
 485  * Cache Configuration
 486  */
 487 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPU */
 488
 489 #if defined(CONFIG_CMD_KGDB)
 490 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 491 #endif
 492
 493 /*-----------------------------------------------------------------------
 494  * HIDx - Hardware Implementation-dependent Registers                    2-11
 495  *-----------------------------------------------------------------------
 496  * HID0 also contains cache control - initially enable both caches and
 497  * invalidate contents, then the final state leaves only the instruction
 498  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 499  * but Soft reset does not.
 500  *
 501  * HID1 has only read-only information - nothing to set.
 502  */
 503 #define CONFIG_SYS_HID0_INIT    (HID0_ICE  |\
 504                          HID0_DCE  |\
 505                          HID0_ICFI |\
 506                          HID0_DCI  |\
 507                          HID0_IFEM |\
 508                          HID0_ABE)
 509
 510 #define CONFIG_SYS_HID0_FINAL   (HID0_ICE  |\
 511                          HID0_IFEM |\
 512                          HID0_ABE  |\
 513                          HID0_EMCP)
 514 #define CONFIG_SYS_HID2 0
 515
 516 /*-----------------------------------------------------------------------
 517  * RMR - Reset Mode Register
 518  *-----------------------------------------------------------------------
 519  */
 520 #define CONFIG_SYS_RMR          0
 521
 522 /*-----------------------------------------------------------------------
 523  * BCR - Bus Configuration                                       4-25
 524  *-----------------------------------------------------------------------
 525  */
 526 #define CONFIG_SYS_BCR          (BCR_EBM      |\
 527                          0x30000000)
 528
 529 /*-----------------------------------------------------------------------
 530  * SIUMCR - SIU Module Configuration                             4-31
 531  * Ref Section 4.3.2.6  page 4-31
 532  *-----------------------------------------------------------------------
 533  */
 534
 535 #define CONFIG_SYS_SIUMCR       (SIUMCR_ESE      |\
 536                          SIUMCR_DPPC00   |\
 537                          SIUMCR_L2CPC10  |\
 538                          SIUMCR_LBPC00   |\
 539                          SIUMCR_APPC10   |\
 540                          SIUMCR_CS10PC00 |\
 541                          SIUMCR_BCTLC00  |\
 542                          SIUMCR_MMR00)
 543
 544
 545 /*-----------------------------------------------------------------------
 546  * SYPCR - System Protection Control                            11-9
 547  * SYPCR can only be written once after reset!
 548  *-----------------------------------------------------------------------
 549  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 550  */
 551 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC |\
 552                          SYPCR_BMT  |\
 553                          SYPCR_PBME |\
 554                          SYPCR_LBME |\
 555                          SYPCR_SWRI |\
 556                          SYPCR_SWP)
 557
 558 /*-----------------------------------------------------------------------
 559  * TMCNTSC - Time Counter Status and Control                     4-40
 560  *-----------------------------------------------------------------------
 561  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 562  * and enable Time Counter
 563  */
 564 #define CONFIG_SYS_TMCNTSC      (TMCNTSC_SEC |\
 565                          TMCNTSC_ALR |\
 566                          TMCNTSC_TCF |\
 567                          TMCNTSC_TCE)
 568
 569 /*-----------------------------------------------------------------------
 570  * PISCR - Periodic Interrupt Status and Control                 4-42
 571  *-----------------------------------------------------------------------
 572  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 573  * Periodic timer
 574  */
 575 #define CONFIG_SYS_PISCR        (PISCR_PS  |\
 576                          PISCR_PTF |\
 577                          PISCR_PTE)
 578
 579 /*-----------------------------------------------------------------------
 580  * SCCR - System Clock Control                                   9-8
 581  *-----------------------------------------------------------------------
 582  */
 583 #define CONFIG_SYS_SCCR 0
 584
 585 /*-----------------------------------------------------------------------
 586  * RCCR - RISC Controller Configuration                         13-7
 587  *-----------------------------------------------------------------------
 588  */
 589 #define CONFIG_SYS_RCCR 0
 590
 591 /*
 592  * Initialize Memory Controller:
 593  *
 594  * Bank Bus     Machine PortSz  Device
 595  * ---- ---     ------- ------  ------
 596  *  0   60x     GPCM    32 bit  FLASH (SIMM - 32MB) *
 597  *  1   unused
 598  *  2   60x     SDRAM   64 bit  SDRAM (DIMM - 128MB)
 599  *  3   60x     SDRAM   64 bit  SDRAM (DIMM - 128MB)
 600  *  4   Local   SDRAM   32 bit  SDRAM (on board - 16MB)
 601  *  5   60x     GPCM     8 bit  Mailbox/EEPROM (8KB)
 602  *  6   60x     GPCM     8 bit  FLASH  (on board - 2MB) *
 603  *  7   60x     GPCM     8 bit  LEDs, switches
 604  *
 605  *  (*) This configuration requires the PPMC8260 be configured
 606  *      so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
 607  *      the on board FLASH. In other words, JP24 should have
 608  *      pins 1 and 2 jumpered and pins 3 and 4 jumpered.
 609  *
 610  */
 611
 612 /*-----------------------------------------------------------------------
 613  * BR0,BR1 - Base Register
 614  *     Ref: Section 10.3.1 on page 10-14
 615  * OR0,OR1 - Option Register
 616  *     Ref: Section 10.3.2 on page 10-18
 617  *-----------------------------------------------------------------------
 618  */
 619
 620 /* Bank 0,1 - FLASH SIMM
 621  *
 622  * This expects the FLASH SIMM to be connected to *CS0
 623  * It consists of 4 AM29F080B parts.
 624  *
 625  * Note: For the 4 MB SIMM, *CS1 is unused.
 626  */
 627
 628 /* BR0 is configured as follows:
 629  *
 630  *     - Base address of 0xFE000000
 631  *     - 32 bit port size
 632  *     - Data errors checking is disabled
 633  *     - Read and write access
 634  *     - GPCM 60x bus
 635  *     - Access are handled by the memory controller according to MSEL
 636  *     - Not used for atomic operations
 637  *     - No data pipelining is done
 638  *     - Valid
 639  */
 640 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
 641                          BRx_PS_32                      |\
 642                          BRx_MS_GPCM_P                  |\
 643                          BRx_V)
 644
 645 /* OR0 is configured as follows:
 646  *
 647  *     - 32 MB
 648  *     - *BCTL0 is asserted upon access to the current memory bank
 649  *     - *CW / *WE are negated a quarter of a clock earlier
 650  *     - *CS is output at the same time as the address lines
 651  *     - Uses a clock cycle length of 5
 652  *     - *PSDVAL is generated internally by the memory controller
 653  *       unless *GTA is asserted earlier externally.
 654  *     - Relaxed timing is generated by the GPCM for accesses
 655  *       initiated to this memory region.
 656  *     - One idle clock is inserted between a read access from the
 657  *       current bank and the next access.
 658  */
 659 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE)      |\
 660                          ORxG_CSNT                      |\
 661                          ORxG_ACS_DIV1                  |\
 662                          ORxG_SCY_5_CLK                 |\
 663                          ORxG_TRLX                      |\
 664                          ORxG_EHTR)
 665
 666 /*-----------------------------------------------------------------------
 667  * BR2,BR3 - Base Register
 668  *     Ref: Section 10.3.1 on page 10-14
 669  * OR2,OR3 - Option Register
 670  *     Ref: Section 10.3.2 on page 10-16
 671  *-----------------------------------------------------------------------
 672  */
 673
 674 /*
 675  * Bank 2,3 - 128 MB SDRAM DIMM
 676  */
 677
 678 /* With a 128 MB DIMM, the BR2 is configured as follows:
 679  *
 680  *     - Base address of 0x00000000/0x08000000
 681  *     - 64 bit port size (60x bus only)
 682  *     - Data errors checking is disabled
 683  *     - Read and write access
 684  *     - SDRAM 60x bus
 685  *     - Access are handled by the memory controller according to MSEL
 686  *     - Not used for atomic operations
 687  *     - No data pipelining is done
 688  *     - Valid
 689  */
 690 #define CONFIG_SYS_BR2_PRELIM   ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
 691                          BRx_PS_64                      |\
 692                          BRx_MS_SDRAM_P                 |\
 693                          BRx_V)
 694
 695 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
 696                          BRx_PS_64                      |\
 697                          BRx_MS_SDRAM_P                 |\
 698                          BRx_V)
 699
 700 /* With a 128 MB DIMM, the OR2 is configured as follows:
 701  *
 702  *     - 128 MB
 703  *     - 4 internal banks per device
 704  *     - Row start address bit is A8 with PSDMR[PBI] = 0
 705  *     - 13 row address lines
 706  *     - Back-to-back page mode
 707  *     - Internal bank interleaving within save device enabled
 708  */
 709
 710 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE)      |\
 711                          ORxS_BPD_4                     |\
 712                          ORxS_ROWST_PBI0_A7             |\
 713                          ORxS_NUMR_13)
 714
 715 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE)      |\
 716                          ORxS_BPD_4                     |\
 717                          ORxS_ROWST_PBI0_A7             |\
 718                          ORxS_NUMR_13)
 719
 720
 721 /*-----------------------------------------------------------------------
 722  * PSDMR - 60x Bus SDRAM Mode Register
 723  *     Ref: Section 10.3.3 on page 10-21
 724  *-----------------------------------------------------------------------
 725  */
 726
 727 /* With a 128 MB DIMM, the PSDMR is configured as follows:
 728  *
 729  *     - Page Based Interleaving,
 730  *     - Refresh Enable,
 731  *     - Normal Operation
 732  *     - Address Multiplexing where A5 is output on A14 pin
 733  *       (A6 on A15, and so on),
 734  *     - use address pins A13-A15 as bank select,
 735  *     - A9 is output on SDA10 during an ACTIVATE command,
 736  *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
 737  *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
 738  *       is 3 clocks,
 739  *     - earliest timing for READ/WRITE command after ACTIVATE command is
 740  *       2 clocks,
 741  *     - earliest timing for PRECHARGE after last data was read is 1 clock,
 742  *     - earliest timing for PRECHARGE after last data was written is 1 clock,
 743  *     - External Address Multiplexing enabled
 744  *     - CAS Latency is 2.
 745  */
 746 #define CONFIG_SYS_PSDMR        (PSDMR_RFEN           |\
 747                          PSDMR_SDAM_A14_IS_A5 |\
 748                          PSDMR_BSMA_A13_A15   |\
 749                          PSDMR_SDA10_PBI0_A9  |\
 750                          PSDMR_RFRC_7_CLK     |\
 751                          PSDMR_PRETOACT_3W    |\
 752                          PSDMR_ACTTORW_2W     |\
 753                          PSDMR_LDOTOPRE_1C    |\
 754                          PSDMR_WRC_1C         |\
 755                          PSDMR_EAMUX          |\
 756                          PSDMR_CL_2)
 757
 758
 759 #define CONFIG_SYS_PSRT 0x0e
 760 #define CONFIG_SYS_MPTPR        MPTPR_PTP_DIV32
 761
 762
 763 /*-----------------------------------------------------------------------
 764  * BR4 - Base Register
 765  *     Ref: Section 10.3.1 on page 10-14
 766  * OR4 - Option Register
 767  *     Ref: Section 10.3.2 on page 10-16
 768  *-----------------------------------------------------------------------
 769  */
 770
 771 /*
 772  * Bank 4 - On board SDRAM
 773  *
 774  */
 775 /* With 16 MB of onboard SDRAM  BR4 is configured as follows
 776  *
 777  *     - Base address 0x38000000
 778  *     - 32 bit port size
 779  *     - Data error checking disabled
 780  *     - Read/Write access
 781  *     - SDRAM local bus
 782  *     - Not used for atomic operations
 783  *     - No data pipelining is done
 784  *     - Valid
 785  *
 786  */
 787
 788 #define CONFIG_SYS_BR4_PRELIM   ((CONFIG_SYS_SDRAM2_BASE & BRx_BA_MSK) |\
 789                          BRx_PS_32                      |\
 790                          BRx_DECC_NONE                  |\
 791                          BRx_MS_SDRAM_L                 |\
 792                          BRx_V)
 793
 794 /*
 795  * With 16MB SDRAM, OR4 is configured as follows
 796  *     - 4 internal banks per device
 797  *     - Row start address bit is A10 with LSDMR[PBI] = 0
 798  *     - 12 row address lines
 799  *     - Back-to-back page mode
 800  *     - Internal bank interleaving within save device enabled
 801  */
 802
 803 #define CONFIG_SYS_OR4_PRELIM   (MEG_TO_AM(CONFIG_SYS_SDRAM2_SIZE)      |\
 804                          ORxS_BPD_4                     |\
 805                          ORxS_ROWST_PBI0_A10            |\
 806                          ORxS_NUMR_12)
 807
 808
 809 /*-----------------------------------------------------------------------
 810  * LSDMR - Local Bus SDRAM Mode Register
 811  *     Ref: Section 10.3.4 on page 10-24
 812  *-----------------------------------------------------------------------
 813  */
 814
 815 /* With a 16 MB onboard SDRAM, the LSDMR is configured as follows:
 816  *
 817  *     - Page Based Interleaving,
 818  *     - Refresh Enable,
 819  *     - Normal Operation
 820  *     - Address Multiplexing where A5 is output on A13 pin
 821  *       (A6 on A15, and so on),
 822  *     - use address pins A15-A17 as bank select,
 823  *     - A11 is output on SDA10 during an ACTIVATE command,
 824  *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
 825  *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
 826  *       is 2 clocks,
 827  *     - earliest timing for READ/WRITE command after ACTIVATE command is
 828  *       2 clocks,
 829  *     - SDRAM burst length is 8
 830  *     - earliest timing for PRECHARGE after last data was read is 1 clock,
 831  *     - earliest timing for PRECHARGE after last data was written is 1 clock,
 832  *     - External Address Multiplexing disabled
 833  *     - CAS Latency is 2.
 834  */
 835 #define CONFIG_SYS_LSDMR        (PSDMR_RFEN           |\
 836                          PSDMR_SDAM_A13_IS_A5 |\
 837                          PSDMR_BSMA_A15_A17   |\
 838                          PSDMR_SDA10_PBI0_A11 |\
 839                          PSDMR_RFRC_7_CLK     |\
 840                          PSDMR_PRETOACT_2W    |\
 841                          PSDMR_ACTTORW_2W     |\
 842                          PSDMR_BL             |\
 843                          PSDMR_LDOTOPRE_1C    |\
 844                          PSDMR_WRC_1C         |\
 845                          PSDMR_CL_2)
 846
 847 #define CONFIG_SYS_LSRT 0x0e
 848
 849 /*-----------------------------------------------------------------------
 850  * BR5 - Base Register
 851  *     Ref: Section 10.3.1 on page 10-14
 852  * OR5 - Option Register
 853  *     Ref: Section 10.3.2 on page 10-16
 854  *-----------------------------------------------------------------------
 855  */
 856
 857 /*
 858  * Bank 5 EEProm and Mailbox
 859  *
 860  * The EEPROM and mailbox live on the same chip select.
 861  * the eeprom is selected if the MSb of the address is set and the mailbox is
 862  * selected if the MSb of the address is clear.
 863  *
 864  */
 865
 866 /* BR5 is configured as follows:
 867  *
 868  *     - Base address of 0x32000000/0xF2000000
 869  *     - 8 bit
 870  *     - Data error checking disabled
 871  *     - Read/Write access
 872  *     - GPCM 60x Bus
 873  *     - SDRAM local bus
 874  *     - No data pipelining is done
 875  *     - Valid
 876  */
 877
 878 #define CONFIG_SYS_BR5_PRELIM   ((CONFIG_SYS_MAILBOX_BASE & BRx_BA_MSK) |\
 879                          BRx_PS_8                        |\
 880                          BRx_DECC_NONE                   |\
 881                          BRx_MS_GPCM_P                   |\
 882                          BRx_V)
 883 /* OR5 is configured as follows
 884  *     - buffer control enabled
 885  *     - chip select negated normally
 886  *     - CS output 1/2 clock after address
 887  *     - 15 wait states
 888  *     - *PSDVAL is generated internally by the memory controller
 889  *       unless *GTA is asserted earlier externally.
 890  *     - Relaxed timing is generated by the GPCM for accesses
 891  *       initiated to this memory region.
 892  *     - One idle clock is inserted between a read access from the
 893  *       current bank and the next access.
 894  */
 895
 896 #define CONFIG_SYS_OR5_PRELIM ((P2SZ_TO_AM(CONFIG_SYS_MAILBOX_SIZE) & ~0x80000000) |\
 897                          ORxG_ACS_DIV2                               |\
 898                          ORxG_SCY_15_CLK                             |\
 899                          ORxG_TRLX                                   |\
 900                          ORxG_EHTR)
 901
 902 /*-----------------------------------------------------------------------
 903  * BR6 - Base Register
 904  *     Ref: Section 10.3.1 on page 10-14
 905  * OR6 - Option Register
 906  *     Ref: Section 10.3.2 on page 10-18
 907  *-----------------------------------------------------------------------
 908  */
 909
 910 /* Bank 6 - I/O select
 911  *
 912  */
 913
 914 /* BR6 is configured as follows:
 915  *
 916  *     - Base address of 0xE0000000
 917  *     - 16 bit port size
 918  *     - Data errors checking is disabled
 919  *     - Read and write access
 920  *     - GPCM 60x bus
 921  *     - Access are handled by the memory controller according to MSEL
 922  *     - Not used for atomic operations
 923  *     - No data pipelining is done
 924  *     - Valid
 925  */
 926 #define CONFIG_SYS_BR6_PRELIM   ((CONFIG_SYS_IOSELECT_BASE & BRx_BA_MSK) |\
 927                            BRx_PS_16                      |\
 928                            BRx_MS_GPCM_P                  |\
 929                            BRx_V)
 930
 931 /* OR6 is configured as follows
 932  *     - buffer control enabled
 933  *     - chip select negated normally
 934  *     - CS output 1/2 clock after address
 935  *     - 15 wait states
 936  *     - *PSDVAL is generated internally by the memory controller
 937  *       unless *GTA is asserted earlier externally.
 938  *     - Relaxed timing is generated by the GPCM for accesses
 939  *       initiated to this memory region.
 940  *     - One idle clock is inserted between a read access from the
 941  *       current bank and the next access.
 942  */
 943
 944 #define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_IOSELECT_SIZE) |\
 945                          ORxG_ACS_DIV2               |\
 946                          ORxG_SCY_15_CLK             |\
 947                          ORxG_TRLX                   |\
 948                          ORxG_EHTR)
 949
 950
 951 /*-----------------------------------------------------------------------
 952  * BR7 - Base Register
 953  *     Ref: Section 10.3.1 on page 10-14
 954  * OR7 - Option Register
 955  *     Ref: Section 10.3.2 on page 10-18
 956  *-----------------------------------------------------------------------
 957  */
 958
 959 /* Bank 7 - LEDs and switches
 960  *
 961  *  LEDs     are at 0x00001 (write only)
 962  *  switches are at 0x00001 (read only)
 963  */
 964 #ifdef CONFIG_SYS_LED_BASE
 965
 966 /* BR7 is configured as follows:
 967  *
 968  *     - Base address of 0xA0000000
 969  *     - 8 bit port size
 970  *     - Data errors checking is disabled
 971  *     - Read and write access
 972  *     - GPCM 60x bus
 973  *     - Access are handled by the memory controller according to MSEL
 974  *     - Not used for atomic operations
 975  *     - No data pipelining is done
 976  *     - Valid
 977  */
 978 #define CONFIG_SYS_BR7_PRELIM   ((CONFIG_SYS_LED_BASE & BRx_BA_MSK)      |\
 979                            BRx_PS_8                      |\
 980                            BRx_DECC_NONE                 |\
 981                            BRx_MS_GPCM_P                 |\
 982                            BRx_V)
 983
 984 /* OR7 is configured as follows:
 985  *
 986  *     - 1 byte
 987  *     - *BCTL0 is asserted upon access to the current memory bank
 988  *     - *CW / *WE are negated a quarter of a clock earlier
 989  *     - *CS is output at the same time as the address lines
 990  *     - Uses a clock cycle length of 15
 991  *     - *PSDVAL is generated internally by the memory controller
 992  *       unless *GTA is asserted earlier externally.
 993  *     - Relaxed timing is generated by the GPCM for accesses
 994  *       initiated to this memory region.
 995  *     - One idle clock is inserted between a read access from the
 996  *       current bank and the next access.
 997  */
 998 #define CONFIG_SYS_OR7_PRELIM   (ORxG_AM_MSK                   |\
 999                          ORxG_CSNT                     |\
1000                          ORxG_ACS_DIV1                 |\
1001                          ORxG_SCY_15_CLK               |\
1002                          ORxG_TRLX                     |\
1003                          ORxG_EHTR)
1004 #endif /* CONFIG_SYS_LED_BASE */
1005 #endif  /* __CONFIG_H */