include/configs/pxa255_idp.h

   1 /*
   2  * (C) Copyright 2002
   3  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   4  *
   5  * (C) Copyright 2002
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * Copied from lubbock.h
  10  *
  11  * (C) Copyright 2004
  12  * BEC Systems <http://bec-systems.com>
  13  * Cliff Brake <cliff.brake@gmail.com>
  14  * Configuation settings for the Accelent/Vibren PXA255 IDP
  15  *
  16  * SPDX-License-Identifier:     GPL-2.0+
  17  */
  18
  19 #ifndef __CONFIG_H
  20 #define __CONFIG_H
  21
  22 #include <asm/arch/pxa-regs.h>
  23
  24 /*
  25  * If we are developing, we might want to start U-Boot from RAM
  26  * so we MUST NOT initialize critical regs like mem-timing ...
  27  */
  28 #undef CONFIG_SKIP_LOWLEVEL_INIT                        /* define for developing */
  29 #define CONFIG_SYS_TEXT_BASE    0x0
  30
  31 /*
  32  * define the following to enable debug blinks.  A debug blink function
  33  * must be defined in memsetup.S
  34  */
  35 #undef DEBUG_BLINK_ENABLE
  36 #undef DEBUG_BLINKC_ENABLE
  37
  38 /*
  39  * High Level Configuration Options
  40  * (easy to change)
  41  */
  42 #define CONFIG_CPU_PXA25X               1       /* This is an PXA250 CPU    */
  43
  44 #undef CONFIG_LCD
  45 #ifdef CONFIG_LCD
  46 #define CONFIG_PXA_LCD
  47 #define CONFIG_SHARP_LM8V31
  48 #endif
  49
  50 #define CONFIG_MMC              1
  51 #define CONFIG_DOS_PARTITION    1
  52 #define CONFIG_BOARD_LATE_INIT
  53
  54 /* we will never enable dcache, because we have to setup MMU first */
  55 #define CONFIG_SYS_DCACHE_OFF
  56
  57 /*
  58  * Size of malloc() pool
  59  */
  60 #define CONFIG_SYS_MALLOC_LEN       (CONFIG_ENV_SIZE + 128*1024)
  61
  62 /*
  63  * PXA250 IDP memory map information
  64  */
  65
  66 #define IDP_CS5_ETH_OFFSET      0x03400000
  67
  68
  69 /*
  70  * Hardware drivers
  71  */
  72 #define CONFIG_SMC91111
  73 #define CONFIG_SMC91111_BASE    (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
  74 #define CONFIG_SMC_USE_32_BIT   1
  75 /* #define CONFIG_SMC_USE_IOFUNCS */
  76
  77 /* the following has to be set high -- suspect something is wrong with
  78  * with the tftp timeout routines. FIXME!!!
  79  */
  80 #define CONFIG_NET_RETRY_COUNT  100
  81
  82 /*
  83  * select serial console configuration
  84  */
  85 #define CONFIG_PXA_SERIAL
  86 #define CONFIG_FFUART          1       /* we use FFUART on LUBBOCK */
  87 #define CONFIG_CONS_INDEX       3
  88
  89 /* allow to overwrite serial and ethaddr */
  90 #define CONFIG_ENV_OVERWRITE
  91
  92 #define CONFIG_BAUDRATE         115200
  93
  94
  95 /*
  96  * BOOTP options
  97  */
  98 #define CONFIG_BOOTP_BOOTFILESIZE
  99 #define CONFIG_BOOTP_BOOTPATH
 100 #define CONFIG_BOOTP_GATEWAY
 101 #define CONFIG_BOOTP_HOSTNAME
 102
 103
 104 /*
 105  * Command line configuration.
 106  */
 107 #define CONFIG_CMD_FAT
 108 #define CONFIG_CMD_DHCP
 109
 110 #define CONFIG_BOOTDELAY        3
 111 #define CONFIG_BOOTCOMMAND      "bootm 40000"
 112 #define CONFIG_BOOTARGS         "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
 113
 114 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
 115 #define CONFIG_SETUP_MEMORY_TAGS        1
 116 /* #define CONFIG_INITRD_TAG            1 */
 117
 118 /*
 119  * Current memory map for Vibren supplied Linux images:
 120  *
 121  * Flash:
 122  * 0 - 0x3ffff (size = 0x40000): bootloader
 123  * 0x40000 - 0x13ffff (size = 0x100000): kernel
 124  * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs
 125  *
 126  * RAM:
 127  * 0xa0008000 - kernel is loaded
 128  * 0xa3000000 - Uboot runs (48MB into RAM)
 129  *
 130  */
 131
 132 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 133         "prog_boot_mmc="                                                \
 134                         "mw.b 0xa0000000 0xff 0x40000; "                \
 135                         "if      mmcinit && "                           \
 136                                 "fatload mmc 0 0xa0000000 u-boot.bin; " \
 137                         "then "                                         \
 138                                 "protect off 0x0 0x3ffff; "             \
 139                                 "erase 0x0 0x3ffff; "                   \
 140                                 "cp.b 0xa0000000 0x0 0x40000; "         \
 141                                 "reset;"                                \
 142                         "fi\0"                                          \
 143         "prog_uzImage_mmc="                                             \
 144                         "mw.b 0xa0000000 0xff 0x100000; "               \
 145                         "if      mmcinit && "                           \
 146                                 "fatload mmc 0 0xa0000000 uzImage; "    \
 147                         "then "                                         \
 148                                 "protect off 0x40000 0xfffff; "         \
 149                                 "erase 0x40000 0xfffff; "               \
 150                                 "cp.b 0xa0000000 0x40000 0x100000; "    \
 151                         "fi\0"                                          \
 152         "prog_jffs_mmc="                                                \
 153                         "mw.b 0xa0000000 0xff 0x1e00000; "              \
 154                         "if      mmcinit && "                           \
 155                                 "fatload mmc 0 0xa0000000 root.jffs; "  \
 156                         "then "                                         \
 157                                 "protect off 0x140000 0x1f3ffff; "      \
 158                                 "erase 0x140000 0x1f3ffff; "            \
 159                                 "cp.b 0xa0000000 0x140000 0x1e00000; "  \
 160                         "fi\0"                                          \
 161         "boot_mmc="                                                     \
 162                         "if      mmcinit && "                           \
 163                                 "fatload mmc 0 0xa1000000 uzImage && "  \
 164                         "then "                                         \
 165                                 "bootm 0xa1000000; "                    \
 166                         "fi\0"                                          \
 167         "prog_boot_net="                                                \
 168                         "mw.b 0xa0000000 0xff 0x100000; "               \
 169                         "if      bootp 0xa0000000 u-boot.bin; "         \
 170                         "then "                                         \
 171                                 "protect off 0x0 0x3ffff; "             \
 172                                 "erase 0x0 0x3ffff; "                   \
 173                                 "cp.b 0xa0000000 0x0 0x40000; "         \
 174                                 "reset; "                               \
 175                         "fi\0"                                          \
 176         "prog_uzImage_net="                                             \
 177                         "mw.b 0xa0000000 0xff 0x100000; "               \
 178                         "if      bootp 0xa0000000 uzImage; "            \
 179                         "then "                                         \
 180                                 "protect off 0x40000 0xfffff; "         \
 181                                 "erase 0x40000 0xfffff; "               \
 182                                 "cp.b 0xa0000000 0x40000 0x100000; "    \
 183                         "fi\0"                                          \
 184         "prog_jffs_net="                                                \
 185                         "mw.b 0xa0000000 0xff 0x1e00000; "              \
 186                         "if      bootp 0xa0000000 root.jffs; "          \
 187                         "then "                                         \
 188                                 "protect off 0x140000 0x1f3ffff; "      \
 189                                 "erase 0x140000 0x1f3ffff; "            \
 190                                 "cp.b 0xa0000000 0x140000 0x1e00000; "  \
 191                         "fi\0"
 192
 193
 194 /*      "erase_env="                    */
 195 /*                      "protect off"   */
 196
 197
 198 #if defined(CONFIG_CMD_KGDB)
 199 #define CONFIG_KGDB_BAUDRATE    115200          /* speed to run kgdb serial port */
 200 #endif
 201
 202 /*
 203  * Miscellaneous configurable options
 204  */
 205 #define CONFIG_SYS_HUSH_PARSER          1
 206
 207 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
 208 #undef CONFIG_SYS_PROMPT
 209 #ifdef CONFIG_SYS_HUSH_PARSER
 210 #define CONFIG_SYS_PROMPT               "$ "            /* Monitor Command Prompt */
 211 #else
 212 #endif
 213 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 214 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 215 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 216 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 217 #define CONFIG_SYS_DEVICE_NULLDEV       1
 218
 219 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on     */
 220 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM   */
 221
 222 #define CONFIG_SYS_LOAD_ADDR            0xa0800000      /* default load address */
 223
 224 #define CONFIG_SYS_CPUSPEED             0x161           /* set core clock to 400/200/100 MHz */
 225
 226 #define RTC     1                               /* enable 32KHz osc */
 227
 228 #ifdef CONFIG_MMC
 229 #define CONFIG_GENERIC_MMC
 230 #define CONFIG_PXA_MMC_GENERIC
 231 #define CONFIG_CMD_MMC
 232 #define CONFIG_SYS_MMC_BASE             0xF0000000
 233 #endif
 234
 235 /*
 236  * Physical Memory Map
 237  */
 238 #define CONFIG_NR_DRAM_BANKS    1          /* we have 1 bank of DRAM */
 239 #define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1 */
 240 #define PHYS_SDRAM_1_SIZE       0x04000000 /* 64 MB */
 241 #define PHYS_SDRAM_2            0xa4000000 /* SDRAM Bank #2 */
 242 #define PHYS_SDRAM_2_SIZE       0x00000000 /* 0 MB */
 243 #define PHYS_SDRAM_3            0xa8000000 /* SDRAM Bank #3 */
 244 #define PHYS_SDRAM_3_SIZE       0x00000000 /* 0 MB */
 245 #define PHYS_SDRAM_4            0xac000000 /* SDRAM Bank #4 */
 246 #define PHYS_SDRAM_4_SIZE       0x00000000 /* 0 MB */
 247
 248 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
 249 #define PHYS_FLASH_2            0x04000000 /* Flash Bank #2 */
 250 #define PHYS_FLASH_SIZE         0x02000000 /* 32 MB */
 251 #define PHYS_FLASH_BANK_SIZE    0x02000000 /* 32 MB Banks */
 252 #define PHYS_FLASH_SECT_SIZE    0x00040000 /* 256 KB sectors (x2) */
 253
 254 #define CONFIG_SYS_DRAM_BASE            0xa0000000
 255 #define CONFIG_SYS_DRAM_SIZE            0x04000000
 256
 257 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 258
 259 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 260 #define CONFIG_SYS_INIT_SP_ADDR         0xfffff800
 261
 262 /*
 263  * GPIO settings
 264  */
 265
 266 #define CONFIG_SYS_GAFR0_L_VAL  0x80001005
 267 #define CONFIG_SYS_GAFR0_U_VAL  0xa5128012
 268 #define CONFIG_SYS_GAFR1_L_VAL  0x699a9558
 269 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa5aa6a
 270 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
 271 #define CONFIG_SYS_GAFR2_U_VAL  0x2
 272 #define CONFIG_SYS_GPCR0_VAL    0x1800400
 273 #define CONFIG_SYS_GPCR1_VAL    0x0
 274 #define CONFIG_SYS_GPCR2_VAL    0x0
 275 #define CONFIG_SYS_GPDR0_VAL    0xc1818440
 276 #define CONFIG_SYS_GPDR1_VAL    0xfcffab82
 277 #define CONFIG_SYS_GPDR2_VAL    0x1ffff
 278 #define CONFIG_SYS_GPSR0_VAL    0x8000
 279 #define CONFIG_SYS_GPSR1_VAL    0x3f0002
 280 #define CONFIG_SYS_GPSR2_VAL    0x1c000
 281
 282 #define CONFIG_SYS_PSSR_VAL             0x20
 283
 284 #define CONFIG_SYS_CCCR                 CCCR_L27|CCCR_M2|CCCR_N10
 285 #define CONFIG_SYS_CKEN                 0x0
 286
 287 /*
 288  * Memory settings
 289  */
 290 #define CONFIG_SYS_MSC0_VAL             0x29DCA4D2
 291 #define CONFIG_SYS_MSC1_VAL             0x43AC494C
 292 #define CONFIG_SYS_MSC2_VAL             0x39D449D4
 293 #define CONFIG_SYS_MDCNFG_VAL           0x090009C9
 294 #define CONFIG_SYS_MDREFR_VAL           0x0085C017
 295 #define CONFIG_SYS_MDMRS_VAL            0x00220022
 296 #define CONFIG_SYS_FLYCNFG_VAL          0x00000000
 297 #define CONFIG_SYS_SXCNFG_VAL           0x00000000
 298
 299 /*
 300  * PCMCIA and CF Interfaces
 301  */
 302 #define CONFIG_SYS_MECR_VAL             0x00000003
 303 #define CONFIG_SYS_MCMEM0_VAL           0x00014405
 304 #define CONFIG_SYS_MCMEM1_VAL           0x00014405
 305 #define CONFIG_SYS_MCATT0_VAL           0x00014405
 306 #define CONFIG_SYS_MCATT1_VAL           0x00014405
 307 #define CONFIG_SYS_MCIO0_VAL            0x00014405
 308 #define CONFIG_SYS_MCIO1_VAL            0x00014405
 309
 310 /*
 311  * FLASH and environment organization
 312  */
 313 #define CONFIG_SYS_FLASH_CFI
 314 #define CONFIG_FLASH_CFI_DRIVER 1
 315
 316 #define CONFIG_SYS_MONITOR_BASE 0
 317 #define CONFIG_SYS_MONITOR_LEN          PHYS_FLASH_SECT_SIZE
 318
 319 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 320 #define CONFIG_SYS_MAX_FLASH_SECT       128  /* max number of sectors on one chip    */
 321
 322 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 323
 324 /* timeout values are in ticks */
 325 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
 326 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 327
 328 /* put cfg at end of flash for now */
 329 #define CONFIG_ENV_IS_IN_FLASH  1
 330  /* Addr of Environment Sector  */
 331 #define CONFIG_ENV_ADDR         (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
 332 #define CONFIG_ENV_SIZE         PHYS_FLASH_SECT_SIZE    /* Total Size of Environment Sector     */
 333 #define CONFIG_ENV_SECT_SIZE    (PHYS_FLASH_SECT_SIZE / 16)
 334
 335 #endif  /* __CONFIG_H */