include/configs/quad100hd.h

   1 /*
   2  * (C) Copyright 2008
   3  * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /************************************************************************
  25  * quad100hd.h - configuration for Quad100hd board
  26  ***********************************************************************/
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*-----------------------------------------------------------------------
  31  * High Level Configuration Options
  32  *----------------------------------------------------------------------*/
  33 #define CONFIG_QUAD100HD        1               /* Board is Quad100hd   */
  34 #define CONFIG_4xx              1               /* ... PPC4xx family    */
  35 #define CONFIG_405EP            1               /* Specifc 405EP support*/
  36
  37 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  38
  39 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  40
  41 #define PLLMR0_DEFAULT          PLLMR0_266_133_66 /* no PCI */
  42 #define PLLMR1_DEFAULT          PLLMR1_266_133_66 /* no PCI */
  43
  44 /* the environment is in the EEPROM by default */
  45 #define CFG_ENV_IS_IN_EEPROM
  46 #undef CFG_ENV_IS_IN_FLASH
  47
  48 #define CONFIG_NET_MULTI        1
  49 #define CONFIG_HAS_ETH1         1
  50 #define CONFIG_MII              1       /* MII PHY management           */
  51 #define CONFIG_PHY_ADDR         0x01    /* PHY address                  */
  52 #define CFG_RX_ETH_BUFFER       16      /* Number of ethernet rx buffers & descriptors */
  53 #define CONFIG_PHY_RESET        1
  54 #define CONFIG_PHY_RESET_DELAY  300     /* PHY RESET recovery delay     */
  55
  56 /*
  57  * Command line configuration.
  58  */
  59 #include <config_cmd_default.h>
  60
  61 #undef CONFIG_CMD_ASKENV
  62 #undef CONFIG_CMD_CACHE
  63 #define CONFIG_CMD_DHCP
  64 #undef CONFIG_CMD_DIAG
  65 #define CONFIG_CMD_EEPROM
  66 #undef CONFIG_CMD_ELF
  67 #define CONFIG_CMD_I2C
  68 #undef CONFIG_CMD_IRQ
  69 #define CONFIG_CMD_JFFS2
  70 #undef CONFIG_CMD_LOG
  71 #undef CONFIG_CMD_MII
  72 #define CONFIG_CMD_NAND
  73 #undef CONFIG_CMD_PING
  74 #define CONFIG_CMD_REGINFO
  75
  76 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
  77
  78 /*-----------------------------------------------------------------------
  79  * SDRAM
  80  *----------------------------------------------------------------------*/
  81 /*
  82  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  83  */
  84 #define CONFIG_SDRAM_BANK0  1
  85 #define CFG_SDRAM_SIZE      0x02000000      /* 32 MB */
  86
  87 /* FIX! SDRAM timings used in datasheet */
  88 #define CFG_SDRAM_CL            3       /* CAS latency */
  89 #define CFG_SDRAM_tRP           20      /* PRECHARGE command period */
  90 #define CFG_SDRAM_tRC           66      /* ACTIVE-to-ACTIVE command period */
  91 #define CFG_SDRAM_tRCD          20      /* ACTIVE-to-READ delay */
  92 #define CFG_SDRAM_tRFC          66      /* Auto refresh period */
  93
  94 /*
  95  * JFFS2
  96  */
  97 #define CFG_JFFS2_FIRST_BANK    0
  98 #ifdef  CFG_KERNEL_IN_JFFS2
  99 #define CFG_JFFS2_FIRST_SECTOR  0   /* JFFS starts at block 0 */
 100 #else /* kernel not in JFFS */
 101 #define CFG_JFFS2_FIRST_SECTOR  8   /* block 0-7 is kernel (1MB = 8 sectors) */
 102 #endif
 103 #define CFG_JFFS2_NUM_BANKS     1
 104
 105 /*-----------------------------------------------------------------------
 106  * Serial Port
 107  *----------------------------------------------------------------------*/
 108 #undef  CFG_EXT_SERIAL_CLOCK                    /* external serial clock */
 109 #define CFG_BASE_BAUD           691200
 110 #define CONFIG_BAUDRATE         115200
 111 #define CONFIG_SERIAL_MULTI
 112
 113 /* The following table includes the supported baudrates */
 114 #define CFG_BAUDRATE_TABLE      \
 115         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 116
 117 /*-----------------------------------------------------------------------
 118  * Miscellaneous configurable options
 119  *----------------------------------------------------------------------*/
 120 #define CFG_LONGHELP                    /* undef to save memory         */
 121 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 122 #if defined(CONFIG_CMD_KGDB)
 123 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 124 #else
 125 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 126 #endif
 127 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 128 #define CFG_MAXARGS             16      /* max number of command args   */
 129 #define CFG_BARGSIZE            CFG_CBSIZE /* Boot Argument Buffer Size */
 130
 131 #define CFG_MEMTEST_START       0x0400000 /* memtest works on           */
 132 #define CFG_MEMTEST_END         0x0C00000 /* 4 ... 12 MB in DRAM        */
 133
 134 #define CFG_LOAD_ADDR           0x100000  /* default load address       */
 135 #define CFG_EXTBDINFO           1       /* To use extended board_info (bd_t) */
 136
 137 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 138
 139 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 140 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 141
 142 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 143 #define CONFIG_LOOPW            1       /* enable loopw command         */
 144 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 145 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 146 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 147
 148 /*-----------------------------------------------------------------------
 149  * I2C
 150  *----------------------------------------------------------------------*/
 151 #define CONFIG_HARD_I2C         1               /* I2C with hardware support    */
 152 #undef  CONFIG_SOFT_I2C                         /* I2C bit-banged               */
 153 #define CFG_I2C_SPEED           400000          /* I2C speed and slave address  */
 154 #define CFG_I2C_SLAVE           0x7F
 155
 156 #define CFG_I2C_EEPROM_ADDR     0x50            /* base address */
 157 #define CFG_I2C_EEPROM_ADDR_LEN 2               /* bytes of address */
 158
 159 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* 8 byte write page size */
 160 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* and takes up to 10 msec */
 161 #define CFG_EEPROM_SIZE                 0x2000
 162
 163 /*-----------------------------------------------------------------------
 164  * Start addresses for the final memory configuration
 165  * (Set up by the startup code)
 166  * Please note that CFG_SDRAM_BASE _must_ start at 0
 167  */
 168 #define CFG_SDRAM_BASE          0x00000000
 169 #define CFG_FLASH_BASE          0xFFC00000
 170 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Monitor   */
 171 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserve 128 kB for malloc()  */
 172 #define CFG_MONITOR_BASE        (TEXT_BASE)
 173
 174 /*
 175  * For booting Linux, the board info and command line data
 176  * have to be in the first 8 MB of memory, since this is
 177  * the maximum mapped by the Linux kernel during initialization.
 178  */
 179 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 180
 181 /*-----------------------------------------------------------------------
 182  * FLASH organization
 183  */
 184 #define CFG_FLASH_CFI                   /* The flash is CFI compatible  */
 185 #define CONFIG_FLASH_CFI_DRIVER
 186
 187 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
 188
 189 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks   */
 190 #define CFG_MAX_FLASH_SECT      128     /* max number of sectors on one chip */
 191
 192 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms) */
 193 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms) */
 194
 195 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster) */
 196 #define CFG_FLASH_INCREMENT      0       /* there is only one bank         */
 197
 198 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 199 #define CFG_FLASH_QUIET_TEST    1       /* don't warn upon unknown flash */
 200
 201 #ifdef CFG_ENV_IS_IN_FLASH
 202 #define CFG_ENV_SECT_SIZE       0x10000 /* size of one complete sector  */
 203 /* the environment is located before u-boot */
 204 #define CFG_ENV_ADDR            (TEXT_BASE - CFG_ENV_SECT_SIZE)
 205
 206 /* Address and size of Redundant Environment Sector     */
 207 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
 208 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SECT_SIZE)
 209 #endif
 210
 211 #ifdef CFG_ENV_IS_IN_EEPROM
 212 #define CFG_ENV_SIZE            0x400           /* Size of Environment vars */
 213 #define CFG_ENV_OFFSET          0x00000000
 214 #define CFG_ENABLE_CRC_16       1       /* Intrinsyc formatting used crc16 */
 215 #endif
 216
 217 /* partly from PPCBoot */
 218 /* NAND */
 219 #define CONFIG_NAND
 220 #ifdef CONFIG_NAND
 221 #define CFG_NAND_BASE   0x60000000
 222 #define CFG_NAND_CS     10   /* our CS is GPIO10 */
 223 #define CFG_NAND_RDY    23   /* our RDY is GPIO23 */
 224 #define CFG_NAND_CE     24   /* our CE is GPIO24  */
 225 #define CFG_NAND_CLE    31   /* our CLE is GPIO31 */
 226 #define CFG_NAND_ALE    30   /* our ALE is GPIO30 */
 227 #define NAND_MAX_CHIPS  1
 228 #define CFG_MAX_NAND_DEVICE     1
 229 #endif
 230
 231 /*-----------------------------------------------------------------------
 232  * Definitions for initial stack pointer and data area (in data cache)
 233  */
 234 /* use on chip memory (OCM) for temperary stack until sdram is tested */
 235 /* see ./cpu/ppc4xx/start.S */
 236 #define CFG_TEMP_STACK_OCM      1
 237
 238 /* On Chip Memory location */
 239 #define CFG_OCM_DATA_ADDR       0xF8000000
 240 #define CFG_OCM_DATA_SIZE       0x1000
 241 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR /* inside of OCM              */
 242 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE /* End of used area in RAM    */
 243
 244 #define CFG_GBL_DATA_SIZE       128  /* size in bytes reserved for initial data */
 245 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 246 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 247
 248 /*-----------------------------------------------------------------------
 249  * External Bus Controller (EBC) Setup
 250  * Taken from PPCBoot board/icecube/icecube.h
 251  */
 252
 253 /* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
 254 #define CFG_EBC_PB0AP           0x04002480
 255 /* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
 256 #define CFG_EBC_PB0CR           0xFFC5A000
 257 #define CFG_EBC_PB1AP           0x04005480
 258 #define CFG_EBC_PB1CR           0x60018000
 259 #define CFG_EBC_PB2AP           0x00000000
 260 #define CFG_EBC_PB2CR           0x00000000
 261 #define CFG_EBC_PB3AP           0x00000000
 262 #define CFG_EBC_PB3CR           0x00000000
 263 #define CFG_EBC_PB4AP           0x00000000
 264 #define CFG_EBC_PB4CR           0x00000000
 265
 266 /*-----------------------------------------------------------------------
 267  * Definitions for GPIO setup (PPC405EP specific)
 268  *
 269  * Taken in part from PPCBoot board/icecube/icecube.h
 270  */
 271 /* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
 272 #define CFG_GPIO0_OSRH          0x55555550
 273 #define CFG_GPIO0_OSRL          0x00000110
 274 #define CFG_GPIO0_ISR1H         0x00000000
 275 #define CFG_GPIO0_ISR1L         0x15555445
 276 #define CFG_GPIO0_TSRH          0x00000000
 277 #define CFG_GPIO0_TSRL          0x00000000
 278 #define CFG_GPIO0_TCR           0xFFFF8097
 279 #define CFG_GPIO0_ODR           0x00000000
 280
 281 #if defined(CONFIG_CMD_KGDB)
 282 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
 283 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
 284 #endif
 285
 286 /* ENVIRONMENT VARS */
 287
 288 #define CONFIG_IPADDR           192.168.1.67
 289 #define CONFIG_SERVERIP         192.168.1.50
 290 #define CONFIG_GATEWAYIP        192.168.1.1
 291 #define CONFIG_NETMASK          255.255.255.0
 292 #define CONFIG_LOADADDR         300000
 293 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 294
 295 /* pass open firmware flat tree */
 296 #define CONFIG_OF_LIBFDT        1
 297
 298 #endif  /* __CONFIG_H */