include/configs/quad100hd.h

   1 /*
   2  * (C) Copyright 2008
   3  * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /************************************************************************
   9  * quad100hd.h - configuration for Quad100hd board
  10  ***********************************************************************/
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*-----------------------------------------------------------------------
  15  * High Level Configuration Options
  16  *----------------------------------------------------------------------*/
  17 #define CONFIG_QUAD100HD        1               /* Board is Quad100hd   */
  18 #define CONFIG_405EP            1               /* Specifc 405EP support*/
  19
  20 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  21
  22 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  23
  24 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  25
  26 #define PLLMR0_DEFAULT          PLLMR0_266_133_66 /* no PCI */
  27 #define PLLMR1_DEFAULT          PLLMR1_266_133_66 /* no PCI */
  28
  29 /* the environment is in the EEPROM by default */
  30 #define CONFIG_ENV_IS_IN_EEPROM
  31 #undef CONFIG_ENV_IS_IN_FLASH
  32
  33 #define CONFIG_PPC4xx_EMAC
  34 #define CONFIG_HAS_ETH1         1
  35 #define CONFIG_MII              1       /* MII PHY management           */
  36 #define CONFIG_PHY_ADDR         0x01    /* PHY address                  */
  37 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* Number of ethernet rx buffers & descriptors */
  38 #define CONFIG_PHY_RESET        1
  39 #define CONFIG_PHY_RESET_DELAY  300     /* PHY RESET recovery delay     */
  40
  41 /*
  42  * Command line configuration.
  43  */
  44 #include <config_cmd_default.h>
  45
  46 #undef CONFIG_CMD_ASKENV
  47 #undef CONFIG_CMD_CACHE
  48 #define CONFIG_CMD_DHCP
  49 #undef CONFIG_CMD_DIAG
  50 #define CONFIG_CMD_EEPROM
  51 #undef CONFIG_CMD_ELF
  52 #define CONFIG_CMD_I2C
  53 #undef CONFIG_CMD_IRQ
  54 #define CONFIG_CMD_JFFS2
  55 #undef CONFIG_CMD_MII
  56 #define CONFIG_CMD_NAND
  57 #undef CONFIG_CMD_PING
  58 #define CONFIG_CMD_REGINFO
  59
  60 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
  61
  62 /*-----------------------------------------------------------------------
  63  * SDRAM
  64  *----------------------------------------------------------------------*/
  65 /*
  66  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  67  */
  68 #define CONFIG_SDRAM_BANK0  1
  69
  70 /* FIX! SDRAM timings used in datasheet */
  71 #define CONFIG_SYS_SDRAM_CL            3       /* CAS latency */
  72 #define CONFIG_SYS_SDRAM_tRP           20      /* PRECHARGE command period */
  73 #define CONFIG_SYS_SDRAM_tRC           66      /* ACTIVE-to-ACTIVE command period */
  74 #define CONFIG_SYS_SDRAM_tRCD          20      /* ACTIVE-to-READ delay */
  75 #define CONFIG_SYS_SDRAM_tRFC          66      /* Auto refresh period */
  76
  77 /*
  78  * JFFS2
  79  */
  80 #define CONFIG_SYS_JFFS2_FIRST_BANK    0
  81 #ifdef  CONFIG_SYS_KERNEL_IN_JFFS2
  82 #define CONFIG_SYS_JFFS2_FIRST_SECTOR  0   /* JFFS starts at block 0 */
  83 #else /* kernel not in JFFS */
  84 #define CONFIG_SYS_JFFS2_FIRST_SECTOR  8   /* block 0-7 is kernel (1MB = 8 sectors) */
  85 #endif
  86 #define CONFIG_SYS_JFFS2_NUM_BANKS     1
  87
  88 /*-----------------------------------------------------------------------
  89  * Serial Port
  90  *----------------------------------------------------------------------*/
  91 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  92 #define CONFIG_SYS_NS16550
  93 #define CONFIG_SYS_NS16550_SERIAL
  94 #define CONFIG_SYS_NS16550_REG_SIZE     1
  95 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  96 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK                     /* external serial clock */
  97 #define CONFIG_SYS_BASE_BAUD            691200
  98 #define CONFIG_BAUDRATE         115200
  99
 100 /* The following table includes the supported baudrates */
 101 #define CONFIG_SYS_BAUDRATE_TABLE       \
 102         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 103
 104 /*-----------------------------------------------------------------------
 105  * Miscellaneous configurable options
 106  *----------------------------------------------------------------------*/
 107 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 108 #if defined(CONFIG_CMD_KGDB)
 109 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 110 #else
 111 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 112 #endif
 113 #define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 114 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 115 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size  */
 116
 117 #define CONFIG_SYS_MEMTEST_START        0x0400000 /* memtest works on           */
 118 #define CONFIG_SYS_MEMTEST_END          0x0C00000 /* 4 ... 12 MB in DRAM        */
 119
 120 #define CONFIG_SYS_LOAD_ADDR            0x100000  /* default load address       */
 121 #define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_info (bd_t) */
 122
 123 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 124 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 125
 126 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 127 #define CONFIG_LOOPW            1       /* enable loopw command         */
 128 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 129 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 130 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 131
 132 /*-----------------------------------------------------------------------
 133  * I2C
 134  *----------------------------------------------------------------------*/
 135 #define CONFIG_SYS_I2C
 136 #define CONFIG_SYS_I2C_PPC4XX
 137 #define CONFIG_SYS_I2C_PPC4XX_CH0
 138 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 139 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 140
 141 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50            /* base address */
 142 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2               /* bytes of address */
 143
 144 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* 8 byte write page size */
 145 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 146 #define CONFIG_SYS_EEPROM_SIZE                  0x2000
 147
 148 /*-----------------------------------------------------------------------
 149  * Start addresses for the final memory configuration
 150  * (Set up by the startup code)
 151  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 152  */
 153 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 154 #define CONFIG_SYS_FLASH_BASE           0xFFC00000
 155 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
 156 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 157 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE)
 158
 159 /*
 160  * For booting Linux, the board info and command line data
 161  * have to be in the first 8 MB of memory, since this is
 162  * the maximum mapped by the Linux kernel during initialization.
 163  */
 164 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 165
 166 /*-----------------------------------------------------------------------
 167  * FLASH organization
 168  */
 169 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 170 #define CONFIG_FLASH_CFI_DRIVER
 171
 172 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 173
 174 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks   */
 175 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max number of sectors on one chip */
 176
 177 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms) */
 178 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms) */
 179
 180 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster) */
 181 #define CONFIG_SYS_FLASH_INCREMENT      0       /* there is only one bank         */
 182
 183 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 184 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash */
 185
 186 #ifdef CONFIG_ENV_IS_IN_FLASH
 187 #define CONFIG_ENV_SECT_SIZE    0x10000 /* size of one complete sector  */
 188 /* the environment is located before u-boot */
 189 #define CONFIG_ENV_ADDR         (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE)
 190
 191 /* Address and size of Redundant Environment Sector     */
 192 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 193 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SECT_SIZE)
 194 #endif
 195
 196 #ifdef CONFIG_ENV_IS_IN_EEPROM
 197 #define CONFIG_ENV_SIZE         0x400           /* Size of Environment vars */
 198 #define CONFIG_ENV_OFFSET               0x00000000
 199 #define CONFIG_SYS_ENABLE_CRC_16        1       /* Intrinsyc formatting used crc16 */
 200 #endif
 201
 202 /* partly from PPCBoot */
 203 /* NAND */
 204 #define CONFIG_NAND
 205 #ifdef CONFIG_NAND
 206 #define CONFIG_SYS_NAND_BASE   0x60000000
 207 #define CONFIG_SYS_NAND_CS      10   /* our CS is GPIO10 */
 208 #define CONFIG_SYS_NAND_RDY     23   /* our RDY is GPIO23 */
 209 #define CONFIG_SYS_NAND_CE      24   /* our CE is GPIO24  */
 210 #define CONFIG_SYS_NAND_CLE     31   /* our CLE is GPIO31 */
 211 #define CONFIG_SYS_NAND_ALE     30   /* our ALE is GPIO30 */
 212 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 213
 214 #endif
 215
 216 /*-----------------------------------------------------------------------
 217  * Definitions for initial stack pointer and data area (in data cache)
 218  */
 219 /* use on chip memory (OCM) for temperary stack until sdram is tested */
 220 /* see ./arch/powerpc/cpu/ppc4xx/start.S */
 221 #define CONFIG_SYS_TEMP_STACK_OCM       1
 222
 223 /* On Chip Memory location */
 224 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 225 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 226 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM               */
 227 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 228
 229 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 230 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 231
 232 /*-----------------------------------------------------------------------
 233  * External Bus Controller (EBC) Setup
 234  * Taken from PPCBoot board/icecube/icecube.h
 235  */
 236
 237 /* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
 238 #define CONFIG_SYS_EBC_PB0AP            0x04002480
 239 /* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
 240 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000
 241 #define CONFIG_SYS_EBC_PB1AP           0x04005480
 242 #define CONFIG_SYS_EBC_PB1CR           0x60018000
 243 #define CONFIG_SYS_EBC_PB2AP           0x00000000
 244 #define CONFIG_SYS_EBC_PB2CR           0x00000000
 245 #define CONFIG_SYS_EBC_PB3AP           0x00000000
 246 #define CONFIG_SYS_EBC_PB3CR           0x00000000
 247 #define CONFIG_SYS_EBC_PB4AP           0x00000000
 248 #define CONFIG_SYS_EBC_PB4CR           0x00000000
 249
 250 /*-----------------------------------------------------------------------
 251  * Definitions for GPIO setup (PPC405EP specific)
 252  *
 253  * Taken in part from PPCBoot board/icecube/icecube.h
 254  */
 255 /* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
 256 #define CONFIG_SYS_GPIO0_OSRL           0x55555550
 257 #define CONFIG_SYS_GPIO0_OSRH           0x00000110
 258 #define CONFIG_SYS_GPIO0_ISR1L          0x00000000
 259 #define CONFIG_SYS_GPIO0_ISR1H          0x15555445
 260 #define CONFIG_SYS_GPIO0_TSRL           0x00000000
 261 #define CONFIG_SYS_GPIO0_TSRH           0x00000000
 262 #define CONFIG_SYS_GPIO0_TCR            0xFFFF8097
 263 #define CONFIG_SYS_GPIO0_ODR            0x00000000
 264
 265 #if defined(CONFIG_CMD_KGDB)
 266 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
 267 #endif
 268
 269 /* ENVIRONMENT VARS */
 270
 271 #define CONFIG_IPADDR           192.168.1.67
 272 #define CONFIG_SERVERIP         192.168.1.50
 273 #define CONFIG_GATEWAYIP        192.168.1.1
 274 #define CONFIG_NETMASK          255.255.255.0
 275 #define CONFIG_LOADADDR         300000
 276 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 277
 278 /* pass open firmware flat tree */
 279 #define CONFIG_OF_LIBFDT        1
 280
 281 #endif  /* __CONFIG_H */