include/configs/quad100hd.h

   1 /*
   2  * (C) Copyright 2008
   3  * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /************************************************************************
  25  * quad100hd.h - configuration for Quad100hd board
  26  ***********************************************************************/
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*-----------------------------------------------------------------------
  31  * High Level Configuration Options
  32  *----------------------------------------------------------------------*/
  33 #define CONFIG_QUAD100HD        1               /* Board is Quad100hd   */
  34 #define CONFIG_4xx              1               /* ... PPC4xx family    */
  35 #define CONFIG_405EP            1               /* Specifc 405EP support*/
  36
  37 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  38
  39 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  40
  41 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  42
  43 #define PLLMR0_DEFAULT          PLLMR0_266_133_66 /* no PCI */
  44 #define PLLMR1_DEFAULT          PLLMR1_266_133_66 /* no PCI */
  45
  46 /* the environment is in the EEPROM by default */
  47 #define CONFIG_ENV_IS_IN_EEPROM
  48 #undef CONFIG_ENV_IS_IN_FLASH
  49
  50 #define CONFIG_PPC4xx_EMAC
  51 #define CONFIG_NET_MULTI        1
  52 #define CONFIG_HAS_ETH1         1
  53 #define CONFIG_MII              1       /* MII PHY management           */
  54 #define CONFIG_PHY_ADDR         0x01    /* PHY address                  */
  55 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* Number of ethernet rx buffers & descriptors */
  56 #define CONFIG_PHY_RESET        1
  57 #define CONFIG_PHY_RESET_DELAY  300     /* PHY RESET recovery delay     */
  58
  59 /*
  60  * Command line configuration.
  61  */
  62 #include <config_cmd_default.h>
  63
  64 #undef CONFIG_CMD_ASKENV
  65 #undef CONFIG_CMD_CACHE
  66 #define CONFIG_CMD_DHCP
  67 #undef CONFIG_CMD_DIAG
  68 #define CONFIG_CMD_EEPROM
  69 #undef CONFIG_CMD_ELF
  70 #define CONFIG_CMD_I2C
  71 #undef CONFIG_CMD_IRQ
  72 #define CONFIG_CMD_JFFS2
  73 #undef CONFIG_CMD_LOG
  74 #undef CONFIG_CMD_MII
  75 #define CONFIG_CMD_NAND
  76 #undef CONFIG_CMD_PING
  77 #define CONFIG_CMD_REGINFO
  78
  79 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
  80
  81 /*-----------------------------------------------------------------------
  82  * SDRAM
  83  *----------------------------------------------------------------------*/
  84 /*
  85  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  86  */
  87 #define CONFIG_SDRAM_BANK0  1
  88
  89 /* FIX! SDRAM timings used in datasheet */
  90 #define CONFIG_SYS_SDRAM_CL            3       /* CAS latency */
  91 #define CONFIG_SYS_SDRAM_tRP           20      /* PRECHARGE command period */
  92 #define CONFIG_SYS_SDRAM_tRC           66      /* ACTIVE-to-ACTIVE command period */
  93 #define CONFIG_SYS_SDRAM_tRCD          20      /* ACTIVE-to-READ delay */
  94 #define CONFIG_SYS_SDRAM_tRFC          66      /* Auto refresh period */
  95
  96 /*
  97  * JFFS2
  98  */
  99 #define CONFIG_SYS_JFFS2_FIRST_BANK    0
 100 #ifdef  CONFIG_SYS_KERNEL_IN_JFFS2
 101 #define CONFIG_SYS_JFFS2_FIRST_SECTOR  0   /* JFFS starts at block 0 */
 102 #else /* kernel not in JFFS */
 103 #define CONFIG_SYS_JFFS2_FIRST_SECTOR  8   /* block 0-7 is kernel (1MB = 8 sectors) */
 104 #endif
 105 #define CONFIG_SYS_JFFS2_NUM_BANKS     1
 106
 107 /*-----------------------------------------------------------------------
 108  * Serial Port
 109  *----------------------------------------------------------------------*/
 110 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 111 #define CONFIG_SYS_NS16550
 112 #define CONFIG_SYS_NS16550_SERIAL
 113 #define CONFIG_SYS_NS16550_REG_SIZE     1
 114 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 115 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK                     /* external serial clock */
 116 #define CONFIG_SYS_BASE_BAUD            691200
 117 #define CONFIG_BAUDRATE         115200
 118 #define CONFIG_SERIAL_MULTI
 119
 120 /* The following table includes the supported baudrates */
 121 #define CONFIG_SYS_BAUDRATE_TABLE       \
 122         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 123
 124 /*-----------------------------------------------------------------------
 125  * Miscellaneous configurable options
 126  *----------------------------------------------------------------------*/
 127 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 128 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 129 #if defined(CONFIG_CMD_KGDB)
 130 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 131 #else
 132 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 133 #endif
 134 #define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 135 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 136 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size  */
 137
 138 #define CONFIG_SYS_MEMTEST_START        0x0400000 /* memtest works on           */
 139 #define CONFIG_SYS_MEMTEST_END          0x0C00000 /* 4 ... 12 MB in DRAM        */
 140
 141 #define CONFIG_SYS_LOAD_ADDR            0x100000  /* default load address       */
 142 #define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_info (bd_t) */
 143
 144 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 145
 146 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 147 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 148
 149 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 150 #define CONFIG_LOOPW            1       /* enable loopw command         */
 151 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 152 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 153 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 154
 155 /*-----------------------------------------------------------------------
 156  * I2C
 157  *----------------------------------------------------------------------*/
 158 #define CONFIG_HARD_I2C         1               /* I2C with hardware support    */
 159 #undef  CONFIG_SOFT_I2C                         /* I2C bit-banged               */
 160 #define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 161 #define CONFIG_SYS_I2C_SPEED            400000          /* I2C speed and slave address  */
 162 #define CONFIG_SYS_I2C_SLAVE            0x7F
 163
 164 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50            /* base address */
 165 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2               /* bytes of address */
 166
 167 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* 8 byte write page size */
 168 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 169 #define CONFIG_SYS_EEPROM_SIZE                  0x2000
 170
 171 /*-----------------------------------------------------------------------
 172  * Start addresses for the final memory configuration
 173  * (Set up by the startup code)
 174  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 175  */
 176 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 177 #define CONFIG_SYS_FLASH_BASE           0xFFC00000
 178 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
 179 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 180 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE)
 181
 182 /*
 183  * For booting Linux, the board info and command line data
 184  * have to be in the first 8 MB of memory, since this is
 185  * the maximum mapped by the Linux kernel during initialization.
 186  */
 187 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 188
 189 /*-----------------------------------------------------------------------
 190  * FLASH organization
 191  */
 192 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 193 #define CONFIG_FLASH_CFI_DRIVER
 194
 195 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 196
 197 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks   */
 198 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max number of sectors on one chip */
 199
 200 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms) */
 201 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms) */
 202
 203 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster) */
 204 #define CONFIG_SYS_FLASH_INCREMENT      0       /* there is only one bank         */
 205
 206 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 207 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash */
 208
 209 #ifdef CONFIG_ENV_IS_IN_FLASH
 210 #define CONFIG_ENV_SECT_SIZE    0x10000 /* size of one complete sector  */
 211 /* the environment is located before u-boot */
 212 #define CONFIG_ENV_ADDR         (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE)
 213
 214 /* Address and size of Redundant Environment Sector     */
 215 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 216 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SECT_SIZE)
 217 #endif
 218
 219 #ifdef CONFIG_ENV_IS_IN_EEPROM
 220 #define CONFIG_ENV_SIZE         0x400           /* Size of Environment vars */
 221 #define CONFIG_ENV_OFFSET               0x00000000
 222 #define CONFIG_SYS_ENABLE_CRC_16        1       /* Intrinsyc formatting used crc16 */
 223 #endif
 224
 225 /* partly from PPCBoot */
 226 /* NAND */
 227 #define CONFIG_NAND
 228 #ifdef CONFIG_NAND
 229 #define CONFIG_SYS_NAND_BASE   0x60000000
 230 #define CONFIG_SYS_NAND_CS      10   /* our CS is GPIO10 */
 231 #define CONFIG_SYS_NAND_RDY     23   /* our RDY is GPIO23 */
 232 #define CONFIG_SYS_NAND_CE      24   /* our CE is GPIO24  */
 233 #define CONFIG_SYS_NAND_CLE     31   /* our CLE is GPIO31 */
 234 #define CONFIG_SYS_NAND_ALE     30   /* our ALE is GPIO30 */
 235 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 236
 237 #endif
 238
 239 /*-----------------------------------------------------------------------
 240  * Definitions for initial stack pointer and data area (in data cache)
 241  */
 242 /* use on chip memory (OCM) for temperary stack until sdram is tested */
 243 /* see ./arch/powerpc/cpu/ppc4xx/start.S */
 244 #define CONFIG_SYS_TEMP_STACK_OCM       1
 245
 246 /* On Chip Memory location */
 247 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 248 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 249 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM               */
 250 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 251
 252 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 253 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 254
 255 /*-----------------------------------------------------------------------
 256  * External Bus Controller (EBC) Setup
 257  * Taken from PPCBoot board/icecube/icecube.h
 258  */
 259
 260 /* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
 261 #define CONFIG_SYS_EBC_PB0AP            0x04002480
 262 /* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
 263 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000
 264 #define CONFIG_SYS_EBC_PB1AP           0x04005480
 265 #define CONFIG_SYS_EBC_PB1CR           0x60018000
 266 #define CONFIG_SYS_EBC_PB2AP           0x00000000
 267 #define CONFIG_SYS_EBC_PB2CR           0x00000000
 268 #define CONFIG_SYS_EBC_PB3AP           0x00000000
 269 #define CONFIG_SYS_EBC_PB3CR           0x00000000
 270 #define CONFIG_SYS_EBC_PB4AP           0x00000000
 271 #define CONFIG_SYS_EBC_PB4CR           0x00000000
 272
 273 /*-----------------------------------------------------------------------
 274  * Definitions for GPIO setup (PPC405EP specific)
 275  *
 276  * Taken in part from PPCBoot board/icecube/icecube.h
 277  */
 278 /* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
 279 #define CONFIG_SYS_GPIO0_OSRL           0x55555550
 280 #define CONFIG_SYS_GPIO0_OSRH           0x00000110
 281 #define CONFIG_SYS_GPIO0_ISR1L          0x00000000
 282 #define CONFIG_SYS_GPIO0_ISR1H          0x15555445
 283 #define CONFIG_SYS_GPIO0_TSRL           0x00000000
 284 #define CONFIG_SYS_GPIO0_TSRH           0x00000000
 285 #define CONFIG_SYS_GPIO0_TCR            0xFFFF8097
 286 #define CONFIG_SYS_GPIO0_ODR            0x00000000
 287
 288 #if defined(CONFIG_CMD_KGDB)
 289 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
 290 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
 291 #endif
 292
 293 /* ENVIRONMENT VARS */
 294
 295 #define CONFIG_IPADDR           192.168.1.67
 296 #define CONFIG_SERVERIP         192.168.1.50
 297 #define CONFIG_GATEWAYIP        192.168.1.1
 298 #define CONFIG_NETMASK          255.255.255.0
 299 #define CONFIG_LOADADDR         300000
 300 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 301
 302 /* pass open firmware flat tree */
 303 #define CONFIG_OF_LIBFDT        1
 304
 305 #endif  /* __CONFIG_H */