include/configs/rk3288_common.h

   1 /*
   2  * (C) Copyright 2015 Google, Inc
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_RK3288_COMMON_H
   8 #define __CONFIG_RK3288_COMMON_H
   9
  10 #include <asm/arch/hardware.h>
  11 #include "rockchip-common.h"
  12
  13 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
  14 #define CONFIG_SYS_NO_FLASH
  15 #define CONFIG_NR_DRAM_BANKS            1
  16 #define CONFIG_ENV_SIZE                 0x2000
  17 #define CONFIG_SYS_MAXARGS              16
  18 #define CONFIG_BAUDRATE                 115200
  19 #define CONFIG_SYS_MALLOC_LEN           (32 << 20)
  20 #define CONFIG_SYS_CBSIZE               1024
  21 #define CONFIG_SYS_THUMB_BUILD
  22
  23 #define CONFIG_SYS_TIMER_RATE           (24 * 1000 * 1000)
  24 #define CONFIG_SYS_TIMER_BASE           0xff810020 /* TIMER7 */
  25 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMER_BASE + 8)
  26
  27 #define CONFIG_SPL_FRAMEWORK
  28 #define CONFIG_SYS_NS16550_MEM32
  29 #define CONFIG_SPL_BOARD_INIT
  30
  31 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
  32 /* Bootrom will load u-boot binary to 0x0 once return from SPL */
  33 #define CONFIG_SYS_TEXT_BASE            0x00000000
  34 #else
  35 #define CONFIG_SYS_TEXT_BASE            0x00100000
  36 #endif
  37 #define CONFIG_SYS_INIT_SP_ADDR         0x00100000
  38 #define CONFIG_SYS_LOAD_ADDR            0x00800800
  39 #define CONFIG_SPL_STACK                0xff718000
  40 #define CONFIG_SPL_TEXT_BASE            0xff704004
  41
  42 /* MMC/SD IP block */
  43 #define CONFIG_GENERIC_MMC
  44 #define CONFIG_BOUNCE_BUFFER
  45
  46 #define CONFIG_FAT_WRITE
  47 #define CONFIG_PARTITION_UUIDS
  48 #define CONFIG_CMD_PART
  49
  50 /* RAW SD card / eMMC locations. */
  51 #define CONFIG_SYS_SPI_U_BOOT_OFFS      (128 << 10)
  52
  53 /* FAT sd card locations. */
  54 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
  55 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
  56
  57 #define CONFIG_SYS_SDRAM_BASE           0
  58 #define CONFIG_NR_DRAM_BANKS            1
  59 #define SDRAM_BANK_SIZE                 (2UL << 30)
  60
  61 #define CONFIG_SPI_FLASH
  62 #define CONFIG_SPI
  63 #define CONFIG_SF_DEFAULT_SPEED 20000000
  64
  65 #ifndef CONFIG_SPL_BUILD
  66 /* usb otg */
  67 #define CONFIG_USB_GADGET
  68 #define CONFIG_USB_GADGET_DUALSPEED
  69 #define CONFIG_USB_GADGET_DWC2_OTG
  70 #define CONFIG_ROCKCHIP_USB2_PHY
  71 #define CONFIG_USB_GADGET_VBUS_DRAW     0
  72
  73 /* fastboot  */
  74 #define CONFIG_CMD_FASTBOOT
  75 #define CONFIG_USB_FUNCTION_FASTBOOT
  76 #define CONFIG_FASTBOOT_FLASH
  77 #define CONFIG_FASTBOOT_FLASH_MMC_DEV   1       /* eMMC */
  78 #define CONFIG_FASTBOOT_BUF_ADDR        CONFIG_SYS_LOAD_ADDR
  79 #define CONFIG_FASTBOOT_BUF_SIZE        0x08000000
  80
  81 /* usb mass storage */
  82 #define CONFIG_USB_FUNCTION_MASS_STORAGE
  83 #define CONFIG_CMD_USB_MASS_STORAGE
  84
  85 #define CONFIG_USB_GADGET_DOWNLOAD
  86 #define CONFIG_G_DNL_MANUFACTURER       "Rockchip"
  87 #define CONFIG_G_DNL_VENDOR_NUM         0x2207
  88 #define CONFIG_G_DNL_PRODUCT_NUM        0x320a
  89
  90 #define ENV_MEM_LAYOUT_SETTINGS \
  91         "scriptaddr=0x00000000\0" \
  92         "pxefile_addr_r=0x00100000\0" \
  93         "fdt_addr_r=0x01f00000\0" \
  94         "kernel_addr_r=0x02000000\0" \
  95         "ramdisk_addr_r=0x04000000\0"
  96
  97 #include <config_distro_bootcmd.h>
  98
  99 /* Linux fails to load the fdt if it's loaded above 256M on a Rock 2 board, so
 100  * limit the fdt reallocation to that */
 101 #define CONFIG_EXTRA_ENV_SETTINGS \
 102         "fdt_high=0x0fffffff\0" \
 103         "initrd_high=0x0fffffff\0" \
 104         "partitions=" PARTS_DEFAULT \
 105         ENV_MEM_LAYOUT_SETTINGS \
 106         ROCKCHIP_DEVICE_SETTINGS \
 107         BOOTENV
 108 #endif
 109
 110 #define CONFIG_BOARD_LATE_INIT
 111 #define CONFIG_PREBOOT
 112
 113 #endif