include/configs/rmu.h

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31
  32 /*
  33  * High Level Configuration Options
  34  * (easy to change)
  35  */
  36
  37 #undef CONFIG_MPC860
  38 #define CONFIG_MPC850           1       /* This is a MPC850 CPU         */
  39 #define CONFIG_RPXLITE          1       /* RMU is the RPXlite clone */
  40 #define CONFIG_RMU                      1
  41
  42 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  43 #undef  CONFIG_8xx_CONS_SMC2
  44 #undef  CONFIG_8xx_CONS_NONE
  45 #define CONFIG_BAUDRATE         9600    /* console baudrate = 9600bps   */
  46 #if 0
  47 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  48 #else
  49 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  50 #endif
  51
  52 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  53
  54 #undef  CONFIG_BOOTARGS
  55 #define CONFIG_BOOTCOMMAND                                                      \
  56         "bootp; "                                                               \
  57         "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "     \
  58         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; "   \
  59         "bootm"
  60
  61 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  62 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  63
  64 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  65
  66 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  67
  68 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  69 #include <cmd_confdefs.h>
  70
  71 /*
  72  * Miscellaneous configurable options
  73  */
  74 #define CFG_LONGHELP                    /* undef to save memory         */
  75 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
  76 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  77 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
  78 #else
  79 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
  80 #endif
  81 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  82 #define CFG_MAXARGS     16              /* max number of command args   */
  83 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
  84
  85 #define CFG_MEMTEST_START       0x0040000       /* memtest works on     */
  86 #define CFG_MEMTEST_END         0x00C0000       /* 4 ... 12 MB in DRAM  */
  87
  88 #define CFG_LOAD_ADDR           0x100000        /* default load address */
  89
  90 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
  91
  92 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
  93
  94 /*
  95  * Low Level Configuration Settings
  96  * (address mappings, register initial values, etc.)
  97  * You should know what you are doing if you make changes here.
  98  */
  99 /*-----------------------------------------------------------------------
 100  * Internal Memory Mapped Register
 101  */
 102 #define CFG_IMMR                0xFA200000
 103
 104 /*-----------------------------------------------------------------------
 105  * Definitions for initial stack pointer and data area (in DPRAM)
 106  */
 107 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 108 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 109 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 110 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 111 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 112
 113 /*-----------------------------------------------------------------------
 114  * Start addresses for the final memory configuration
 115  * (Set up by the startup code)
 116  * Please note that CFG_SDRAM_BASE _must_ start at 0
 117  */
 118 #define CFG_SDRAM_BASE          0x00000000
 119 #define CFG_FLASH_BASE  0xFF800000
 120 /*%%% #define CFG_FLASH_BASE            0xFFF00000 */
 121 #if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
 122 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 123 #else
 124 #define CFG_MONITOR_LEN         (128 << 10)     /* Reserve 128 kB for Monitor   */
 125 #endif
 126 #define CFG_MONITOR_BASE        0xFFF00000
 127 /*%%% #define CFG_MONITOR_BASE  CFG_FLASH_BASE */
 128 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 129
 130 /*
 131  * For booting Linux, the board info and command line data
 132  * have to be in the first 8 MB of memory, since this is
 133  * the maximum mapped by the Linux kernel during initialization.
 134  */
 135 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 136
 137 /*-----------------------------------------------------------------------
 138  * FLASH organization
 139  */
 140 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 141 #define CFG_MAX_FLASH_SECT      35      /* max number of sectors on one chip    */
 142
 143 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 144 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 145
 146 #define CFG_ENV_IS_IN_FLASH     1
 147 #define CFG_ENV_OFFSET      0x00740000  /*   Offset   of Environment Sector     */
 148 #define CFG_ENV_SIZE            0x40000 /* Total Size of Environment Sector     */
 149 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + CFG_ENV_OFFSET)
 150
 151 /* Address and size of Redundant Environment Sector     */
 152 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SIZE)
 153 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 154
 155 /*-----------------------------------------------------------------------
 156  * Cache Configuration
 157  */
 158 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 159 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 160 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 161 #endif
 162
 163 /*-----------------------------------------------------------------------
 164  * SYPCR - System Protection Control                            11-9
 165  * SYPCR can only be written once after reset!
 166  *-----------------------------------------------------------------------
 167  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 168  */
 169 #if defined(CONFIG_WATCHDOG)
 170 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 171                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 172 #else
 173 #define CFG_SYPCR       (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 174 #endif
 175
 176 /*-----------------------------------------------------------------------
 177  * SIUMCR - SIU Module Configuration                            11-6
 178  *-----------------------------------------------------------------------
 179  * PCMCIA config., multi-function pin tri-state
 180  */
 181 #define CFG_SIUMCR      (SIUMCR_MLRC10)
 182
 183 /*-----------------------------------------------------------------------
 184  * TBSCR - Time Base Status and Control                         11-26
 185  *-----------------------------------------------------------------------
 186  * Clear Reference Interrupt Status, Timebase freezing enabled
 187  */
 188 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
 189
 190 /*-----------------------------------------------------------------------
 191  * RTCSC - Real-Time Clock Status and Control Register          11-27
 192  *-----------------------------------------------------------------------
 193  */
 194 /*%%%#define CFG_RTCSC  (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
 195 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_RTE)
 196
 197 /*-----------------------------------------------------------------------
 198  * PISCR - Periodic Interrupt Status and Control                11-31
 199  *-----------------------------------------------------------------------
 200  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 201  */
 202 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
 203
 204 /*-----------------------------------------------------------------------
 205  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 206  *-----------------------------------------------------------------------
 207  * Reset PLL lock status sticky bit, timer expired status bit and timer
 208  * interrupt status bit
 209  *
 210  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 211  */
 212 /* up to 50 MHz we use a 1:1 clock */
 213 #define CFG_PLPRCR      ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
 214
 215 /*-----------------------------------------------------------------------
 216  * SCCR - System Clock and reset Control Register               15-27
 217  *-----------------------------------------------------------------------
 218  * Set clock output, timebase and RTC source and divider,
 219  * power management and some other internal clocks
 220  */
 221 #define SCCR_MASK       SCCR_EBDF00
 222 /* up to 50 MHz we use a 1:1 clock */
 223 #define CFG_SCCR        (SCCR_COM00 | SCCR_TBS)
 224
 225 /*-----------------------------------------------------------------------
 226  * PCMCIA stuff
 227  *-----------------------------------------------------------------------
 228  *
 229  */
 230 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 231 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 232 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 233 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 234 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 235 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 236 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 237 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 238
 239 /*-----------------------------------------------------------------------
 240  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 241  *-----------------------------------------------------------------------
 242  */
 243
 244 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 245
 246 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 247 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 248 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 249
 250 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 251 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 252
 253 #define CFG_ATA_IDE0_OFFSET     0x0000
 254
 255 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 256
 257 /* Offset for data I/O                  */
 258 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 259
 260 /* Offset for normal register accesses  */
 261 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 262
 263 /* Offset for alternate registers       */
 264 #define CFG_ATA_ALT_OFFSET      0x0100
 265
 266 /*-----------------------------------------------------------------------
 267  *
 268  *-----------------------------------------------------------------------
 269  *
 270  */
 271 /*#define       CFG_DER 0x2002000F*/
 272 #define CFG_DER 0
 273
 274 /*
 275  * Init Memory Controller:
 276  *
 277  * BR0 and OR0 (FLASH)
 278  */
 279
 280 #define FLASH_BASE_PRELIM       0xFE000000      /* FLASH base */
 281 #define CFG_PRELIM_OR_AM        0xFE000000      /* OR addr mask */
 282
 283 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
 284 #define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
 285
 286 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 287 #define CFG_BR0_PRELIM  ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
 288
 289 /*
 290  * BR1 and OR1 (SDRAM)
 291  *
 292  */
 293 #define SDRAM_BASE_PRELIM       0x00000000      /* SDRAM base   */
 294 #define SDRAM_MAX_SIZE          0x01000000      /* max 16 MB */
 295
 296 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 297 #define CFG_OR_TIMING_SDRAM     0x00000E00
 298
 299 #define CFG_OR1_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
 300 #define CFG_BR1_PRELIM  ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 301
 302 /* RPXLITE mem setting */
 303 #define CFG_BR3_PRELIM  0xFA400001              /* BCSR */
 304 #define CFG_OR3_PRELIM  0xFFFF8910
 305 #define CFG_BR4_PRELIM  0xFA000401              /* NVRAM&SRAM */
 306 #define CFG_OR4_PRELIM  0xFFFE0970
 307
 308 /*
 309  * Memory Periodic Timer Prescaler
 310  */
 311
 312 /* periodic timer for refresh */
 313 #define CFG_MAMR_PTA    20
 314
 315 /*
 316  * Refresh clock Prescalar
 317  */
 318 #define CFG_MPTPR       MPTPR_PTP_DIV2
 319
 320 /*
 321  * MAMR settings for SDRAM
 322  */
 323
 324 /* 10 column SDRAM */
 325 #define CFG_MAMR_10COL  ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 326                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 327                          MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
 328
 329 /*
 330  * Internal Definitions
 331  *
 332  * Boot Flags
 333  */
 334 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH     */
 335 #define BOOTFLAG_WARM   0x02    /* Software reboot                      */
 336
 337 /*
 338  * BCSRx
 339  *
 340  * Board Status and Control Registers
 341  *
 342  */
 343
 344 #define BCSR0 0xFA400000
 345 #define BCSR1 0xFA400001
 346 #define BCSR2 0xFA400002
 347 #define BCSR3 0xFA400003
 348
 349 #define BCSR0_ENMONXCVR 0x01    /* Monitor XVCR Control */
 350 #define BCSR0_ENNVRAM   0x02    /* CS4# Control */
 351 #define BCSR0_LED5      0x04    /* LED5 control 0='on' 1='off' */
 352 #define BCSR0_LED4      0x08    /* LED4 control 0='on' 1='off' */
 353 #define BCSR0_FULLDPLX  0x10    /* Ethernet XCVR Control */
 354 #define BCSR0_COLTEST   0x20
 355 #define BCSR0_ETHLPBK   0x40
 356 #define BCSR0_ETHEN     0x80
 357
 358 #define BCSR1_PCVCTL7   0x01    /* PC Slot B Control */
 359 #define BCSR1_PCVCTL6   0x02
 360 #define BCSR1_PCVCTL5   0x04
 361 #define BCSR1_PCVCTL4   0x08
 362 #define BCSR1_IPB5SEL   0x10
 363
 364 #define BCSR2_ENPA5HDR  0x08    /* USB Control */
 365 #define BCSR2_ENUSBCLK  0x10
 366 #define BCSR2_USBPWREN  0x20
 367 #define BCSR2_USBSPD    0x40
 368 #define BCSR2_USBSUSP   0x80
 369
 370 #define BCSR3_BWRTC     0x01    /* Real Time Clock Battery */
 371 #define BCSR3_BWNVR     0x02    /* NVRAM Battery */
 372 #define BCSR3_RDY_BSY   0x04    /* Flash Operation */
 373 #define BCSR3_RPXL      0x08    /* Reserved (reads back '1') */
 374 #define BCSR3_D27       0x10    /* Dip Switch settings */
 375 #define BCSR3_D26       0x20
 376 #define BCSR3_D25       0x40
 377 #define BCSR3_D24       0x80
 378
 379 #endif  /* __CONFIG_H */