include/configs/rmu.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31
  32 /*
  33  * High Level Configuration Options
  34  * (easy to change)
  35  */
  36
  37 #undef CONFIG_MPC860
  38 #define CONFIG_MPC850           1       /* This is a MPC850 CPU         */
  39 #define CONFIG_RPXLITE          1       /* RMU is the RPXlite clone */
  40 #define CONFIG_RMU                      1
  41
  42 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  43 #undef  CONFIG_8xx_CONS_SMC2
  44 #undef  CONFIG_8xx_CONS_NONE
  45 #define CONFIG_BAUDRATE         9600    /* console baudrate = 9600bps   */
  46 #if 0
  47 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  48 #else
  49 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  50 #endif
  51
  52 #undef  CONFIG_BOOTARGS
  53 #define CONFIG_BOOTCOMMAND                                                      \
  54         "bootp; "                                                               \
  55         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  56         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
  57         "bootm"
  58
  59 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  60 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  61
  62 /* enable I2C and select the hardware/software driver */
  63 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
  64 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
  65
  66 #define CONFIG_SYS_I2C_SPEED            40000   /* 40 kHz is supposed to work   */
  67 #define CONFIG_SYS_I2C_SLAVE            0xFE
  68
  69 /* Software (bit-bang) I2C driver configuration */
  70 #define PB_SCL          0x00000020      /* PB 26 */
  71 #define PB_SDA          0x00000010      /* PB 27 */
  72
  73 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
  74 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
  75 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
  76 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
  77 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
  78                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
  79 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
  80                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
  81 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
  82
  83 /* M41T11 Serial Access Timekeeper(R) SRAM */
  84 #define CONFIG_RTC_M41T11 1
  85 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  86 #define CONFIG_SYS_M41T11_BASE_YEAR 1900        /* play along with the linux driver */
  87
  88 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  89
  90
  91 /*
  92  * Command line configuration.
  93  */
  94 #include <config_cmd_default.h>
  95
  96 #define CONFIG_CMD_DATE
  97 #define CONFIG_CMD_DHCP
  98 #define CONFIG_CMD_I2C
  99 #define CONFIG_CMD_NFS
 100 #define CONFIG_CMD_SNTP
 101
 102
 103 /*
 104  * BOOTP options
 105  */
 106 #define CONFIG_BOOTP_SUBNETMASK
 107 #define CONFIG_BOOTP_GATEWAY
 108 #define CONFIG_BOOTP_HOSTNAME
 109 #define CONFIG_BOOTP_BOOTPATH
 110 #define CONFIG_BOOTP_BOOTFILESIZE
 111
 112
 113 #define CONFIG_AUTOBOOT_KEYED           /* Enable password protection */
 114 #define CONFIG_AUTOBOOT_PROMPT          \
 115         "\nEnter password - autoboot in %d sec...\n", bootdelay
 116 #define CONFIG_AUTOBOOT_DELAY_STR       "system"
 117
 118 /*
 119  * Miscellaneous configurable options
 120  */
 121 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 122 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 123 #if defined(CONFIG_CMD_KGDB)
 124 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 125 #else
 126 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 127 #endif
 128 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 129 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 130 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 131
 132 #define CONFIG_SYS_MEMTEST_START        0x0040000       /* memtest works on     */
 133 #define CONFIG_SYS_MEMTEST_END          0x00C0000       /* 4 ... 12 MB in DRAM  */
 134
 135 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 136
 137 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 138
 139 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 140
 141 /*
 142  * Low Level Configuration Settings
 143  * (address mappings, register initial values, etc.)
 144  * You should know what you are doing if you make changes here.
 145  */
 146 /*-----------------------------------------------------------------------
 147  * Internal Memory Mapped Register
 148  */
 149 #define CONFIG_SYS_IMMR         0xFA200000
 150
 151 /*-----------------------------------------------------------------------
 152  * Definitions for initial stack pointer and data area (in DPRAM)
 153  */
 154 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 155 #define CONFIG_SYS_INIT_RAM_END 0x2F00  /* End of used area in DPRAM    */
 156 #define CONFIG_SYS_GBL_DATA_SIZE        64  /* size in bytes reserved for initial data */
 157 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 158 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 159
 160 /*-----------------------------------------------------------------------
 161  * Start addresses for the final memory configuration
 162  * (Set up by the startup code)
 163  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 164  */
 165 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 166 #define CONFIG_SYS_FLASH_BASE           (0-flash_info[0].size)  /* Put flash at end     */
 167 #if defined(DEBUG) || defined(CONFIG_CMD_IDE)
 168 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 169 #else
 170 #define CONFIG_SYS_MONITOR_LEN          (128 << 10)     /* Reserve 128 kB for Monitor   */
 171 #endif
 172 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
 173 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 174
 175 /*
 176  * For booting Linux, the board info and command line data
 177  * have to be in the first 8 MB of memory, since this is
 178  * the maximum mapped by the Linux kernel during initialization.
 179  */
 180 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 181
 182 /*-----------------------------------------------------------------------
 183  * FLASH organization
 184  */
 185 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 186 #define CONFIG_SYS_MAX_FLASH_SECT       67      /* max number of sectors on one chip    */
 187
 188 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 189 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 190
 191 #define CONFIG_ENV_IS_IN_FLASH  1
 192 #define CONFIG_ENV_ADDR         ((TEXT_BASE) + 0x40000)
 193 #define CONFIG_ENV_SIZE         0x40000 /* Total Size of Environment Sector     */
 194
 195 /* Address and size of Redundant Environment Sector     */
 196 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
 197 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 198
 199 /*-----------------------------------------------------------------------
 200  * Reset address
 201  */
 202 #define CONFIG_SYS_RESET_ADDRESS        ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res)))
 203
 204 /*-----------------------------------------------------------------------
 205  * Cache Configuration
 206  */
 207 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 208 #if defined(CONFIG_CMD_KGDB)
 209 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 210 #endif
 211
 212 /*-----------------------------------------------------------------------
 213  * SYPCR - System Protection Control                            11-9
 214  * SYPCR can only be written once after reset!
 215  *-----------------------------------------------------------------------
 216  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 217  */
 218 #if defined(CONFIG_WATCHDOG)
 219 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 220                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 221 #else
 222 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 223 #endif
 224
 225 /*-----------------------------------------------------------------------
 226  * SIUMCR - SIU Module Configuration                            11-6
 227  *-----------------------------------------------------------------------
 228  * PCMCIA config., multi-function pin tri-state
 229  */
 230 #define CONFIG_SYS_SIUMCR       (SIUMCR_MLRC10)
 231
 232 /*-----------------------------------------------------------------------
 233  * TBSCR - Time Base Status and Control                         11-26
 234  *-----------------------------------------------------------------------
 235  * Clear Reference Interrupt Status, Timebase freezing enabled
 236  */
 237 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
 238
 239 /*-----------------------------------------------------------------------
 240  * RTCSC - Real-Time Clock Status and Control Register          11-27
 241  *-----------------------------------------------------------------------
 242  */
 243 /*%%%#define CONFIG_SYS_RTCSC   (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
 244 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_RTE)
 245
 246 /*-----------------------------------------------------------------------
 247  * PISCR - Periodic Interrupt Status and Control                11-31
 248  *-----------------------------------------------------------------------
 249  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 250  */
 251 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
 252
 253 /*-----------------------------------------------------------------------
 254  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 255  *-----------------------------------------------------------------------
 256  * Reset PLL lock status sticky bit, timer expired status bit and timer
 257  * interrupt status bit
 258  *
 259  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 260  */
 261 /* up to 50 MHz we use a 1:1 clock */
 262 #define CONFIG_SYS_PLPRCR       ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
 263
 264 /*-----------------------------------------------------------------------
 265  * SCCR - System Clock and reset Control Register               15-27
 266  *-----------------------------------------------------------------------
 267  * Set clock output, timebase and RTC source and divider,
 268  * power management and some other internal clocks
 269  */
 270 #define SCCR_MASK       SCCR_EBDF00
 271 /* up to 50 MHz we use a 1:1 clock */
 272 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS)
 273
 274 /*-----------------------------------------------------------------------
 275  * PCMCIA stuff
 276  *-----------------------------------------------------------------------
 277  *
 278  */
 279 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 280 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 281 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 282 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 283 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 284 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 285 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 286 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 287
 288 /*-----------------------------------------------------------------------
 289  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 290  *-----------------------------------------------------------------------
 291  */
 292
 293 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 294
 295 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 296 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 297 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 298
 299 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 300 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 301
 302 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 303
 304 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 305
 306 /* Offset for data I/O                  */
 307 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 308
 309 /* Offset for normal register accesses  */
 310 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 311
 312 /* Offset for alternate registers       */
 313 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 314
 315 /*-----------------------------------------------------------------------
 316  *
 317  *-----------------------------------------------------------------------
 318  *
 319  */
 320 /*#define       CONFIG_SYS_DER  0x2002000F*/
 321 #define CONFIG_SYS_DER  0
 322
 323 /*
 324  * Init Memory Controller:
 325  *
 326  * BR0 and OR0 (FLASH)
 327  */
 328
 329 #define FLASH_BASE_PRELIM       0xFC000000      /* FLASH base - up to 64 MB of flash */
 330 #define CONFIG_SYS_PRELIM_OR_AM 0xFC000000      /* OR addr mask - map 64 MB */
 331
 332 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
 333 #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
 334
 335 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 336 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
 337
 338 /*
 339  * BR1 and OR1 (SDRAM)
 340  *
 341  */
 342 #define SDRAM_BASE_PRELIM       0x00000000      /* SDRAM base   */
 343 #define SDRAM_MAX_SIZE          0x08000000      /* max 128 MB */
 344
 345 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 346 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000E00
 347
 348 #define CONFIG_SYS_OR1_PRELIM   (0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM ) /* map 256 MB */
 349 #define CONFIG_SYS_BR1_PRELIM   ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 350
 351 /* RPXLITE mem setting */
 352 #define CONFIG_SYS_NVRAM_BASE   0xFA000000              /* NVRAM & SRAM base */
 353 /*      IMMR:           0xFA200000                 IMMR base address - see above */
 354 #define CONFIG_SYS_BCSR_BASE    0xFA400000              /* BCSR base address */
 355
 356 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_BCSR_BASE | BR_V)                   /* BCSR */
 357 #define CONFIG_SYS_OR3_PRELIM   0xFFFF8910
 358 #define CONFIG_SYS_BR4_PRELIM  (CONFIG_SYS_NVRAM_BASE | BR_PS_8 | BR_V) /* NVRAM & SRAM */
 359 #define CONFIG_SYS_OR4_PRELIM   0xFFFE0970
 360
 361 /*
 362  * Memory Periodic Timer Prescaler
 363  */
 364
 365 /* periodic timer for refresh */
 366 #define CONFIG_SYS_MAMR_PTA     20
 367
 368 /*
 369  * Refresh clock Prescalar
 370  */
 371 #define CONFIG_SYS_MPTPR        MPTPR_PTP_DIV2
 372
 373 /*
 374  * MAMR settings for SDRAM
 375  */
 376
 377 /* 9 column SDRAM */
 378 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 379                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 380                          MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
 381
 382 /*
 383  * Internal Definitions
 384  *
 385  * Boot Flags
 386  */
 387 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH     */
 388 #define BOOTFLAG_WARM   0x02    /* Software reboot                      */
 389
 390 /*
 391  * BCSRx
 392  *
 393  * Board Status and Control Registers
 394  *
 395  */
 396
 397 #define BCSR0   (CONFIG_SYS_BCSR_BASE + 0)
 398 #define BCSR1   (CONFIG_SYS_BCSR_BASE + 1)
 399 #define BCSR2   (CONFIG_SYS_BCSR_BASE + 2)
 400 #define BCSR3   (CONFIG_SYS_BCSR_BASE + 3)
 401
 402 #define BCSR0_ENMONXCVR 0x01    /* Monitor XVCR Control */
 403 #define BCSR0_ENNVRAM   0x02    /* CS4# Control */
 404 #define BCSR0_LED5      0x04    /* LED5 control 0='on' 1='off' */
 405 #define BCSR0_LED4      0x08    /* LED4 control 0='on' 1='off' */
 406 #define BCSR0_FULLDPLX  0x10    /* Ethernet XCVR Control */
 407 #define BCSR0_COLTEST   0x20
 408 #define BCSR0_ETHLPBK   0x40
 409 #define BCSR0_ETHEN     0x80
 410
 411 #define BCSR1_PCVCTL7   0x01    /* PC Slot B Control */
 412 #define BCSR1_PCVCTL6   0x02
 413 #define BCSR1_PCVCTL5   0x04
 414 #define BCSR1_PCVCTL4   0x08
 415 #define BCSR1_IPB5SEL   0x10
 416
 417 #define BCSR2_ENPA5HDR  0x08    /* USB Control */
 418 #define BCSR2_ENUSBCLK  0x10
 419 #define BCSR2_USBPWREN  0x20
 420 #define BCSR2_USBSPD    0x40
 421 #define BCSR2_USBSUSP   0x80
 422
 423 #define BCSR3_BWRTC     0x01    /* Real Time Clock Battery */
 424 #define BCSR3_BWNVR     0x02    /* NVRAM Battery */
 425 #define BCSR3_RDY_BSY   0x04    /* Flash Operation */
 426 #define BCSR3_RPXL      0x08    /* Reserved (reads back '1') */
 427 #define BCSR3_D27       0x10    /* Dip Switch settings */
 428 #define BCSR3_D26       0x20
 429 #define BCSR3_D25       0x40
 430 #define BCSR3_D24       0x80
 431
 432 #endif  /* __CONFIG_H */