include/configs/sacsng.h

   1 /*
   2  * (C) Copyright 2000
   3  * Murray Jensen <Murray.Jensen@cmst.csiro.au>
   4  *
   5  * (C) Copyright 2000
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * (C) Copyright 2001
  10  * Advent Networks, Inc. <http://www.adventnetworks.com>
  11  * Jay Monkman <jtm@smoothsmoothie.com>
  12  *
  13  * Configuration settings for the SACSng 8260 board.
  14  *
  15  * SPDX-License-Identifier:     GPL-2.0+
  16  */
  17
  18 #ifndef __CONFIG_H
  19 #define __CONFIG_H
  20
  21 #define CONFIG_SYS_TEXT_BASE    0x40000000
  22
  23 #undef DEBUG_BOOTP_EXT        /* Debug received vendor fields */
  24
  25 #undef CONFIG_LOGBUFFER       /* External logbuffer support */
  26
  27 /*****************************************************************************
  28  *
  29  * These settings must match the way _your_ board is set up
  30  *
  31  *****************************************************************************/
  32
  33 /* What is the oscillator's (UX2) frequency in Hz? */
  34 #define CONFIG_8260_CLKIN  66666600
  35
  36 /*-----------------------------------------------------------------------
  37  * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
  38  *-----------------------------------------------------------------------
  39  * What should MODCK_H be? It is dependent on the oscillator
  40  * frequency, MODCK[1-3], and desired CPM and core frequencies.
  41  * Here are some example values (all frequencies are in MHz):
  42  *
  43  * MODCK_H   MODCK[1-3]  Osc    CPM    Core  S2-6   S2-7   S2-8
  44  * -------   ----------  ---    ---    ----  -----  -----  -----
  45  * 0x1       0x5         33     100    133   Open   Close  Open
  46  * 0x1       0x6         33     100    166   Open   Open   Close
  47  * 0x1       0x7         33     100    200   Open   Open   Open
  48  *
  49  * 0x2       0x2         33     133    133   Close  Open   Close
  50  * 0x2       0x3         33     133    166   Close  Open   Open
  51  * 0x2       0x4         33     133    200   Open   Close  Close
  52  * 0x2       0x5         33     133    233   Open   Close  Open
  53  * 0x2       0x6         33     133    266   Open   Open   Close
  54  *
  55  * 0x5       0x5         66     133    133   Open   Close  Open
  56  * 0x5       0x6         66     133    166   Open   Open   Close
  57  * 0x5       0x7         66     133    200   Open   Open   Open
  58  * 0x6       0x0         66     133    233   Close  Close  Close
  59  * 0x6       0x1         66     133    266   Close  Close  Open
  60  * 0x6       0x2         66     133    300   Close  Open   Close
  61  */
  62 #define CONFIG_SYS_SBC_MODCK_H 0x05
  63
  64 /* Define this if you want to boot from 0x00000100. If you don't define
  65  * this, you will need to program the bootloader to 0xfff00000, and
  66  * get the hardware reset config words at 0xfe000000. The simplest
  67  * way to do that is to program the bootloader at both addresses.
  68  * It is suggested that you just let U-Boot live at 0x00000000.
  69  */
  70 #define CONFIG_SYS_SBC_BOOT_LOW 1
  71
  72 /* What should the base address of the main FLASH be and how big is
  73  * it (in MBytes)?  This must contain CONFIG_SYS_TEXT_BASE from board/sacsng/config.mk
  74  * The main FLASH is whichever is connected to *CS0.
  75  */
  76 #define CONFIG_SYS_FLASH0_BASE 0x40000000
  77 #define CONFIG_SYS_FLASH0_SIZE 2
  78
  79 /* What should the base address of the secondary FLASH be and how big
  80  * is it (in Mbytes)?  The secondary FLASH is whichever is connected
  81  * to *CS6.
  82  */
  83 #define CONFIG_SYS_FLASH1_BASE 0x60000000
  84 #define CONFIG_SYS_FLASH1_SIZE 2
  85
  86 /* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
  87  */
  88 #define CONFIG_VERY_BIG_RAM     1
  89
  90 /* What should be the base address of SDRAM DIMM and how big is
  91  * it (in Mbytes)?  This will normally auto-configure via the SPD.
  92 */
  93 #define CONFIG_SYS_SDRAM0_BASE 0x00000000
  94 #define CONFIG_SYS_SDRAM0_SIZE 64
  95
  96 /*
  97  * Memory map example with 64 MB DIMM:
  98  *
  99  *     0x0000 0000     Exception Vector code, 8k
 100  *           :
 101  *     0x0000 1FFF
 102  *     0x0000 2000     Free for Application Use
 103  *           :
 104  *           :
 105  *
 106  *           :
 107  *           :
 108  *     0x03F5 FF30     Monitor Stack (Growing downward)
 109  *                     Monitor Stack Buffer (0x80)
 110  *     0x03F5 FFB0     Board Info Data
 111  *     0x03F6 0000     Malloc Arena
 112  *           :              CONFIG_ENV_SECT_SIZE, 16k
 113  *           :              CONFIG_SYS_MALLOC_LEN,    128k
 114  *     0x03FC 0000     RAM Copy of Monitor Code
 115  *           :              CONFIG_SYS_MONITOR_LEN,   256k
 116  *     0x03FF FFFF     [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
 117  */
 118
 119 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY | \
 120                                  CONFIG_SYS_POST_CPU)
 121
 122
 123 /*
 124  * select serial console configuration
 125  *
 126  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 127  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 128  * for SCC).
 129  *
 130  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 131  * defined elsewhere.
 132  */
 133 #define CONFIG_CONS_ON_SMC      1       /* define if console on SMC */
 134 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
 135 #undef  CONFIG_CONS_NONE                /* define if console on neither */
 136 #define CONFIG_CONS_INDEX       1       /* which SMC/SCC channel for console */
 137
 138 /*
 139  * select ethernet configuration
 140  *
 141  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 142  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 143  * for FCC)
 144  *
 145  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 146  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 147  */
 148
 149 #undef  CONFIG_ETHER_ON_SCC
 150 #define CONFIG_ETHER_ON_FCC
 151 #undef  CONFIG_ETHER_NONE               /* define if ethernet on neither */
 152
 153 #ifdef  CONFIG_ETHER_ON_SCC
 154 #define CONFIG_ETHER_INDEX      1       /* which SCC/FCC channel for ethernet */
 155 #endif  /* CONFIG_ETHER_ON_SCC */
 156
 157 #ifdef  CONFIG_ETHER_ON_FCC
 158 #define CONFIG_ETHER_INDEX      2       /* which SCC/FCC channel for ethernet */
 159 #undef  CONFIG_ETHER_LOOPBACK_TEST      /* Ethernet external loopback test */
 160 #define CONFIG_MII                      /* MII PHY management           */
 161 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
 162 /*
 163  * Port pins used for bit-banged MII communictions (if applicable).
 164  */
 165
 166 #define MDIO_PORT       2               /* Port A=0, B=1, C=2, D=3 */
 167 #define MDIO_DECLARE    volatile ioport_t *iop = ioport_addr ( \
 168                                 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 169 #define MDC_DECLARE     MDIO_DECLARE
 170
 171 #define MDIO_ACTIVE     (iop->pdir |=  0x40000000)
 172 #define MDIO_TRISTATE   (iop->pdir &= ~0x40000000)
 173 #define MDIO_READ       ((iop->pdat &  0x40000000) != 0)
 174
 175 #define MDIO(bit)       if(bit) iop->pdat |=  0x40000000; \
 176                         else    iop->pdat &= ~0x40000000
 177
 178 #define MDC(bit)        if(bit) iop->pdat |=  0x80000000; \
 179                         else    iop->pdat &= ~0x80000000
 180
 181 #define MIIDELAY        udelay(50)
 182 #endif  /* CONFIG_ETHER_ON_FCC */
 183
 184 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
 185
 186 /*
 187  *  - RX clk is CLK11
 188  *  - TX clk is CLK12
 189  */
 190 # define CONFIG_SYS_CMXSCR_VALUE1       (CMXSCR_RS1CS_CLK11  | CMXSCR_TS1CS_CLK12)
 191
 192 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 193
 194 /*
 195  * - Rx-CLK is CLK13
 196  * - Tx-CLK is CLK14
 197  * - Select bus for bd/buffers (see 28-13)
 198  * - Enable Full Duplex in FSMR
 199  */
 200 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 201 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 202 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
 203 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
 204
 205 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 206
 207 #define CONFIG_SHOW_BOOT_PROGRESS 1     /* boot progress enabled        */
 208
 209 /*
 210  * Configure for RAM tests.
 211  */
 212 #undef  CONFIG_SYS_DRAM_TEST                    /* calls other tests in board.c */
 213
 214
 215 /*
 216  * Status LED for power up status feedback.
 217  */
 218 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
 219
 220 #define STATUS_LED_PAR          im_ioport.iop_ppara
 221 #define STATUS_LED_DIR          im_ioport.iop_pdira
 222 #define STATUS_LED_ODR          im_ioport.iop_podra
 223 #define STATUS_LED_DAT          im_ioport.iop_pdata
 224
 225 #define STATUS_LED_BIT          0x00000800      /* LED 0 is on PA.20    */
 226 #define STATUS_LED_PERIOD       (CONFIG_SYS_HZ)
 227 #define STATUS_LED_STATE        STATUS_LED_OFF
 228 #define STATUS_LED_BIT1         0x00001000      /* LED 1 is on PA.19    */
 229 #define STATUS_LED_PERIOD1      (CONFIG_SYS_HZ)
 230 #define STATUS_LED_STATE1       STATUS_LED_OFF
 231 #define STATUS_LED_BIT2         0x00002000      /* LED 2 is on PA.18    */
 232 #define STATUS_LED_PERIOD2      (CONFIG_SYS_HZ/2)
 233 #define STATUS_LED_STATE2       STATUS_LED_ON
 234
 235 #define STATUS_LED_ACTIVE       0               /* LED on for bit == 0  */
 236
 237 #define STATUS_LED_YELLOW       0
 238 #define STATUS_LED_GREEN        1
 239 #define STATUS_LED_RED          2
 240 #define STATUS_LED_BOOT         1
 241
 242
 243 /*
 244  * Select SPI support configuration
 245  */
 246 #define CONFIG_SOFT_SPI         /* Enable SPI driver */
 247 #define MAX_SPI_BYTES   4       /* Maximum number of bytes we can handle */
 248 #undef  DEBUG_SPI               /* Disable SPI debugging */
 249
 250 /*
 251  * Software (bit-bang) SPI driver configuration
 252  */
 253 #ifdef CONFIG_SOFT_SPI
 254
 255 /*
 256  * Software (bit-bang) SPI driver configuration
 257  */
 258 #define I2C_SCLK        0x00002000      /* PD 18: Shift clock */
 259 #define I2C_MOSI        0x00004000      /* PD 17: Master Out, Slave In */
 260 #define I2C_MISO        0x00008000      /* PD 16: Master In, Slave Out */
 261
 262 #undef  SPI_INIT                        /* no port initialization needed */
 263 #define SPI_READ        ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
 264 #define SPI_SDA(bit)    do {                                            \
 265                         if(bit) immr->im_ioport.iop_pdatd |=  I2C_MOSI; \
 266                         else    immr->im_ioport.iop_pdatd &= ~I2C_MOSI; \
 267                         } while (0)
 268 #define SPI_SCL(bit)    do {                                            \
 269                         if(bit) immr->im_ioport.iop_pdatd |=  I2C_SCLK; \
 270                         else    immr->im_ioport.iop_pdatd &= ~I2C_SCLK; \
 271                         } while (0)
 272 #define SPI_DELAY                       /* No delay is needed */
 273 #endif /* CONFIG_SOFT_SPI */
 274
 275
 276 /*
 277  * select I2C support configuration
 278  *
 279  * Supported configurations are {none, software, hardware} drivers.
 280  * If the software driver is chosen, there are some additional
 281  * configuration items that the driver uses to drive the port pins.
 282  */
 283 #define CONFIG_SYS_I2C
 284 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
 285 #define CONFIG_SYS_I2C_SOFT_SPEED       400000
 286 #define CONFIG_SYS_I2C_SOFT_SLAVE       0x7F
 287 /*
 288  * Software (bit-bang) I2C driver configuration
 289  */
 290 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 291 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 292 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 293 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 294 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 295                         else    iop->pdat &= ~0x00010000
 296 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 297                         else    iop->pdat &= ~0x00020000
 298 #define I2C_DELAY       udelay(20)      /* 1/4 I2C clock duration */
 299
 300 /* Define this to reserve an entire FLASH sector for
 301  * environment variables. Otherwise, the environment will be
 302  * put in the same sector as U-Boot, and changing variables
 303  * will erase U-Boot temporarily
 304  */
 305 #define CONFIG_ENV_IN_OWN_SECT  1
 306
 307 /* Define this to contain any number of null terminated strings that
 308  * will be part of the default environment compiled into the boot image.
 309  */
 310 #define CONFIG_EXTRA_ENV_SETTINGS \
 311 "quiet=0\0" \
 312 "serverip=192.168.123.205\0" \
 313 "ipaddr=192.168.123.203\0" \
 314 "checkhostname=VR8500\0" \
 315 "reprog="\
 316     "bootp; " \
 317     "tftpboot 0x140000 /bdi2000/u-boot.bin; " \
 318     "protect off 60000000 6003FFFF; " \
 319     "erase 60000000 6003FFFF; " \
 320     "cp.b 140000 60000000 ${filesize}; " \
 321     "protect on 60000000 6003FFFF\0" \
 322 "copyenv="\
 323     "protect off 60040000 6004FFFF; " \
 324     "erase 60040000 6004FFFF; " \
 325     "cp.b 40040000 60040000 10000; " \
 326     "protect on 60040000 6004FFFF\0" \
 327 "copyprog="\
 328     "protect off 60000000 6003FFFF; " \
 329     "erase 60000000 6003FFFF; " \
 330     "cp.b 40000000 60000000 40000; " \
 331     "protect on 60000000 6003FFFF\0" \
 332 "zapenv="\
 333     "protect off 40040000 4004FFFF; " \
 334     "erase 40040000 4004FFFF; " \
 335     "protect on 40040000 4004FFFF\0" \
 336 "zapotherenv="\
 337     "protect off 60040000 6004FFFF; " \
 338     "erase 60040000 6004FFFF; " \
 339     "protect on 60040000 6004FFFF\0" \
 340 "root-on-initrd="\
 341     "setenv bootcmd "\
 342     "version\\;" \
 343     "echo\\;" \
 344     "bootp\\;" \
 345     "setenv bootargs root=/dev/ram0 rw quiet " \
 346     "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
 347     "run boot-hook\\;" \
 348     "bootm\0" \
 349 "root-on-initrd-debug="\
 350     "setenv bootcmd "\
 351     "version\\;" \
 352     "echo\\;" \
 353     "bootp\\;" \
 354     "setenv bootargs root=/dev/ram0 rw debug " \
 355     "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
 356     "run debug-hook\\;" \
 357     "run boot-hook\\;" \
 358     "bootm\0" \
 359 "root-on-nfs="\
 360     "setenv bootcmd "\
 361     "version\\;" \
 362     "echo\\;" \
 363     "bootp\\;" \
 364     "setenv bootargs root=/dev/nfs rw quiet " \
 365     "nfsroot=\\${serverip}:\\${rootpath} " \
 366     "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
 367     "run boot-hook\\;" \
 368     "bootm\0" \
 369 "root-on-nfs-debug="\
 370     "setenv bootcmd "\
 371     "version\\;" \
 372     "echo\\;" \
 373     "bootp\\;" \
 374     "setenv bootargs root=/dev/nfs rw debug " \
 375     "nfsroot=\\${serverip}:\\${rootpath} " \
 376     "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
 377     "run debug-hook\\;" \
 378     "run boot-hook\\;" \
 379     "bootm\0" \
 380 "debug-checkout="\
 381     "setenv checkhostname;" \
 382     "setenv ethaddr 00:09:70:00:00:01;" \
 383     "bootp;" \
 384     "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \
 385     "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
 386     "run debug-hook;" \
 387     "run boot-hook;" \
 388     "bootm\0" \
 389 "debug-hook="\
 390     "echo ipaddr    ${ipaddr};" \
 391     "echo serverip  ${serverip};" \
 392     "echo gatewayip ${gatewayip};" \
 393     "echo netmask   ${netmask};" \
 394     "echo hostname  ${hostname}\0" \
 395 "ana=run adc ; run dac\0" \
 396 "adc=run adc-12 ; run adc-34\0" \
 397 "adc-12=echo ### ADC-12 ; i2c md e 81 e\0" \
 398 "adc-34=echo ### ADC-34 ; i2c md f 81 e\0" \
 399 "dac=echo ### DAC ; i2c md 11 81 5\0" \
 400 "boot-hook=echo\0"
 401
 402 /* What should the console's baud rate be? */
 403 #define CONFIG_BAUDRATE         9600
 404
 405 /* Ethernet MAC address */
 406 #define CONFIG_ETHADDR          00:09:70:00:00:00
 407
 408 /* The default Ethernet MAC address can be overwritten just once  */
 409 #ifdef  CONFIG_ETHADDR
 410 #define CONFIG_OVERWRITE_ETHADDR_ONCE 1
 411 #endif
 412
 413 /*
 414  * Define this to do some miscellaneous board-specific initialization.
 415  */
 416 #define CONFIG_MISC_INIT_R
 417
 418 /* Set to a positive value to delay for running BOOTCOMMAND */
 419 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 second */
 420
 421 /* Be selective on what keys can delay or stop the autoboot process
 422  *     To stop  use: " "
 423  */
 424 #define CONFIG_AUTOBOOT_KEYED
 425 #define CONFIG_AUTOBOOT_PROMPT  "Autobooting...\n"
 426 #define CONFIG_AUTOBOOT_STOP_STR        " "
 427 #undef  CONFIG_AUTOBOOT_DELAY_STR
 428 #define CONFIG_ZERO_BOOTDELAY_CHECK
 429 #define DEBUG_BOOTKEYS          0
 430
 431 /* Define a command string that is automatically executed when no character
 432  * is read on the console interface withing "Boot Delay" after reset.
 433  */
 434 #undef  CONFIG_BOOT_ROOT_INITRD         /* Use ram disk for the root file system */
 435 #define CONFIG_BOOT_ROOT_NFS            /* Use a NFS mounted root file system */
 436
 437 #ifdef CONFIG_BOOT_ROOT_INITRD
 438 #define CONFIG_BOOTCOMMAND \
 439         "version;" \
 440         "echo;" \
 441         "bootp;" \
 442         "setenv bootargs root=/dev/ram0 rw quiet " \
 443         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
 444         "run boot-hook;" \
 445         "bootm"
 446 #endif /* CONFIG_BOOT_ROOT_INITRD */
 447
 448 #ifdef CONFIG_BOOT_ROOT_NFS
 449 #define CONFIG_BOOTCOMMAND \
 450         "version;" \
 451         "echo;" \
 452         "bootp;" \
 453         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \
 454         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
 455         "run boot-hook;" \
 456         "bootm"
 457 #endif /* CONFIG_BOOT_ROOT_NFS */
 458
 459 #define CONFIG_BOOTP_RANDOM_DELAY       /* Randomize the BOOTP retry delay */
 460
 461 /*
 462  * BOOTP options
 463  */
 464 #define CONFIG_BOOTP_SUBNETMASK
 465 #define CONFIG_BOOTP_GATEWAY
 466 #define CONFIG_BOOTP_HOSTNAME
 467 #define CONFIG_BOOTP_BOOTPATH
 468 #define CONFIG_BOOTP_BOOTFILESIZE
 469 #define  CONFIG_BOOTP_DNS
 470 #define  CONFIG_BOOTP_DNS2
 471 #define  CONFIG_BOOTP_SEND_HOSTNAME
 472
 473
 474 /* undef this to save memory */
 475 #define CONFIG_SYS_LONGHELP
 476
 477 /* Monitor Command Prompt */
 478 #define CONFIG_SYS_PROMPT               "=> "
 479
 480 #undef  CONFIG_SYS_HUSH_PARSER
 481 #ifdef  CONFIG_SYS_HUSH_PARSER
 482 #endif
 483
 484 /* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
 485  * of an image is printed by image commands like bootm or iminfo.
 486  */
 487 #define CONFIG_TIMESTAMP
 488
 489 /* If this variable is defined, an environment variable named "ver"
 490  * is created by U-Boot showing the U-Boot version.
 491  */
 492 #define CONFIG_VERSION_VARIABLE
 493
 494
 495 /*
 496  * Command line configuration.
 497  */
 498 #include <config_cmd_default.h>
 499
 500 #define CONFIG_CMD_ELF
 501 #define CONFIG_CMD_ASKENV
 502 #define CONFIG_CMD_I2C
 503 #define CONFIG_CMD_SPI
 504 #define CONFIG_CMD_SDRAM
 505 #define CONFIG_CMD_REGINFO
 506 #define CONFIG_CMD_IMMAP
 507 #define CONFIG_CMD_IRQ
 508 #define CONFIG_CMD_PING
 509
 510 #undef CONFIG_CMD_KGDB
 511
 512 #ifdef CONFIG_ETHER_ON_FCC
 513 #define CONFIG_CMD_MII
 514 #endif
 515
 516
 517 /* Where do the internal registers live? */
 518 #define CONFIG_SYS_IMMR         0xF0000000
 519
 520 #undef  CONFIG_WATCHDOG                 /* disable the watchdog */
 521
 522 /*****************************************************************************
 523  *
 524  * You should not have to modify any of the following settings
 525  *
 526  *****************************************************************************/
 527
 528 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
 529 #define CONFIG_SACSng           1       /* munged for the SACSng */
 530 #define CONFIG_CPM2             1       /* Has a CPM2 */
 531
 532 /*
 533  * Miscellaneous configurable options
 534  */
 535 #define CONFIG_SYS_BOOTM_HEADER_QUIET 1        /* Suppress the image header dump    */
 536                                         /* in the bootm command.             */
 537 #define CONFIG_SYS_BOOTM_PROGESS_QUIET 1       /* Suppress the progress displays,   */
 538                                         /* "## <message>" from the bootm cmd */
 539 #define CONFIG_SYS_BOOTP_CHECK_HOSTNAME 1      /* If checkhostname environment is   */
 540                                         /* defined, then the hostname param  */
 541                                         /* validated against checkhostname.  */
 542 #define CONFIG_SYS_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up   */
 543 #define CONFIG_SYS_BOOTP_SHORT_RANDOM_DELAY 1  /* Use a short random delay value    */
 544                                         /* (limited to maximum of 1024 msec) */
 545 #define CONFIG_SYS_CHK_FOR_ABORT_AT_LEAST_ONCE 1
 546                                         /* Check for abort key presses       */
 547                                         /* at least once in dependent of the */
 548                                         /* CONFIG_BOOTDELAY value.           */
 549 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1        /* Don't print console @ startup     */
 550 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1      /* Echo the inverted Ethernet link   */
 551                                         /* state to the fault LED.           */
 552 #define CONFIG_SYS_FAULT_MII_ADDR 0x02         /* MII addr of the PHY to check for  */
 553                                         /* the Ethernet link state.          */
 554 #define CONFIG_SYS_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing  */
 555                                         /* until the TFTP is successful.     */
 556 #define CONFIG_SYS_STATUS_OFF_AFTER_NETBOOT 1  /* After a successful netboot,       */
 557                                         /* turn off the STATUS LEDs.         */
 558 #define CONFIG_SYS_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on      */
 559                                         /* incoming data.                    */
 560 #define CONFIG_SYS_TFTP_BLOCKS_PER_HASH 100    /* For every XX blocks, output a '#' */
 561                                         /* to signify that tftp is moving.   */
 562 #define CONFIG_SYS_TFTP_HASHES_PER_FLASH 200   /* For every '#' hashes,             */
 563                                         /* flash the status LED.             */
 564 #define CONFIG_SYS_TFTP_HASHES_PER_LINE 65     /* Only output XX '#'s per line      */
 565                                         /* during the tftp file transfer.    */
 566 #define CONFIG_SYS_TFTP_PROGESS_QUIET 1        /* Suppress the progress displays    */
 567                                         /* '#'s from the tftp command.       */
 568 #define CONFIG_SYS_TFTP_STATUS_QUIET 1         /* Suppress the status displays      */
 569                                         /* issued during the tftp command.   */
 570 #define CONFIG_SYS_TFTP_TIMEOUT_COUNT 5        /* How many timeouts TFTP will allow */
 571                                         /* before it gives up.               */
 572
 573 #if defined(CONFIG_CMD_KGDB)
 574 #  define CONFIG_SYS_CBSIZE             1024    /* Console I/O Buffer Size           */
 575 #else
 576 #  define CONFIG_SYS_CBSIZE             256     /* Console I/O Buffer Size           */
 577 #endif
 578
 579 /* Print Buffer Size */
 580 #define CONFIG_SYS_PBSIZE         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
 581
 582 #define CONFIG_SYS_MAXARGS              32      /* max number of command args   */
 583
 584 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size     */
 585
 586 #define CONFIG_SYS_LOAD_ADDR            0x400000   /* default load address */
 587 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 588
 589 #define CONFIG_SYS_ALT_MEMTEST                 /* Select full-featured memory test */
 590 #define CONFIG_SYS_MEMTEST_START        0x2000  /* memtest works from the end of */
 591                                         /* the exception vector table */
 592                                         /* to the end of the DRAM  */
 593                                         /* less monitor and malloc area */
 594 #define CONFIG_SYS_STACK_USAGE          0x10000 /* Reserve 64k for the stack usage */
 595 #define CONFIG_SYS_MEM_END_USAGE        ( CONFIG_SYS_MONITOR_LEN \
 596                                 + CONFIG_SYS_MALLOC_LEN \
 597                                 + CONFIG_ENV_SECT_SIZE \
 598                                 + CONFIG_SYS_STACK_USAGE )
 599
 600 #define CONFIG_SYS_MEMTEST_END          ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
 601                                 - CONFIG_SYS_MEM_END_USAGE )
 602
 603 /*
 604  * Low Level Configuration Settings
 605  * (address mappings, register initial values, etc.)
 606  * You should know what you are doing if you make changes here.
 607  */
 608
 609 #define CONFIG_SYS_FLASH_BASE   CONFIG_SYS_FLASH0_BASE
 610 #define CONFIG_SYS_FLASH_SIZE   CONFIG_SYS_FLASH0_SIZE
 611 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_SDRAM0_BASE
 612 #define CONFIG_SYS_SDRAM_SIZE   CONFIG_SYS_SDRAM0_SIZE
 613
 614 /*-----------------------------------------------------------------------
 615  * Hard Reset Configuration Words
 616  */
 617 #if defined(CONFIG_SYS_SBC_BOOT_LOW)
 618 #  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 619 #else
 620 #  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (0)
 621 #endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
 622
 623 /* get the HRCW ISB field from CONFIG_SYS_IMMR */
 624 #define CONFIG_SYS_SBC_HRCW_IMMR        ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
 625                                   ((CONFIG_SYS_IMMR & 0x01000000) >>  7) | \
 626                                   ((CONFIG_SYS_IMMR & 0x00100000) >>  4) )
 627
 628 #define CONFIG_SYS_HRCW_MASTER          ( HRCW_BPS10                            | \
 629                                   HRCW_DPPC11                           | \
 630                                   CONFIG_SYS_SBC_HRCW_IMMR                      | \
 631                                   HRCW_MMR00                            | \
 632                                   HRCW_LBPC11                           | \
 633                                   HRCW_APPC10                           | \
 634                                   HRCW_CS10PC00                         | \
 635                                   (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111)   | \
 636                                   CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
 637
 638 /* no slaves */
 639 #define CONFIG_SYS_HRCW_SLAVE1          0
 640 #define CONFIG_SYS_HRCW_SLAVE2          0
 641 #define CONFIG_SYS_HRCW_SLAVE3          0
 642 #define CONFIG_SYS_HRCW_SLAVE4          0
 643 #define CONFIG_SYS_HRCW_SLAVE5          0
 644 #define CONFIG_SYS_HRCW_SLAVE6          0
 645 #define CONFIG_SYS_HRCW_SLAVE7          0
 646
 647 /*-----------------------------------------------------------------------
 648  * Definitions for initial stack pointer and data area (in DPRAM)
 649  */
 650 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 651 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM   */
 652 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 653 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 654
 655 /*-----------------------------------------------------------------------
 656  * Start addresses for the final memory configuration
 657  * (Set up by the startup code)
 658  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 659  * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
 660  */
 661 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
 662
 663 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 664 #  define CONFIG_SYS_RAMBOOT
 665 #endif
 666
 667 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 668 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 669
 670 /*
 671  * For booting Linux, the board info and command line data
 672  * have to be in the first 8 MB of memory, since this is
 673  * the maximum mapped by the Linux kernel during initialization.
 674  */
 675 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 676
 677 /*-----------------------------------------------------------------------
 678  * FLASH and environment organization
 679  */
 680
 681 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant              */
 682 #undef  CONFIG_SYS_FLASH_PROTECTION             /* use hardware protection              */
 683 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 684 #define CONFIG_SYS_MAX_FLASH_SECT       (64+4)  /* max number of sectors on one chip    */
 685
 686 #define CONFIG_SYS_FLASH_ERASE_TOUT     8000    /* Timeout for Flash Erase (in ms)      */
 687 #define CONFIG_SYS_FLASH_WRITE_TOUT     1       /* Timeout for Flash Write (in ms)      */
 688
 689 #ifndef CONFIG_SYS_RAMBOOT
 690 #  define CONFIG_ENV_IS_IN_FLASH        1
 691
 692 #  ifdef CONFIG_ENV_IN_OWN_SECT
 693 #    define CONFIG_ENV_ADDR     (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 694 #    define CONFIG_ENV_SECT_SIZE        0x10000
 695 #  else
 696 #    define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
 697 #    define CONFIG_ENV_SIZE     0x1000  /* Total Size of Environment Sector     */
 698 #    define CONFIG_ENV_SECT_SIZE        0x10000 /* see README - env sect real size      */
 699 #  endif /* CONFIG_ENV_IN_OWN_SECT */
 700
 701 #else
 702 #  define CONFIG_ENV_IS_IN_NVRAM        1
 703 #  define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 704 #  define CONFIG_ENV_SIZE               0x200
 705 #endif /* CONFIG_SYS_RAMBOOT */
 706
 707 /*-----------------------------------------------------------------------
 708  * Cache Configuration
 709  */
 710 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPU */
 711
 712 #if defined(CONFIG_CMD_KGDB)
 713 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 714 #endif
 715
 716 /*-----------------------------------------------------------------------
 717  * HIDx - Hardware Implementation-dependent Registers                    2-11
 718  *-----------------------------------------------------------------------
 719  * HID0 also contains cache control - initially enable both caches and
 720  * invalidate contents, then the final state leaves only the instruction
 721  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 722  * but Soft reset does not.
 723  *
 724  * HID1 has only read-only information - nothing to set.
 725  */
 726 #define CONFIG_SYS_HID0_INIT    (HID0_ICE  |\
 727                          HID0_DCE  |\
 728                          HID0_ICFI |\
 729                          HID0_DCI  |\
 730                          HID0_IFEM |\
 731                          HID0_ABE)
 732
 733 #define CONFIG_SYS_HID0_FINAL   (HID0_ICE  |\
 734                          HID0_IFEM |\
 735                          HID0_ABE  |\
 736                          HID0_EMCP)
 737 #define CONFIG_SYS_HID2 0
 738
 739 /*-----------------------------------------------------------------------
 740  * RMR - Reset Mode Register
 741  *-----------------------------------------------------------------------
 742  */
 743 #define CONFIG_SYS_RMR          0
 744
 745 /*-----------------------------------------------------------------------
 746  * BCR - Bus Configuration                                       4-25
 747  *-----------------------------------------------------------------------
 748  */
 749 #define CONFIG_SYS_BCR          (BCR_ETM)
 750
 751 /*-----------------------------------------------------------------------
 752  * SIUMCR - SIU Module Configuration                             4-31
 753  *-----------------------------------------------------------------------
 754  */
 755
 756 #define CONFIG_SYS_SIUMCR       (SIUMCR_DPPC11  |\
 757                          SIUMCR_L2CPC00 |\
 758                          SIUMCR_APPC10  |\
 759                          SIUMCR_MMR00)
 760
 761
 762 /*-----------------------------------------------------------------------
 763  * SYPCR - System Protection Control                            11-9
 764  * SYPCR can only be written once after reset!
 765  *-----------------------------------------------------------------------
 766  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 767  */
 768 #if defined(CONFIG_WATCHDOG)
 769 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC |\
 770                          SYPCR_BMT  |\
 771                          SYPCR_PBME |\
 772                          SYPCR_LBME |\
 773                          SYPCR_SWRI |\
 774                          SYPCR_SWP  |\
 775                          SYPCR_SWE)
 776 #else
 777 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC |\
 778                          SYPCR_BMT  |\
 779                          SYPCR_PBME |\
 780                          SYPCR_LBME |\
 781                          SYPCR_SWRI |\
 782                          SYPCR_SWP)
 783 #endif /* CONFIG_WATCHDOG */
 784
 785 /*-----------------------------------------------------------------------
 786  * TMCNTSC - Time Counter Status and Control                     4-40
 787  *-----------------------------------------------------------------------
 788  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 789  * and enable Time Counter
 790  */
 791 #define CONFIG_SYS_TMCNTSC      (TMCNTSC_SEC |\
 792                          TMCNTSC_ALR |\
 793                          TMCNTSC_TCF |\
 794                          TMCNTSC_TCE)
 795
 796 /*-----------------------------------------------------------------------
 797  * PISCR - Periodic Interrupt Status and Control                 4-42
 798  *-----------------------------------------------------------------------
 799  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 800  * Periodic timer
 801  */
 802 #define CONFIG_SYS_PISCR        (PISCR_PS  |\
 803                          PISCR_PTF |\
 804                          PISCR_PTE)
 805
 806 /*-----------------------------------------------------------------------
 807  * SCCR - System Clock Control                                   9-8
 808  *-----------------------------------------------------------------------
 809  */
 810 #define CONFIG_SYS_SCCR 0
 811
 812 /*-----------------------------------------------------------------------
 813  * RCCR - RISC Controller Configuration                         13-7
 814  *-----------------------------------------------------------------------
 815  */
 816 #define CONFIG_SYS_RCCR 0
 817
 818 /*
 819  * Initialize Memory Controller:
 820  *
 821  * Bank Bus     Machine PortSz  Device
 822  * ---- ---     ------- ------  ------
 823  *  0   60x     GPCM    16 bit  FLASH (primary flash - 2MB)
 824  *  1   60x     GPCM    -- bit  (Unused)
 825  *  2   60x     SDRAM   64 bit  SDRAM (DIMM)
 826  *  3   60x     SDRAM   64 bit  SDRAM (DIMM)
 827  *  4   60x     GPCM    -- bit  (Unused)
 828  *  5   60x     GPCM    -- bit  (Unused)
 829  *  6   60x     GPCM    16 bit  FLASH  (secondary flash - 2MB)
 830  */
 831
 832 /*-----------------------------------------------------------------------
 833  * BR0,BR1 - Base Register
 834  *     Ref: Section 10.3.1 on page 10-14
 835  * OR0,OR1 - Option Register
 836  *     Ref: Section 10.3.2 on page 10-18
 837  *-----------------------------------------------------------------------
 838  */
 839
 840 /* Bank 0 - Primary FLASH
 841  */
 842
 843 /* BR0 is configured as follows:
 844  *
 845  *     - Base address of 0x40000000
 846  *     - 16 bit port size
 847  *     - Data errors checking is disabled
 848  *     - Read and write access
 849  *     - GPCM 60x bus
 850  *     - Access are handled by the memory controller according to MSEL
 851  *     - Not used for atomic operations
 852  *     - No data pipelining is done
 853  *     - Valid
 854  */
 855 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
 856                          BRx_PS_16                      |\
 857                          BRx_MS_GPCM_P                  |\
 858                          BRx_V)
 859
 860 /* OR0 is configured as follows:
 861  *
 862  *     - 4 MB
 863  *     - *BCTL0 is asserted upon access to the current memory bank
 864  *     - *CW / *WE are negated a quarter of a clock earlier
 865  *     - *CS is output at the same time as the address lines
 866  *     - Uses a clock cycle length of 5
 867  *     - *PSDVAL is generated internally by the memory controller
 868  *       unless *GTA is asserted earlier externally.
 869  *     - Relaxed timing is generated by the GPCM for accesses
 870  *       initiated to this memory region.
 871  *     - One idle clock is inserted between a read access from the
 872  *       current bank and the next access.
 873  */
 874 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE)      |\
 875                          ORxG_CSNT                      |\
 876                          ORxG_ACS_DIV1                  |\
 877                          ORxG_SCY_5_CLK                 |\
 878                          ORxG_TRLX                      |\
 879                          ORxG_EHTR)
 880
 881 /*-----------------------------------------------------------------------
 882  * BR2,BR3 - Base Register
 883  *     Ref: Section 10.3.1 on page 10-14
 884  * OR2,OR3 - Option Register
 885  *     Ref: Section 10.3.2 on page 10-16
 886  *-----------------------------------------------------------------------
 887  */
 888
 889 /* Bank 2,3 - SDRAM DIMM
 890  */
 891
 892 /* The BR2 is configured as follows:
 893  *
 894  *     - Base address of 0x00000000
 895  *     - 64 bit port size (60x bus only)
 896  *     - Data errors checking is disabled
 897  *     - Read and write access
 898  *     - SDRAM 60x bus
 899  *     - Access are handled by the memory controller according to MSEL
 900  *     - Not used for atomic operations
 901  *     - No data pipelining is done
 902  *     - Valid
 903  */
 904 #define CONFIG_SYS_BR2_PRELIM   ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
 905                          BRx_PS_64                      |\
 906                          BRx_MS_SDRAM_P                 |\
 907                          BRx_V)
 908
 909 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
 910                          BRx_PS_64                      |\
 911                          BRx_MS_SDRAM_P                 |\
 912                          BRx_V)
 913
 914 /* With a 64 MB DIMM, the OR2 is configured as follows:
 915  *
 916  *     - 64 MB
 917  *     - 4 internal banks per device
 918  *     - Row start address bit is A8 with PSDMR[PBI] = 0
 919  *     - 12 row address lines
 920  *     - Back-to-back page mode
 921  *     - Internal bank interleaving within save device enabled
 922  */
 923 #if (CONFIG_SYS_SDRAM0_SIZE == 64)
 924 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE)      |\
 925                          ORxS_BPD_4                     |\
 926                          ORxS_ROWST_PBI0_A8             |\
 927                          ORxS_NUMR_12)
 928 #else
 929 #error "INVALID SDRAM CONFIGURATION"
 930 #endif
 931
 932 /*-----------------------------------------------------------------------
 933  * PSDMR - 60x Bus SDRAM Mode Register
 934  *     Ref: Section 10.3.3 on page 10-21
 935  *-----------------------------------------------------------------------
 936  */
 937
 938 /* Address that the DIMM SPD memory lives at.
 939  */
 940 #define SDRAM_SPD_ADDR 0x50
 941
 942 #if (CONFIG_SYS_SDRAM0_SIZE == 64)
 943 /* With a 64 MB DIMM, the PSDMR is configured as follows:
 944  *
 945  *     - Bank Based Interleaving,
 946  *     - Refresh Enable,
 947  *     - Address Multiplexing where A5 is output on A14 pin
 948  *       (A6 on A15, and so on),
 949  *     - use address pins A14-A16 as bank select,
 950  *     - A9 is output on SDA10 during an ACTIVATE command,
 951  *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
 952  *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
 953  *       is 3 clocks,
 954  *     - earliest timing for READ/WRITE command after ACTIVATE command is
 955  *       2 clocks,
 956  *     - earliest timing for PRECHARGE after last data was read is 1 clock,
 957  *     - earliest timing for PRECHARGE after last data was written is 1 clock,
 958  *     - CAS Latency is 2.
 959  */
 960 #define CONFIG_SYS_PSDMR        (PSDMR_RFEN           |\
 961                          PSDMR_SDAM_A14_IS_A5 |\
 962                          PSDMR_BSMA_A14_A16   |\
 963                          PSDMR_SDA10_PBI0_A9  |\
 964                          PSDMR_RFRC_7_CLK     |\
 965                          PSDMR_PRETOACT_3W    |\
 966                          PSDMR_ACTTORW_2W     |\
 967                          PSDMR_LDOTOPRE_1C    |\
 968                          PSDMR_WRC_1C         |\
 969                          PSDMR_CL_2)
 970 #else
 971 #error "INVALID SDRAM CONFIGURATION"
 972 #endif
 973
 974 /*
 975  * Shoot for approximately 1MHz on the prescaler.
 976  */
 977 #if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000))
 978 #define CONFIG_SYS_MPTPR        MPTPR_PTP_DIV64
 979 #elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000))
 980 #define CONFIG_SYS_MPTPR        MPTPR_PTP_DIV32
 981 #else
 982 #warning "Unconfigured bus clock freq: check CONFIG_SYS_MPTPR and CONFIG_SYS_PSRT are OK"
 983 #define CONFIG_SYS_MPTPR        MPTPR_PTP_DIV32
 984 #endif
 985 #define CONFIG_SYS_PSRT 14
 986
 987
 988 /*-----------------------------------------------------------------------
 989  * BR6 - Base Register
 990  *     Ref: Section 10.3.1 on page 10-14
 991  * OR6 - Option Register
 992  *     Ref: Section 10.3.2 on page 10-18
 993  *-----------------------------------------------------------------------
 994  */
 995
 996 /* Bank 6 - Secondary FLASH
 997  *
 998  * The secondary FLASH is connected to *CS6
 999  */
1000 #if (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE))
1001
1002 /* BR6 is configured as follows:
1003  *
1004  *     - Base address of 0x60000000
1005  *     - 16 bit port size
1006  *     - Data errors checking is disabled
1007  *     - Read and write access
1008  *     - GPCM 60x bus
1009  *     - Access are handled by the memory controller according to MSEL
1010  *     - Not used for atomic operations
1011  *     - No data pipelining is done
1012  *     - Valid
1013  */
1014 #  define CONFIG_SYS_BR6_PRELIM  ((CONFIG_SYS_FLASH1_BASE & BRx_BA_MSK) |\
1015                            BRx_PS_16                      |\
1016                            BRx_MS_GPCM_P                  |\
1017                            BRx_V)
1018
1019 /* OR6 is configured as follows:
1020  *
1021  *     - 2 MB
1022  *     - *BCTL0 is asserted upon access to the current memory bank
1023  *     - *CW / *WE are negated a quarter of a clock earlier
1024  *     - *CS is output at the same time as the address lines
1025  *     - Uses a clock cycle length of 5
1026  *     - *PSDVAL is generated internally by the memory controller
1027  *       unless *GTA is asserted earlier externally.
1028  *     - Relaxed timing is generated by the GPCM for accesses
1029  *       initiated to this memory region.
1030  *     - One idle clock is inserted between a read access from the
1031  *       current bank and the next access.
1032  */
1033 #  define CONFIG_SYS_OR6_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH1_SIZE)  |\
1034                            ORxG_CSNT                   |\
1035                            ORxG_ACS_DIV1               |\
1036                            ORxG_SCY_5_CLK              |\
1037                            ORxG_TRLX                   |\
1038                            ORxG_EHTR)
1039 #endif /* (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) */
1040
1041 #endif  /* __CONFIG_H */