include/configs/sacsng.h

   1 /*
   2  * (C) Copyright 2000
   3  * Murray Jensen <Murray.Jensen@cmst.csiro.au>
   4  *
   5  * (C) Copyright 2000
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * (C) Copyright 2001
  10  * Advent Networks, Inc. <http://www.adventnetworks.com>
  11  * Jay Monkman <jtm@smoothsmoothie.com>
  12  *
  13  * Configuration settings for the SACSng 8260 board.
  14  *
  15  * SPDX-License-Identifier:     GPL-2.0+
  16  */
  17
  18 #ifndef __CONFIG_H
  19 #define __CONFIG_H
  20
  21 #define CONFIG_SYS_TEXT_BASE    0x40000000
  22
  23 #undef DEBUG_BOOTP_EXT        /* Debug received vendor fields */
  24
  25 #undef CONFIG_LOGBUFFER       /* External logbuffer support */
  26
  27 /*****************************************************************************
  28  *
  29  * These settings must match the way _your_ board is set up
  30  *
  31  *****************************************************************************/
  32
  33 /* What is the oscillator's (UX2) frequency in Hz? */
  34 #define CONFIG_8260_CLKIN  66666600
  35
  36 /*-----------------------------------------------------------------------
  37  * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
  38  *-----------------------------------------------------------------------
  39  * What should MODCK_H be? It is dependent on the oscillator
  40  * frequency, MODCK[1-3], and desired CPM and core frequencies.
  41  * Here are some example values (all frequencies are in MHz):
  42  *
  43  * MODCK_H   MODCK[1-3]  Osc    CPM    Core  S2-6   S2-7   S2-8
  44  * -------   ----------  ---    ---    ----  -----  -----  -----
  45  * 0x1       0x5         33     100    133   Open   Close  Open
  46  * 0x1       0x6         33     100    166   Open   Open   Close
  47  * 0x1       0x7         33     100    200   Open   Open   Open
  48  *
  49  * 0x2       0x2         33     133    133   Close  Open   Close
  50  * 0x2       0x3         33     133    166   Close  Open   Open
  51  * 0x2       0x4         33     133    200   Open   Close  Close
  52  * 0x2       0x5         33     133    233   Open   Close  Open
  53  * 0x2       0x6         33     133    266   Open   Open   Close
  54  *
  55  * 0x5       0x5         66     133    133   Open   Close  Open
  56  * 0x5       0x6         66     133    166   Open   Open   Close
  57  * 0x5       0x7         66     133    200   Open   Open   Open
  58  * 0x6       0x0         66     133    233   Close  Close  Close
  59  * 0x6       0x1         66     133    266   Close  Close  Open
  60  * 0x6       0x2         66     133    300   Close  Open   Close
  61  */
  62 #define CONFIG_SYS_SBC_MODCK_H 0x05
  63
  64 /* Define this if you want to boot from 0x00000100. If you don't define
  65  * this, you will need to program the bootloader to 0xfff00000, and
  66  * get the hardware reset config words at 0xfe000000. The simplest
  67  * way to do that is to program the bootloader at both addresses.
  68  * It is suggested that you just let U-Boot live at 0x00000000.
  69  */
  70 #define CONFIG_SYS_SBC_BOOT_LOW 1
  71
  72 /* What should the base address of the main FLASH be and how big is
  73  * it (in MBytes)?  This must contain CONFIG_SYS_TEXT_BASE from board/sacsng/config.mk
  74  * The main FLASH is whichever is connected to *CS0.
  75  */
  76 #define CONFIG_SYS_FLASH0_BASE 0x40000000
  77 #define CONFIG_SYS_FLASH0_SIZE 2
  78
  79 /* What should the base address of the secondary FLASH be and how big
  80  * is it (in Mbytes)?  The secondary FLASH is whichever is connected
  81  * to *CS6.
  82  */
  83 #define CONFIG_SYS_FLASH1_BASE 0x60000000
  84 #define CONFIG_SYS_FLASH1_SIZE 2
  85
  86 /* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
  87  */
  88 #define CONFIG_VERY_BIG_RAM     1
  89
  90 /* What should be the base address of SDRAM DIMM and how big is
  91  * it (in Mbytes)?  This will normally auto-configure via the SPD.
  92 */
  93 #define CONFIG_SYS_SDRAM0_BASE 0x00000000
  94 #define CONFIG_SYS_SDRAM0_SIZE 64
  95
  96 /*
  97  * Memory map example with 64 MB DIMM:
  98  *
  99  *     0x0000 0000     Exception Vector code, 8k
 100  *           :
 101  *     0x0000 1FFF
 102  *     0x0000 2000     Free for Application Use
 103  *           :
 104  *           :
 105  *
 106  *           :
 107  *           :
 108  *     0x03F5 FF30     Monitor Stack (Growing downward)
 109  *                     Monitor Stack Buffer (0x80)
 110  *     0x03F5 FFB0     Board Info Data
 111  *     0x03F6 0000     Malloc Arena
 112  *           :              CONFIG_ENV_SECT_SIZE, 16k
 113  *           :              CONFIG_SYS_MALLOC_LEN,    128k
 114  *     0x03FC 0000     RAM Copy of Monitor Code
 115  *           :              CONFIG_SYS_MONITOR_LEN,   256k
 116  *     0x03FF FFFF     [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
 117  */
 118
 119 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY | \
 120                                  CONFIG_SYS_POST_CPU)
 121
 122
 123 /*
 124  * select serial console configuration
 125  *
 126  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 127  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 128  * for SCC).
 129  *
 130  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 131  * defined elsewhere.
 132  */
 133 #define CONFIG_CONS_ON_SMC      1       /* define if console on SMC */
 134 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
 135 #undef  CONFIG_CONS_NONE                /* define if console on neither */
 136 #define CONFIG_CONS_INDEX       1       /* which SMC/SCC channel for console */
 137
 138 /*
 139  * select ethernet configuration
 140  *
 141  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 142  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 143  * for FCC)
 144  *
 145  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 146  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 147  */
 148
 149 #undef  CONFIG_ETHER_ON_SCC
 150 #define CONFIG_ETHER_ON_FCC
 151 #undef  CONFIG_ETHER_NONE               /* define if ethernet on neither */
 152
 153 #ifdef  CONFIG_ETHER_ON_SCC
 154 #define CONFIG_ETHER_INDEX      1       /* which SCC/FCC channel for ethernet */
 155 #endif  /* CONFIG_ETHER_ON_SCC */
 156
 157 #ifdef  CONFIG_ETHER_ON_FCC
 158 #define CONFIG_ETHER_INDEX      2       /* which SCC/FCC channel for ethernet */
 159 #undef  CONFIG_ETHER_LOOPBACK_TEST      /* Ethernet external loopback test */
 160 #define CONFIG_MII                      /* MII PHY management           */
 161 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
 162 /*
 163  * Port pins used for bit-banged MII communictions (if applicable).
 164  */
 165
 166 #define MDIO_PORT       2               /* Port A=0, B=1, C=2, D=3 */
 167 #define MDIO_DECLARE    volatile ioport_t *iop = ioport_addr ( \
 168                                 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 169 #define MDC_DECLARE     MDIO_DECLARE
 170
 171 #define MDIO_ACTIVE     (iop->pdir |=  0x40000000)
 172 #define MDIO_TRISTATE   (iop->pdir &= ~0x40000000)
 173 #define MDIO_READ       ((iop->pdat &  0x40000000) != 0)
 174
 175 #define MDIO(bit)       if(bit) iop->pdat |=  0x40000000; \
 176                         else    iop->pdat &= ~0x40000000
 177
 178 #define MDC(bit)        if(bit) iop->pdat |=  0x80000000; \
 179                         else    iop->pdat &= ~0x80000000
 180
 181 #define MIIDELAY        udelay(50)
 182 #endif  /* CONFIG_ETHER_ON_FCC */
 183
 184 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
 185
 186 /*
 187  *  - RX clk is CLK11
 188  *  - TX clk is CLK12
 189  */
 190 # define CONFIG_SYS_CMXSCR_VALUE1       (CMXSCR_RS1CS_CLK11  | CMXSCR_TS1CS_CLK12)
 191
 192 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 193
 194 /*
 195  * - Rx-CLK is CLK13
 196  * - Tx-CLK is CLK14
 197  * - Select bus for bd/buffers (see 28-13)
 198  * - Enable Full Duplex in FSMR
 199  */
 200 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 201 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 202 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
 203 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
 204
 205 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 206
 207 #define CONFIG_SHOW_BOOT_PROGRESS 1     /* boot progress enabled        */
 208
 209 /*
 210  * Configure for RAM tests.
 211  */
 212 #undef  CONFIG_SYS_DRAM_TEST                    /* calls other tests in board.c */
 213
 214
 215 /*
 216  * Status LED for power up status feedback.
 217  */
 218 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
 219
 220 #define STATUS_LED_PAR          im_ioport.iop_ppara
 221 #define STATUS_LED_DIR          im_ioport.iop_pdira
 222 #define STATUS_LED_ODR          im_ioport.iop_podra
 223 #define STATUS_LED_DAT          im_ioport.iop_pdata
 224
 225 #define STATUS_LED_BIT          0x00000800      /* LED 0 is on PA.20    */
 226 #define STATUS_LED_PERIOD       (CONFIG_SYS_HZ)
 227 #define STATUS_LED_STATE        STATUS_LED_OFF
 228 #define STATUS_LED_BIT1         0x00001000      /* LED 1 is on PA.19    */
 229 #define STATUS_LED_PERIOD1      (CONFIG_SYS_HZ)
 230 #define STATUS_LED_STATE1       STATUS_LED_OFF
 231 #define STATUS_LED_BIT2         0x00002000      /* LED 2 is on PA.18    */
 232 #define STATUS_LED_PERIOD2      (CONFIG_SYS_HZ/2)
 233 #define STATUS_LED_STATE2       STATUS_LED_ON
 234
 235 #define STATUS_LED_ACTIVE       0               /* LED on for bit == 0  */
 236
 237 #define STATUS_LED_YELLOW       0
 238 #define STATUS_LED_GREEN        1
 239 #define STATUS_LED_RED          2
 240 #define STATUS_LED_BOOT         1
 241
 242
 243 /*
 244  * Select SPI support configuration
 245  */
 246 #define CONFIG_SOFT_SPI         /* Enable SPI driver */
 247 #define MAX_SPI_BYTES   4       /* Maximum number of bytes we can handle */
 248 #undef  DEBUG_SPI               /* Disable SPI debugging */
 249
 250 /*
 251  * Software (bit-bang) SPI driver configuration
 252  */
 253 #ifdef CONFIG_SOFT_SPI
 254
 255 /*
 256  * Software (bit-bang) SPI driver configuration
 257  */
 258 #define I2C_SCLK        0x00002000      /* PD 18: Shift clock */
 259 #define I2C_MOSI        0x00004000      /* PD 17: Master Out, Slave In */
 260 #define I2C_MISO        0x00008000      /* PD 16: Master In, Slave Out */
 261
 262 #undef  SPI_INIT                        /* no port initialization needed */
 263 #define SPI_READ        ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
 264 #define SPI_SDA(bit)    do {                                            \
 265                         if(bit) immr->im_ioport.iop_pdatd |=  I2C_MOSI; \
 266                         else    immr->im_ioport.iop_pdatd &= ~I2C_MOSI; \
 267                         } while (0)
 268 #define SPI_SCL(bit)    do {                                            \
 269                         if(bit) immr->im_ioport.iop_pdatd |=  I2C_SCLK; \
 270                         else    immr->im_ioport.iop_pdatd &= ~I2C_SCLK; \
 271                         } while (0)
 272 #define SPI_DELAY                       /* No delay is needed */
 273 #endif /* CONFIG_SOFT_SPI */
 274
 275
 276 /*
 277  * select I2C support configuration
 278  *
 279  * Supported configurations are {none, software, hardware} drivers.
 280  * If the software driver is chosen, there are some additional
 281  * configuration items that the driver uses to drive the port pins.
 282  */
 283 #define CONFIG_SYS_I2C
 284 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
 285 #define CONFIG_SYS_I2C_SOFT_SPEED       400000
 286 #define CONFIG_SYS_I2C_SOFT_SLAVE       0x7F
 287 /*
 288  * Software (bit-bang) I2C driver configuration
 289  */
 290 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 291 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 292 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 293 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 294 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 295                         else    iop->pdat &= ~0x00010000
 296 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 297                         else    iop->pdat &= ~0x00020000
 298 #define I2C_DELAY       udelay(20)      /* 1/4 I2C clock duration */
 299
 300 /* Define this to reserve an entire FLASH sector for
 301  * environment variables. Otherwise, the environment will be
 302  * put in the same sector as U-Boot, and changing variables
 303  * will erase U-Boot temporarily
 304  */
 305 #define CONFIG_ENV_IN_OWN_SECT  1
 306
 307 /* Define this to contain any number of null terminated strings that
 308  * will be part of the default environment compiled into the boot image.
 309  */
 310 #define CONFIG_EXTRA_ENV_SETTINGS \
 311 "quiet=0\0" \
 312 "serverip=192.168.123.205\0" \
 313 "ipaddr=192.168.123.203\0" \
 314 "checkhostname=VR8500\0" \
 315 "reprog="\
 316     "bootp; " \
 317     "tftpboot 0x140000 /bdi2000/u-boot.bin; " \
 318     "protect off 60000000 6003FFFF; " \
 319     "erase 60000000 6003FFFF; " \
 320     "cp.b 140000 60000000 ${filesize}; " \
 321     "protect on 60000000 6003FFFF\0" \
 322 "copyenv="\
 323     "protect off 60040000 6004FFFF; " \
 324     "erase 60040000 6004FFFF; " \
 325     "cp.b 40040000 60040000 10000; " \
 326     "protect on 60040000 6004FFFF\0" \
 327 "copyprog="\
 328     "protect off 60000000 6003FFFF; " \
 329     "erase 60000000 6003FFFF; " \
 330     "cp.b 40000000 60000000 40000; " \
 331     "protect on 60000000 6003FFFF\0" \
 332 "zapenv="\
 333     "protect off 40040000 4004FFFF; " \
 334     "erase 40040000 4004FFFF; " \
 335     "protect on 40040000 4004FFFF\0" \
 336 "zapotherenv="\
 337     "protect off 60040000 6004FFFF; " \
 338     "erase 60040000 6004FFFF; " \
 339     "protect on 60040000 6004FFFF\0" \
 340 "root-on-initrd="\
 341     "setenv bootcmd "\
 342     "version\\;" \
 343     "echo\\;" \
 344     "bootp\\;" \
 345     "setenv bootargs root=/dev/ram0 rw quiet " \
 346     "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
 347     "run boot-hook\\;" \
 348     "bootm\0" \
 349 "root-on-initrd-debug="\
 350     "setenv bootcmd "\
 351     "version\\;" \
 352     "echo\\;" \
 353     "bootp\\;" \
 354     "setenv bootargs root=/dev/ram0 rw debug " \
 355     "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
 356     "run debug-hook\\;" \
 357     "run boot-hook\\;" \
 358     "bootm\0" \
 359 "root-on-nfs="\
 360     "setenv bootcmd "\
 361     "version\\;" \
 362     "echo\\;" \
 363     "bootp\\;" \
 364     "setenv bootargs root=/dev/nfs rw quiet " \
 365     "nfsroot=\\${serverip}:\\${rootpath} " \
 366     "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
 367     "run boot-hook\\;" \
 368     "bootm\0" \
 369 "root-on-nfs-debug="\
 370     "setenv bootcmd "\
 371     "version\\;" \
 372     "echo\\;" \
 373     "bootp\\;" \
 374     "setenv bootargs root=/dev/nfs rw debug " \
 375     "nfsroot=\\${serverip}:\\${rootpath} " \
 376     "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
 377     "run debug-hook\\;" \
 378     "run boot-hook\\;" \
 379     "bootm\0" \
 380 "debug-checkout="\
 381     "setenv checkhostname;" \
 382     "setenv ethaddr 00:09:70:00:00:01;" \
 383     "bootp;" \
 384     "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \
 385     "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
 386     "run debug-hook;" \
 387     "run boot-hook;" \
 388     "bootm\0" \
 389 "debug-hook="\
 390     "echo ipaddr    ${ipaddr};" \
 391     "echo serverip  ${serverip};" \
 392     "echo gatewayip ${gatewayip};" \
 393     "echo netmask   ${netmask};" \
 394     "echo hostname  ${hostname}\0" \
 395 "ana=run adc ; run dac\0" \
 396 "adc=run adc-12 ; run adc-34\0" \
 397 "adc-12=echo ### ADC-12 ; i2c md e 81 e\0" \
 398 "adc-34=echo ### ADC-34 ; i2c md f 81 e\0" \
 399 "dac=echo ### DAC ; i2c md 11 81 5\0" \
 400 "boot-hook=echo\0"
 401
 402 /* What should the console's baud rate be? */
 403 #define CONFIG_BAUDRATE         9600
 404
 405 /* Ethernet MAC address */
 406 #define CONFIG_ETHADDR          00:09:70:00:00:00
 407
 408 /* The default Ethernet MAC address can be overwritten just once  */
 409 #ifdef  CONFIG_ETHADDR
 410 #define CONFIG_OVERWRITE_ETHADDR_ONCE 1
 411 #endif
 412
 413 /*
 414  * Define this to do some miscellaneous board-specific initialization.
 415  */
 416 #define CONFIG_MISC_INIT_R
 417
 418 /* Set to a positive value to delay for running BOOTCOMMAND */
 419 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 second */
 420
 421 /* Be selective on what keys can delay or stop the autoboot process
 422  *     To stop  use: " "
 423  */
 424 #define CONFIG_AUTOBOOT_KEYED
 425 #define CONFIG_AUTOBOOT_PROMPT  "Autobooting...\n"
 426 #define CONFIG_AUTOBOOT_STOP_STR        " "
 427 #undef  CONFIG_AUTOBOOT_DELAY_STR
 428 #define CONFIG_ZERO_BOOTDELAY_CHECK
 429 #define DEBUG_BOOTKEYS          0
 430
 431 /* Define a command string that is automatically executed when no character
 432  * is read on the console interface withing "Boot Delay" after reset.
 433  */
 434 #undef  CONFIG_BOOT_ROOT_INITRD         /* Use ram disk for the root file system */
 435 #define CONFIG_BOOT_ROOT_NFS            /* Use a NFS mounted root file system */
 436
 437 #ifdef CONFIG_BOOT_ROOT_INITRD
 438 #define CONFIG_BOOTCOMMAND \
 439         "version;" \
 440         "echo;" \
 441         "bootp;" \
 442         "setenv bootargs root=/dev/ram0 rw quiet " \
 443         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
 444         "run boot-hook;" \
 445         "bootm"
 446 #endif /* CONFIG_BOOT_ROOT_INITRD */
 447
 448 #ifdef CONFIG_BOOT_ROOT_NFS
 449 #define CONFIG_BOOTCOMMAND \
 450         "version;" \
 451         "echo;" \
 452         "bootp;" \
 453         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \
 454         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
 455         "run boot-hook;" \
 456         "bootm"
 457 #endif /* CONFIG_BOOT_ROOT_NFS */
 458
 459 #define CONFIG_BOOTP_RANDOM_DELAY       /* Randomize the BOOTP retry delay */
 460
 461 /*
 462  * BOOTP options
 463  */
 464 #define CONFIG_BOOTP_SUBNETMASK
 465 #define CONFIG_BOOTP_GATEWAY
 466 #define CONFIG_BOOTP_HOSTNAME
 467 #define CONFIG_BOOTP_BOOTPATH
 468 #define CONFIG_BOOTP_BOOTFILESIZE
 469 #define  CONFIG_BOOTP_DNS
 470 #define  CONFIG_BOOTP_DNS2
 471 #define  CONFIG_BOOTP_SEND_HOSTNAME
 472
 473
 474 /* undef this to save memory */
 475 #define CONFIG_SYS_LONGHELP
 476
 477 /* Monitor Command Prompt */
 478
 479 #undef  CONFIG_SYS_HUSH_PARSER
 480 #ifdef  CONFIG_SYS_HUSH_PARSER
 481 #endif
 482
 483 /* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
 484  * of an image is printed by image commands like bootm or iminfo.
 485  */
 486 #define CONFIG_TIMESTAMP
 487
 488 /* If this variable is defined, an environment variable named "ver"
 489  * is created by U-Boot showing the U-Boot version.
 490  */
 491 #define CONFIG_VERSION_VARIABLE
 492
 493
 494 /*
 495  * Command line configuration.
 496  */
 497 #include <config_cmd_default.h>
 498
 499 #define CONFIG_CMD_ELF
 500 #define CONFIG_CMD_ASKENV
 501 #define CONFIG_CMD_I2C
 502 #define CONFIG_CMD_SPI
 503 #define CONFIG_CMD_SDRAM
 504 #define CONFIG_CMD_REGINFO
 505 #define CONFIG_CMD_IMMAP
 506 #define CONFIG_CMD_IRQ
 507 #define CONFIG_CMD_PING
 508
 509 #undef CONFIG_CMD_KGDB
 510
 511 #ifdef CONFIG_ETHER_ON_FCC
 512 #define CONFIG_CMD_MII
 513 #endif
 514
 515
 516 /* Where do the internal registers live? */
 517 #define CONFIG_SYS_IMMR         0xF0000000
 518
 519 #undef  CONFIG_WATCHDOG                 /* disable the watchdog */
 520
 521 /*****************************************************************************
 522  *
 523  * You should not have to modify any of the following settings
 524  *
 525  *****************************************************************************/
 526
 527 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
 528 #define CONFIG_SACSng           1       /* munged for the SACSng */
 529 #define CONFIG_CPM2             1       /* Has a CPM2 */
 530
 531 /*
 532  * Miscellaneous configurable options
 533  */
 534 #define CONFIG_SYS_BOOTM_HEADER_QUIET 1        /* Suppress the image header dump    */
 535                                         /* in the bootm command.             */
 536 #define CONFIG_SYS_BOOTM_PROGESS_QUIET 1       /* Suppress the progress displays,   */
 537                                         /* "## <message>" from the bootm cmd */
 538 #define CONFIG_SYS_BOOTP_CHECK_HOSTNAME 1      /* If checkhostname environment is   */
 539                                         /* defined, then the hostname param  */
 540                                         /* validated against checkhostname.  */
 541 #define CONFIG_SYS_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up   */
 542 #define CONFIG_SYS_BOOTP_SHORT_RANDOM_DELAY 1  /* Use a short random delay value    */
 543                                         /* (limited to maximum of 1024 msec) */
 544 #define CONFIG_SYS_CHK_FOR_ABORT_AT_LEAST_ONCE 1
 545                                         /* Check for abort key presses       */
 546                                         /* at least once in dependent of the */
 547                                         /* CONFIG_BOOTDELAY value.           */
 548 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1        /* Don't print console @ startup     */
 549 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1      /* Echo the inverted Ethernet link   */
 550                                         /* state to the fault LED.           */
 551 #define CONFIG_SYS_FAULT_MII_ADDR 0x02         /* MII addr of the PHY to check for  */
 552                                         /* the Ethernet link state.          */
 553 #define CONFIG_SYS_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing  */
 554                                         /* until the TFTP is successful.     */
 555 #define CONFIG_SYS_STATUS_OFF_AFTER_NETBOOT 1  /* After a successful netboot,       */
 556                                         /* turn off the STATUS LEDs.         */
 557 #define CONFIG_SYS_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on      */
 558                                         /* incoming data.                    */
 559 #define CONFIG_SYS_TFTP_BLOCKS_PER_HASH 100    /* For every XX blocks, output a '#' */
 560                                         /* to signify that tftp is moving.   */
 561 #define CONFIG_SYS_TFTP_HASHES_PER_FLASH 200   /* For every '#' hashes,             */
 562                                         /* flash the status LED.             */
 563 #define CONFIG_SYS_TFTP_HASHES_PER_LINE 65     /* Only output XX '#'s per line      */
 564                                         /* during the tftp file transfer.    */
 565 #define CONFIG_SYS_TFTP_PROGESS_QUIET 1        /* Suppress the progress displays    */
 566                                         /* '#'s from the tftp command.       */
 567 #define CONFIG_SYS_TFTP_STATUS_QUIET 1         /* Suppress the status displays      */
 568                                         /* issued during the tftp command.   */
 569 #define CONFIG_SYS_TFTP_TIMEOUT_COUNT 5        /* How many timeouts TFTP will allow */
 570                                         /* before it gives up.               */
 571
 572 #if defined(CONFIG_CMD_KGDB)
 573 #  define CONFIG_SYS_CBSIZE             1024    /* Console I/O Buffer Size           */
 574 #else
 575 #  define CONFIG_SYS_CBSIZE             256     /* Console I/O Buffer Size           */
 576 #endif
 577
 578 /* Print Buffer Size */
 579 #define CONFIG_SYS_PBSIZE         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
 580
 581 #define CONFIG_SYS_MAXARGS              32      /* max number of command args   */
 582
 583 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size     */
 584
 585 #define CONFIG_SYS_LOAD_ADDR            0x400000   /* default load address */
 586
 587 #define CONFIG_SYS_ALT_MEMTEST                 /* Select full-featured memory test */
 588 #define CONFIG_SYS_MEMTEST_START        0x2000  /* memtest works from the end of */
 589                                         /* the exception vector table */
 590                                         /* to the end of the DRAM  */
 591                                         /* less monitor and malloc area */
 592 #define CONFIG_SYS_STACK_USAGE          0x10000 /* Reserve 64k for the stack usage */
 593 #define CONFIG_SYS_MEM_END_USAGE        ( CONFIG_SYS_MONITOR_LEN \
 594                                 + CONFIG_SYS_MALLOC_LEN \
 595                                 + CONFIG_ENV_SECT_SIZE \
 596                                 + CONFIG_SYS_STACK_USAGE )
 597
 598 #define CONFIG_SYS_MEMTEST_END          ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
 599                                 - CONFIG_SYS_MEM_END_USAGE )
 600
 601 /*
 602  * Low Level Configuration Settings
 603  * (address mappings, register initial values, etc.)
 604  * You should know what you are doing if you make changes here.
 605  */
 606
 607 #define CONFIG_SYS_FLASH_BASE   CONFIG_SYS_FLASH0_BASE
 608 #define CONFIG_SYS_FLASH_SIZE   CONFIG_SYS_FLASH0_SIZE
 609 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_SDRAM0_BASE
 610 #define CONFIG_SYS_SDRAM_SIZE   CONFIG_SYS_SDRAM0_SIZE
 611
 612 /*-----------------------------------------------------------------------
 613  * Hard Reset Configuration Words
 614  */
 615 #if defined(CONFIG_SYS_SBC_BOOT_LOW)
 616 #  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 617 #else
 618 #  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (0)
 619 #endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
 620
 621 /* get the HRCW ISB field from CONFIG_SYS_IMMR */
 622 #define CONFIG_SYS_SBC_HRCW_IMMR        ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
 623                                   ((CONFIG_SYS_IMMR & 0x01000000) >>  7) | \
 624                                   ((CONFIG_SYS_IMMR & 0x00100000) >>  4) )
 625
 626 #define CONFIG_SYS_HRCW_MASTER          ( HRCW_BPS10                            | \
 627                                   HRCW_DPPC11                           | \
 628                                   CONFIG_SYS_SBC_HRCW_IMMR                      | \
 629                                   HRCW_MMR00                            | \
 630                                   HRCW_LBPC11                           | \
 631                                   HRCW_APPC10                           | \
 632                                   HRCW_CS10PC00                         | \
 633                                   (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111)   | \
 634                                   CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
 635
 636 /* no slaves */
 637 #define CONFIG_SYS_HRCW_SLAVE1          0
 638 #define CONFIG_SYS_HRCW_SLAVE2          0
 639 #define CONFIG_SYS_HRCW_SLAVE3          0
 640 #define CONFIG_SYS_HRCW_SLAVE4          0
 641 #define CONFIG_SYS_HRCW_SLAVE5          0
 642 #define CONFIG_SYS_HRCW_SLAVE6          0
 643 #define CONFIG_SYS_HRCW_SLAVE7          0
 644
 645 /*-----------------------------------------------------------------------
 646  * Definitions for initial stack pointer and data area (in DPRAM)
 647  */
 648 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 649 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM   */
 650 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 651 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 652
 653 /*-----------------------------------------------------------------------
 654  * Start addresses for the final memory configuration
 655  * (Set up by the startup code)
 656  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 657  * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
 658  */
 659 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
 660
 661 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 662 #  define CONFIG_SYS_RAMBOOT
 663 #endif
 664
 665 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 666 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 667
 668 /*
 669  * For booting Linux, the board info and command line data
 670  * have to be in the first 8 MB of memory, since this is
 671  * the maximum mapped by the Linux kernel during initialization.
 672  */
 673 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 674
 675 /*-----------------------------------------------------------------------
 676  * FLASH and environment organization
 677  */
 678
 679 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant              */
 680 #undef  CONFIG_SYS_FLASH_PROTECTION             /* use hardware protection              */
 681 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 682 #define CONFIG_SYS_MAX_FLASH_SECT       (64+4)  /* max number of sectors on one chip    */
 683
 684 #define CONFIG_SYS_FLASH_ERASE_TOUT     8000    /* Timeout for Flash Erase (in ms)      */
 685 #define CONFIG_SYS_FLASH_WRITE_TOUT     1       /* Timeout for Flash Write (in ms)      */
 686
 687 #ifndef CONFIG_SYS_RAMBOOT
 688 #  define CONFIG_ENV_IS_IN_FLASH        1
 689
 690 #  ifdef CONFIG_ENV_IN_OWN_SECT
 691 #    define CONFIG_ENV_ADDR     (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 692 #    define CONFIG_ENV_SECT_SIZE        0x10000
 693 #  else
 694 #    define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
 695 #    define CONFIG_ENV_SIZE     0x1000  /* Total Size of Environment Sector     */
 696 #    define CONFIG_ENV_SECT_SIZE        0x10000 /* see README - env sect real size      */
 697 #  endif /* CONFIG_ENV_IN_OWN_SECT */
 698
 699 #else
 700 #  define CONFIG_ENV_IS_IN_NVRAM        1
 701 #  define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 702 #  define CONFIG_ENV_SIZE               0x200
 703 #endif /* CONFIG_SYS_RAMBOOT */
 704
 705 /*-----------------------------------------------------------------------
 706  * Cache Configuration
 707  */
 708 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPU */
 709
 710 #if defined(CONFIG_CMD_KGDB)
 711 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 712 #endif
 713
 714 /*-----------------------------------------------------------------------
 715  * HIDx - Hardware Implementation-dependent Registers                    2-11
 716  *-----------------------------------------------------------------------
 717  * HID0 also contains cache control - initially enable both caches and
 718  * invalidate contents, then the final state leaves only the instruction
 719  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 720  * but Soft reset does not.
 721  *
 722  * HID1 has only read-only information - nothing to set.
 723  */
 724 #define CONFIG_SYS_HID0_INIT    (HID0_ICE  |\
 725                          HID0_DCE  |\
 726                          HID0_ICFI |\
 727                          HID0_DCI  |\
 728                          HID0_IFEM |\
 729                          HID0_ABE)
 730
 731 #define CONFIG_SYS_HID0_FINAL   (HID0_ICE  |\
 732                          HID0_IFEM |\
 733                          HID0_ABE  |\
 734                          HID0_EMCP)
 735 #define CONFIG_SYS_HID2 0
 736
 737 /*-----------------------------------------------------------------------
 738  * RMR - Reset Mode Register
 739  *-----------------------------------------------------------------------
 740  */
 741 #define CONFIG_SYS_RMR          0
 742
 743 /*-----------------------------------------------------------------------
 744  * BCR - Bus Configuration                                       4-25
 745  *-----------------------------------------------------------------------
 746  */
 747 #define CONFIG_SYS_BCR          (BCR_ETM)
 748
 749 /*-----------------------------------------------------------------------
 750  * SIUMCR - SIU Module Configuration                             4-31
 751  *-----------------------------------------------------------------------
 752  */
 753
 754 #define CONFIG_SYS_SIUMCR       (SIUMCR_DPPC11  |\
 755                          SIUMCR_L2CPC00 |\
 756                          SIUMCR_APPC10  |\
 757                          SIUMCR_MMR00)
 758
 759
 760 /*-----------------------------------------------------------------------
 761  * SYPCR - System Protection Control                            11-9
 762  * SYPCR can only be written once after reset!
 763  *-----------------------------------------------------------------------
 764  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 765  */
 766 #if defined(CONFIG_WATCHDOG)
 767 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC |\
 768                          SYPCR_BMT  |\
 769                          SYPCR_PBME |\
 770                          SYPCR_LBME |\
 771                          SYPCR_SWRI |\
 772                          SYPCR_SWP  |\
 773                          SYPCR_SWE)
 774 #else
 775 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC |\
 776                          SYPCR_BMT  |\
 777                          SYPCR_PBME |\
 778                          SYPCR_LBME |\
 779                          SYPCR_SWRI |\
 780                          SYPCR_SWP)
 781 #endif /* CONFIG_WATCHDOG */
 782
 783 /*-----------------------------------------------------------------------
 784  * TMCNTSC - Time Counter Status and Control                     4-40
 785  *-----------------------------------------------------------------------
 786  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 787  * and enable Time Counter
 788  */
 789 #define CONFIG_SYS_TMCNTSC      (TMCNTSC_SEC |\
 790                          TMCNTSC_ALR |\
 791                          TMCNTSC_TCF |\
 792                          TMCNTSC_TCE)
 793
 794 /*-----------------------------------------------------------------------
 795  * PISCR - Periodic Interrupt Status and Control                 4-42
 796  *-----------------------------------------------------------------------
 797  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 798  * Periodic timer
 799  */
 800 #define CONFIG_SYS_PISCR        (PISCR_PS  |\
 801                          PISCR_PTF |\
 802                          PISCR_PTE)
 803
 804 /*-----------------------------------------------------------------------
 805  * SCCR - System Clock Control                                   9-8
 806  *-----------------------------------------------------------------------
 807  */
 808 #define CONFIG_SYS_SCCR 0
 809
 810 /*-----------------------------------------------------------------------
 811  * RCCR - RISC Controller Configuration                         13-7
 812  *-----------------------------------------------------------------------
 813  */
 814 #define CONFIG_SYS_RCCR 0
 815
 816 /*
 817  * Initialize Memory Controller:
 818  *
 819  * Bank Bus     Machine PortSz  Device
 820  * ---- ---     ------- ------  ------
 821  *  0   60x     GPCM    16 bit  FLASH (primary flash - 2MB)
 822  *  1   60x     GPCM    -- bit  (Unused)
 823  *  2   60x     SDRAM   64 bit  SDRAM (DIMM)
 824  *  3   60x     SDRAM   64 bit  SDRAM (DIMM)
 825  *  4   60x     GPCM    -- bit  (Unused)
 826  *  5   60x     GPCM    -- bit  (Unused)
 827  *  6   60x     GPCM    16 bit  FLASH  (secondary flash - 2MB)
 828  */
 829
 830 /*-----------------------------------------------------------------------
 831  * BR0,BR1 - Base Register
 832  *     Ref: Section 10.3.1 on page 10-14
 833  * OR0,OR1 - Option Register
 834  *     Ref: Section 10.3.2 on page 10-18
 835  *-----------------------------------------------------------------------
 836  */
 837
 838 /* Bank 0 - Primary FLASH
 839  */
 840
 841 /* BR0 is configured as follows:
 842  *
 843  *     - Base address of 0x40000000
 844  *     - 16 bit port size
 845  *     - Data errors checking is disabled
 846  *     - Read and write access
 847  *     - GPCM 60x bus
 848  *     - Access are handled by the memory controller according to MSEL
 849  *     - Not used for atomic operations
 850  *     - No data pipelining is done
 851  *     - Valid
 852  */
 853 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
 854                          BRx_PS_16                      |\
 855                          BRx_MS_GPCM_P                  |\
 856                          BRx_V)
 857
 858 /* OR0 is configured as follows:
 859  *
 860  *     - 4 MB
 861  *     - *BCTL0 is asserted upon access to the current memory bank
 862  *     - *CW / *WE are negated a quarter of a clock earlier
 863  *     - *CS is output at the same time as the address lines
 864  *     - Uses a clock cycle length of 5
 865  *     - *PSDVAL is generated internally by the memory controller
 866  *       unless *GTA is asserted earlier externally.
 867  *     - Relaxed timing is generated by the GPCM for accesses
 868  *       initiated to this memory region.
 869  *     - One idle clock is inserted between a read access from the
 870  *       current bank and the next access.
 871  */
 872 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE)      |\
 873                          ORxG_CSNT                      |\
 874                          ORxG_ACS_DIV1                  |\
 875                          ORxG_SCY_5_CLK                 |\
 876                          ORxG_TRLX                      |\
 877                          ORxG_EHTR)
 878
 879 /*-----------------------------------------------------------------------
 880  * BR2,BR3 - Base Register
 881  *     Ref: Section 10.3.1 on page 10-14
 882  * OR2,OR3 - Option Register
 883  *     Ref: Section 10.3.2 on page 10-16
 884  *-----------------------------------------------------------------------
 885  */
 886
 887 /* Bank 2,3 - SDRAM DIMM
 888  */
 889
 890 /* The BR2 is configured as follows:
 891  *
 892  *     - Base address of 0x00000000
 893  *     - 64 bit port size (60x bus only)
 894  *     - Data errors checking is disabled
 895  *     - Read and write access
 896  *     - SDRAM 60x bus
 897  *     - Access are handled by the memory controller according to MSEL
 898  *     - Not used for atomic operations
 899  *     - No data pipelining is done
 900  *     - Valid
 901  */
 902 #define CONFIG_SYS_BR2_PRELIM   ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
 903                          BRx_PS_64                      |\
 904                          BRx_MS_SDRAM_P                 |\
 905                          BRx_V)
 906
 907 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
 908                          BRx_PS_64                      |\
 909                          BRx_MS_SDRAM_P                 |\
 910                          BRx_V)
 911
 912 /* With a 64 MB DIMM, the OR2 is configured as follows:
 913  *
 914  *     - 64 MB
 915  *     - 4 internal banks per device
 916  *     - Row start address bit is A8 with PSDMR[PBI] = 0
 917  *     - 12 row address lines
 918  *     - Back-to-back page mode
 919  *     - Internal bank interleaving within save device enabled
 920  */
 921 #if (CONFIG_SYS_SDRAM0_SIZE == 64)
 922 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE)      |\
 923                          ORxS_BPD_4                     |\
 924                          ORxS_ROWST_PBI0_A8             |\
 925                          ORxS_NUMR_12)
 926 #else
 927 #error "INVALID SDRAM CONFIGURATION"
 928 #endif
 929
 930 /*-----------------------------------------------------------------------
 931  * PSDMR - 60x Bus SDRAM Mode Register
 932  *     Ref: Section 10.3.3 on page 10-21
 933  *-----------------------------------------------------------------------
 934  */
 935
 936 /* Address that the DIMM SPD memory lives at.
 937  */
 938 #define SDRAM_SPD_ADDR 0x50
 939
 940 #if (CONFIG_SYS_SDRAM0_SIZE == 64)
 941 /* With a 64 MB DIMM, the PSDMR is configured as follows:
 942  *
 943  *     - Bank Based Interleaving,
 944  *     - Refresh Enable,
 945  *     - Address Multiplexing where A5 is output on A14 pin
 946  *       (A6 on A15, and so on),
 947  *     - use address pins A14-A16 as bank select,
 948  *     - A9 is output on SDA10 during an ACTIVATE command,
 949  *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
 950  *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
 951  *       is 3 clocks,
 952  *     - earliest timing for READ/WRITE command after ACTIVATE command is
 953  *       2 clocks,
 954  *     - earliest timing for PRECHARGE after last data was read is 1 clock,
 955  *     - earliest timing for PRECHARGE after last data was written is 1 clock,
 956  *     - CAS Latency is 2.
 957  */
 958 #define CONFIG_SYS_PSDMR        (PSDMR_RFEN           |\
 959                          PSDMR_SDAM_A14_IS_A5 |\
 960                          PSDMR_BSMA_A14_A16   |\
 961                          PSDMR_SDA10_PBI0_A9  |\
 962                          PSDMR_RFRC_7_CLK     |\
 963                          PSDMR_PRETOACT_3W    |\
 964                          PSDMR_ACTTORW_2W     |\
 965                          PSDMR_LDOTOPRE_1C    |\
 966                          PSDMR_WRC_1C         |\
 967                          PSDMR_CL_2)
 968 #else
 969 #error "INVALID SDRAM CONFIGURATION"
 970 #endif
 971
 972 /*
 973  * Shoot for approximately 1MHz on the prescaler.
 974  */
 975 #if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000))
 976 #define CONFIG_SYS_MPTPR        MPTPR_PTP_DIV64
 977 #elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000))
 978 #define CONFIG_SYS_MPTPR        MPTPR_PTP_DIV32
 979 #else
 980 #warning "Unconfigured bus clock freq: check CONFIG_SYS_MPTPR and CONFIG_SYS_PSRT are OK"
 981 #define CONFIG_SYS_MPTPR        MPTPR_PTP_DIV32
 982 #endif
 983 #define CONFIG_SYS_PSRT 14
 984
 985
 986 /*-----------------------------------------------------------------------
 987  * BR6 - Base Register
 988  *     Ref: Section 10.3.1 on page 10-14
 989  * OR6 - Option Register
 990  *     Ref: Section 10.3.2 on page 10-18
 991  *-----------------------------------------------------------------------
 992  */
 993
 994 /* Bank 6 - Secondary FLASH
 995  *
 996  * The secondary FLASH is connected to *CS6
 997  */
 998 #if (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE))
 999
1000 /* BR6 is configured as follows:
1001  *
1002  *     - Base address of 0x60000000
1003  *     - 16 bit port size
1004  *     - Data errors checking is disabled
1005  *     - Read and write access
1006  *     - GPCM 60x bus
1007  *     - Access are handled by the memory controller according to MSEL
1008  *     - Not used for atomic operations
1009  *     - No data pipelining is done
1010  *     - Valid
1011  */
1012 #  define CONFIG_SYS_BR6_PRELIM  ((CONFIG_SYS_FLASH1_BASE & BRx_BA_MSK) |\
1013                            BRx_PS_16                      |\
1014                            BRx_MS_GPCM_P                  |\
1015                            BRx_V)
1016
1017 /* OR6 is configured as follows:
1018  *
1019  *     - 2 MB
1020  *     - *BCTL0 is asserted upon access to the current memory bank
1021  *     - *CW / *WE are negated a quarter of a clock earlier
1022  *     - *CS is output at the same time as the address lines
1023  *     - Uses a clock cycle length of 5
1024  *     - *PSDVAL is generated internally by the memory controller
1025  *       unless *GTA is asserted earlier externally.
1026  *     - Relaxed timing is generated by the GPCM for accesses
1027  *       initiated to this memory region.
1028  *     - One idle clock is inserted between a read access from the
1029  *       current bank and the next access.
1030  */
1031 #  define CONFIG_SYS_OR6_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH1_SIZE)  |\
1032                            ORxG_CSNT                   |\
1033                            ORxG_ACS_DIV1               |\
1034                            ORxG_SCY_5_CLK              |\
1035                            ORxG_TRLX                   |\
1036                            ORxG_EHTR)
1037 #endif /* (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) */
1038
1039 #endif  /* __CONFIG_H */