include/configs/sama5d3xek.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the SAMA5D3xEK board.
   4  *
   5  * Copyright (C) 2012 - 2013 Atmel
   6  *
   7  * based on at91sam9m10g45ek.h by:
   8  * Stelian Pop <stelian@popies.net>
   9  * Lead Tech Design <www.leadtechdesign.com>
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 #include "at91-sama5_common.h"
  16
  17 /*
  18  * This needs to be defined for the OHCI code to work but it is defined as
  19  * ATMEL_ID_UHPHS in the CPU specific header files.
  20  */
  21 #define ATMEL_ID_UHP                    32
  22
  23 /*
  24  * Specify the clock enable bit in the PMC_SCER register.
  25  */
  26 #define ATMEL_PMC_UHP                   (1 <<  6)
  27
  28 /* board specific (not enough SRAM) */
  29 #define CONFIG_SAMA5D3_LCD_BASE         0x23E00000
  30
  31 /* NOR flash */
  32 #ifdef CONFIG_MTD_NOR_FLASH
  33 #define CONFIG_SYS_FLASH_BASE           0x10000000
  34 #define CONFIG_SYS_MAX_FLASH_SECT       131
  35 #endif
  36
  37 /* SDRAM */
  38 #define CONFIG_SYS_SDRAM_BASE           0x20000000
  39 #define CONFIG_SYS_SDRAM_SIZE           0x20000000
  40
  41 /* SerialFlash */
  42
  43 /* NAND flash */
  44 #ifdef CONFIG_CMD_NAND
  45 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  46 #define CONFIG_SYS_NAND_BASE            0x60000000
  47 /* our ALE is AD21 */
  48 #define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
  49 /* our CLE is AD22 */
  50 #define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
  51 #endif
  52
  53 /* USB */
  54 #ifdef CONFIG_CMD_USB
  55 #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
  56 #define CONFIG_USB_OHCI_NEW
  57 #define CONFIG_SYS_USB_OHCI_CPU_INIT
  58 #define CONFIG_SYS_USB_OHCI_REGS_BASE           ATMEL_BASE_OHCI
  59 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "sama5d3"
  60 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      3
  61 #endif
  62
  63 /* SPL */
  64
  65 #define CONFIG_SYS_MONITOR_LEN          (512 << 10)
  66
  67 #endif