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Blackfin: unify default I2C settings for ADI boards
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1 /*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 * Gary Jennejohn <garyj@denx.de>
6 * David Mueller <d.mueller@elsoft.ch>
7 *
8 * Modified for the friendly-arm SBC-2410X by
9 * (C) Copyright 2005
10 * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
11 *
12 * Configuation settings for the friendly-arm SBC-2410X board.
13 *
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 */
32
33 #ifndef __CONFIG_H
34 #define __CONFIG_H
35
36 /*
37 * If we are developing, we might want to start armboot from ram
38 * so we MUST NOT initialize critical regs like mem-timing ...
39 */
40 #undef CONFIG_SKIP_LOWLEVEL_INIT /* undef for developing */
41
42 /*
43 * High Level Configuration Options
44 * (easy to change)
45 */
46 #define CONFIG_ARM920T 1 /* This is an ARM920T Core */
47 #define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
48 #define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
49 #define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */
50
51 /* input clock of PLL */
52 #define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */
53
54
55 #define USE_920T_MMU 1
56 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
57
58 /*
59 * Size of malloc() pool
60 */
61 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
62 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
63
64 /*
65 * Hardware drivers
66 */
67 #define CONFIG_NET_MULTI
68 #define CONFIG_CS8900 /* we have a CS8900 on-board */
69 #define CONFIG_CS8900_BASE 0x19000300
70 #define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */
71
72 /*
73 * select serial console configuration
74 */
75 #define CONFIG_S3C24X0_SERIAL
76 #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SBC2410X */
77
78 /************************************************************
79 * RTC
80 ************************************************************/
81 #define CONFIG_RTC_S3C24X0 1
82
83 /* allow to overwrite serial and ethaddr */
84 #define CONFIG_ENV_OVERWRITE
85
86 #define CONFIG_BAUDRATE 115200
87
88
89 /*
90 * BOOTP options
91 */
92 #define CONFIG_BOOTP_BOOTFILESIZE
93 #define CONFIG_BOOTP_BOOTPATH
94 #define CONFIG_BOOTP_GATEWAY
95 #define CONFIG_BOOTP_HOSTNAME
96
97
98 /*
99 * Command line configuration.
100 */
101 #include <config_cmd_default.h>
102
103 #define CONFIG_CMD_ASKENV
104 #define CONFIG_CMD_CACHE
105 #define CONFIG_CMD_DATE
106 #define CONFIG_CMD_DHCP
107 #define CONFIG_CMD_ELF
108 #define CONFIG_CMD_PING
109
110
111 #define CONFIG_BOOTDELAY 3
112 #define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs " \
113 "nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv " \
114 "ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
115 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b
116 #define CONFIG_NETMASK 255.255.255.0
117 #define CONFIG_IPADDR 192.168.0.69
118 #define CONFIG_SERVERIP 192.168.0.1
119 /*#define CONFIG_BOOTFILE "elinos-lart" */
120 #define CONFIG_BOOTCOMMAND "dhcp; bootm"
121
122 #if defined(CONFIG_CMD_KGDB)
123 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
124 /* what's this ? it's not used anywhere */
125 #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
126 #endif
127
128 /*
129 * Miscellaneous configurable options
130 */
131 #define CONFIG_SYS_LONGHELP /* undef to save memory */
132 #define CONFIG_SYS_PROMPT "[ ~ljh@GDLC ]# " /* Monitor Command Prompt */
133 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
134 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
135 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
136 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
137
138 #define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
139 #define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
140
141 #define CONFIG_SYS_LOAD_ADDR 0x33000000 /* default load address */
142
143 #define CONFIG_SYS_HZ 1000
144
145 /* valid baudrates */
146 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
147
148 /*-----------------------------------------------------------------------
149 * Stack sizes
150 *
151 * The stack sizes are set up in start.S using the settings below
152 */
153 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
154 #ifdef CONFIG_USE_IRQ
155 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
156 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
157 #endif
158
159 /*-----------------------------------------------------------------------
160 * Physical Memory Map
161 */
162 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
163 #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
164 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
165
166 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
167
168 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
169
170 /*-----------------------------------------------------------------------
171 * FLASH and environment organization
172 */
173 /* #define CONFIG_AMD_LV400 1 /\* uncomment this if you have a LV400 flash *\/ */
174
175 #define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
176
177 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
178
179 #ifdef CONFIG_AMD_LV800
180 #define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
181 #define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
182 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
183 #endif
184
185 #ifdef CONFIG_AMD_LV400
186 #define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
187 #define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
188 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
189 #endif
190
191 /* timeout values are in ticks */
192 #define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
193 #define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
194
195 #define CONFIG_ENV_IS_IN_FLASH 1
196 #define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
197
198 /*-----------------------------------------------------------------------
199 * NAND flash settings
200 */
201 #if defined(CONFIG_CMD_NAND)
202 #define CONFIG_NAND_S3C2410
203 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
204 #endif /* CONFIG_CMD_NAND */
205
206 #define CONFIG_SETUP_MEMORY_TAGS
207 #define CONFIG_INITRD_TAG
208 #define CONFIG_CMDLINE_TAG
209
210 #define CONFIG_SYS_HUSH_PARSER
211 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
212
213 #define CONFIG_CMDLINE_EDITING
214
215 #ifdef CONFIG_CMDLINE_EDITING
216 #undef CONFIG_AUTO_COMPLETE
217 #else
218 #define CONFIG_AUTO_COMPLETE
219 #endif
220
221 #endif /* __CONFIG_H */