include/configs/sbc2410x.h

   1 /*
   2  * (C) Copyright 2002
   3  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4  * Marius Groeger <mgroeger@sysgo.de>
   5  * Gary Jennejohn <gj@denx.de>
   6  * David Mueller <d.mueller@elsoft.ch>
   7  *
   8  * Modified for the friendly-arm SBC-2410X by
   9  * (C) Copyright 2005
  10  * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
  11  *
  12  * Configuation settings for the friendly-arm SBC-2410X board.
  13  *
  14  * See file CREDITS for list of people who contributed to this
  15  * project.
  16  *
  17  * This program is free software; you can redistribute it and/or
  18  * modify it under the terms of the GNU General Public License as
  19  * published by the Free Software Foundation; either version 2 of
  20  * the License, or (at your option) any later version.
  21  *
  22  * This program is distributed in the hope that it will be useful,
  23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  * GNU General Public License for more details.
  26  *
  27  * You should have received a copy of the GNU General Public License
  28  * along with this program; if not, write to the Free Software
  29  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30  * MA 02111-1307 USA
  31  */
  32
  33 #ifndef __CONFIG_H
  34 #define __CONFIG_H
  35
  36 /*
  37  * If we are developing, we might want to start armboot from ram
  38  * so we MUST NOT initialize critical regs like mem-timing ...
  39  */
  40 #undef CONFIG_SKIP_LOWLEVEL_INIT        /* undef for developing */
  41
  42 /*
  43  * High Level Configuration Options
  44  * (easy to change)
  45  */
  46 #define CONFIG_ARM920T          1       /* This is an ARM920T Core      */
  47 #define CONFIG_S3C2410          1       /* in a SAMSUNG S3C2410 SoC     */
  48 #define CONFIG_SBC2410X         1       /* on a friendly-arm SBC-2410X Board  */
  49
  50 /* input clock of PLL */
  51 #define CONFIG_SYS_CLK_FREQ     12000000/* the SBC2410X has 12MHz input clock */
  52
  53
  54 #define USE_920T_MMU            1
  55 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
  56
  57 /*
  58  * Size of malloc() pool
  59  */
  60 #define CFG_MALLOC_LEN          (CFG_ENV_SIZE + 128*1024)
  61 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
  62
  63 /*
  64  * Hardware drivers
  65  */
  66 #define CONFIG_DRIVER_CS8900    1       /* we have a CS8900 on-board */
  67 #define CS8900_BASE             0x19000300
  68 #define CS8900_BUS16            1 /* the Linux driver does accesses as shorts */
  69
  70 /*
  71  * select serial console configuration
  72  */
  73 #define CONFIG_SERIAL1          1       /* we use SERIAL 1 on SBC2410X */
  74
  75 /************************************************************
  76  * RTC
  77  ************************************************************/
  78 #define CONFIG_RTC_S3C24X0      1
  79
  80 /* allow to overwrite serial and ethaddr */
  81 #define CONFIG_ENV_OVERWRITE
  82
  83 #define CONFIG_BAUDRATE         115200
  84
  85 /***********************************************************
  86  * Command definition
  87  ***********************************************************/
  88 #define CONFIG_COMMANDS \
  89                         (CONFIG_CMD_DFL  | \
  90                         CFG_CMD_CACHE    | \
  91                         /*CFG_CMD_NAND   |*/ \
  92                         /*CFG_CMD_EEPROM |*/ \
  93                         /*CFG_CMD_I2C    |*/ \
  94                         /*CFG_CMD_USB    |*/ \
  95                         CFG_CMD_REGINFO  | \
  96                         CFG_CMD_DATE     | \
  97                         CFG_CMD_PING     | \
  98                         CFG_CMD_DHCP     | \
  99                         CFG_CMD_ELF)
 100
 101 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 102 #include <cmd_confdefs.h>
 103
 104 #define CONFIG_BOOTDELAY        3
 105 #define CONFIG_BOOTARGS         "console=ttySAC0 root=/dev/nfs nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
 106 #define CONFIG_ETHADDR          08:00:3e:26:0a:5b
 107 #define CONFIG_NETMASK          255.255.255.0
 108 #define CONFIG_IPADDR           192.168.0.69
 109 #define CONFIG_SERVERIP         192.168.0.1
 110 /*#define CONFIG_BOOTFILE       "elinos-lart" */
 111 #define CONFIG_BOOTCOMMAND      "dhcp; bootm"
 112
 113 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 114 #define CONFIG_KGDB_BAUDRATE    115200          /* speed to run kgdb serial port */
 115 /* what's this ? it's not used anywhere */
 116 #define CONFIG_KGDB_SER_INDEX   1               /* which serial port to use */
 117 #endif
 118
 119 /*
 120  * Miscellaneous configurable options
 121  */
 122 #define CFG_LONGHELP                            /* undef to save memory         */
 123 #define CFG_PROMPT              "[ ~ljh@GDLC ]# "       /* Monitor Command Prompt       */
 124 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 125 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 126 #define CFG_MAXARGS             16              /* max number of command args   */
 127 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 128
 129 #define CFG_MEMTEST_START       0x30000000      /* memtest works on     */
 130 #define CFG_MEMTEST_END         0x33F00000      /* 63 MB in DRAM        */
 131
 132 #undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 133
 134 #define CFG_LOAD_ADDR           0x33000000      /* default load address */
 135
 136 /* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
 137 /* it to wrap 100 times (total 1562500) to get 1 sec. */
 138 #define CFG_HZ                  1562500
 139
 140 /* valid baudrates */
 141 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 142
 143 /*-----------------------------------------------------------------------
 144  * Stack sizes
 145  *
 146  * The stack sizes are set up in start.S using the settings below
 147  */
 148 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 149 #ifdef CONFIG_USE_IRQ
 150 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 151 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 152 #endif
 153
 154 /*-----------------------------------------------------------------------
 155  * Physical Memory Map
 156  */
 157 #define CONFIG_NR_DRAM_BANKS    1          /* we have 1 bank of DRAM */
 158 #define PHYS_SDRAM_1            0x30000000 /* SDRAM Bank #1 */
 159 #define PHYS_SDRAM_1_SIZE       0x04000000 /* 64 MB */
 160
 161 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
 162
 163 #define CFG_FLASH_BASE          PHYS_FLASH_1
 164
 165 /*-----------------------------------------------------------------------
 166  * FLASH and environment organization
 167  */
 168 /* #define CONFIG_AMD_LV400     1       /\* uncomment this if you have a LV400 flash *\/ */
 169
 170 #define CONFIG_AMD_LV800        1       /* uncomment this if you have a LV800 flash */
 171
 172 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks */
 173
 174 #ifdef CONFIG_AMD_LV800
 175 #define PHYS_FLASH_SIZE         0x00100000 /* 1MB */
 176 #define CFG_MAX_FLASH_SECT      (19)    /* max number of sectors on one chip */
 177 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
 178 #endif
 179
 180 #ifdef CONFIG_AMD_LV400
 181 #define PHYS_FLASH_SIZE         0x00080000 /* 512KB */
 182 #define CFG_MAX_FLASH_SECT      (11)    /* max number of sectors on one chip */
 183 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x070000) /* addr of environment */
 184 #endif
 185
 186 /* timeout values are in ticks */
 187 #define CFG_FLASH_ERASE_TOUT    (5*CFG_HZ) /* Timeout for Flash Erase */
 188 #define CFG_FLASH_WRITE_TOUT    (5*CFG_HZ) /* Timeout for Flash Write */
 189
 190 #define CFG_ENV_IS_IN_FLASH     1
 191 #define CFG_ENV_SIZE            0x10000 /* Total Size of Environment Sector */
 192
 193 /*-----------------------------------------------------------------------
 194  * NAND flash settings
 195  */
 196 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 197 #define CFG_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */
 198 #define SECTORSIZE 512
 199
 200 #define ADDR_COLUMN 1
 201 #define ADDR_PAGE 2
 202 #define ADDR_COLUMN_PAGE 3
 203
 204 #define NAND_ChipID_UNKNOWN     0x00
 205 #define NAND_MAX_FLOORS 1
 206 #define NAND_MAX_CHIPS 1
 207
 208 #define NAND_WAIT_READY(nand)   NF_WaitRB()
 209 #define NAND_DISABLE_CE(nand)   NF_SetCE(NFCE_HIGH)
 210 #define NAND_ENABLE_CE(nand)    NF_SetCE(NFCE_LOW)
 211 #define WRITE_NAND_COMMAND(d, adr)      NF_Cmd(d)
 212 #define WRITE_NAND_COMMANDW(d, adr)     NF_CmdW(d)
 213 #define WRITE_NAND_ADDRESS(d, adr)      NF_Addr(d)
 214 #define WRITE_NAND(d, adr)              NF_Write(d)
 215 #define READ_NAND(adr)                  NF_Read()
 216 /* the following functions are NOP's because S3C24X0 handles this in hardware */
 217 #define NAND_CTL_CLRALE(nandptr)
 218 #define NAND_CTL_SETALE(nandptr)
 219 #define NAND_CTL_CLRCLE(nandptr)
 220 #define NAND_CTL_SETCLE(nandptr)
 221 /* #undef CONFIG_MTD_NAND_VERIFY_WRITE */
 222 #endif  /* CONFIG_COMMANDS & CFG_CMD_NAND */
 223
 224 #define CONFIG_SETUP_MEMORY_TAGS
 225 #define CONFIG_INITRD_TAG
 226 #define CONFIG_CMDLINE_TAG
 227
 228 #define CFG_HUSH_PARSER
 229 #define CFG_PROMPT_HUSH_PS2   "> "
 230
 231 #define CONFIG_CMDLINE_EDITING
 232
 233 #ifdef CONFIG_CMDLINE_EDITING
 234 #undef CONFIG_AUTO_COMPLETE
 235 #else
 236 #define CONFIG_AUTO_COMPLETE
 237 #endif
 238
 239 #endif  /* __CONFIG_H */