include/configs/sbc35_a9g20.h

   1 /*
   2  * Copyright (C) 2009
   3  * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
   4  *
   5  * Configuation settings for the Calao SBC35-A9G20 board
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /* SoC type is defined in boards.cfg */
  14 #include <asm/hardware.h>
  15 #include <linux/sizes.h>
  16
  17 #if defined(CONFIG_SYS_USE_NANDFLASH)
  18 #define CONFIG_ENV_IS_IN_NAND
  19 #else
  20 #define CONFIG_ENV_IS_IN_EEPROM
  21 #endif
  22
  23 #define MACH_TYPE_SBC35_A9G20           1848
  24 #define CONFIG_MACH_TYPE                MACH_TYPE_SBC35_A9G20
  25
  26 /* ARM asynchronous clock */
  27 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock xtal */
  28 #define CONFIG_SYS_AT91_MAIN_CLOCK      12000000        /* 12.000 MHz crystal */
  29
  30 #define CONFIG_ARCH_CPU_INIT
  31
  32 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
  33 #define CONFIG_SETUP_MEMORY_TAGS
  34 #define CONFIG_INITRD_TAG
  35 #define CONFIG_SKIP_LOWLEVEL_INIT
  36
  37 /* GPIO */
  38 #define CONFIG_ATMEL_LEGACY             /* required until (g)pio is fixed */
  39 #define CONFIG_AT91_GPIO
  40
  41 /* Serial */
  42 #define CONFIG_ATMEL_USART
  43 #define CONFIG_USART_BASE               ATMEL_BASE_DBGU
  44 #define CONFIG_USART_ID                 ATMEL_ID_SYS
  45 #define CONFIG_BAUDRATE                 115200
  46
  47 #define CONFIG_BOOTDELAY        3
  48
  49 /*
  50  * BOOTP options
  51  */
  52 #define CONFIG_BOOTP_BOOTFILESIZE
  53 #define CONFIG_BOOTP_BOOTPATH
  54 #define CONFIG_BOOTP_GATEWAY
  55 #define CONFIG_BOOTP_HOSTNAME
  56
  57 /*
  58  * Command line configuration.
  59  */
  60 #include <config_cmd_default.h>
  61 #undef CONFIG_CMD_BDI
  62 #undef CONFIG_CMD_FPGA
  63 #undef CONFIG_CMD_IMI
  64 #undef CONFIG_CMD_IMLS
  65 #undef CONFIG_CMD_LOADS
  66 #undef CONFIG_CMD_SOURCE
  67
  68 #define CONFIG_CMD_PING
  69 #define CONFIG_CMD_DHCP
  70 #define CONFIG_CMD_USB
  71
  72 /* SDRAM */
  73 #define CONFIG_NR_DRAM_BANKS    1
  74 #define CONFIG_SYS_SDRAM_BASE   ATMEL_BASE_CS1
  75 #define CONFIG_SYS_SDRAM_SIZE   0x04000000      /* 64 megs */
  76 #define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \
  77                                  GENERATED_GBL_DATA_SIZE)
  78
  79 /* SPI EEPROM */
  80 #define CONFIG_SPI
  81 #define CONFIG_CMD_SPI
  82 #define CONFIG_ATMEL_SPI
  83
  84 #define CONFIG_CMD_EEPROM
  85 #define CONFIG_SPI_M95XXX
  86 #define CONFIG_SYS_EEPROM_SIZE 0x10000
  87 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
  88
  89 /* SPI RTC */
  90 #define CONFIG_CMD_DATE
  91 #define CONFIG_RTC_M41T94
  92 #define CONFIG_M41T94_SPI_BUS 0
  93 #define CONFIG_M41T94_SPI_CS 0
  94
  95 /* NAND flash */
  96 #define CONFIG_CMD_NAND
  97 #define CONFIG_NAND_ATMEL
  98 #define CONFIG_SYS_MAX_NAND_DEVICE              1
  99 #define CONFIG_SYS_NAND_BASE                    0x40000000
 100 #define CONFIG_SYS_NAND_DBW_8
 101 /* our ALE is AD21 */
 102 #define CONFIG_SYS_NAND_MASK_ALE                (1 << 21)
 103 /* our CLE is AD22 */
 104 #define CONFIG_SYS_NAND_MASK_CLE                (1 << 22)
 105 #define CONFIG_SYS_NAND_ENABLE_PIN              AT91_PIN_PC14
 106 #define CONFIG_SYS_NAND_READY_PIN               AT91_PIN_PC13
 107
 108 /* NOR flash - no real flash on this board */
 109 #define CONFIG_SYS_NO_FLASH                     1
 110
 111 /* Ethernet */
 112 #define CONFIG_MACB
 113 #define CONFIG_RMII
 114 #define CONFIG_NET_RETRY_COUNT          20
 115 #define CONFIG_RESET_PHY_R
 116 #define CONFIG_MACB_SEARCH_PHY
 117 #define CONFIG_AT91_WANTS_COMMON_PHY
 118
 119 /* USB */
 120 #define CONFIG_USB_ATMEL
 121 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 122 #define CONFIG_USB_OHCI_NEW
 123 #define CONFIG_DOS_PARTITION
 124 #define CONFIG_SYS_USB_OHCI_CPU_INIT
 125 #define CONFIG_SYS_USB_OHCI_REGS_BASE   0x00500000      /* AT91SAM9260_UHP_BASE */
 126 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "at91sam9260"
 127 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 128 #define CONFIG_USB_STORAGE
 129 #define CONFIG_CMD_FAT
 130
 131 #define CONFIG_SYS_LOAD_ADDR            0x22000000      /* load address */
 132
 133 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
 134 #define CONFIG_SYS_MEMTEST_END          0x23e00000
 135
 136 /* Env in EEPROM, bootstrap + u-boot in NAND*/
 137 #ifdef CONFIG_ENV_IS_IN_EEPROM
 138 #define CONFIG_ENV_OFFSET       0x20
 139 #define CONFIG_ENV_SIZE         0x1000
 140 #endif
 141
 142 /* Env, bootstrap and u-boot in NAND */
 143 #ifdef CONFIG_ENV_IS_IN_NAND
 144 #define CONFIG_ENV_OFFSET               0x60000
 145 #define CONFIG_ENV_OFFSET_REDUND        0x80000
 146 #define CONFIG_ENV_SIZE                 0x20000
 147 #endif
 148
 149 #define CONFIG_BOOTCOMMAND      "nboot 0x21000000 0 400000"
 150 #define CONFIG_BOOTARGS         "console=ttyS0,115200 " \
 151                                 "root=/dev/mtdblock1 " \
 152                                 "mtdparts=atmel_nand:16M(kernel)ro," \
 153                                 "120M(rootfs),-(other) " \
 154                                 "rw rootfstype=jffs2"
 155
 156
 157 #define CONFIG_SYS_PROMPT       "U-Boot> "
 158 #define CONFIG_SYS_CBSIZE       256
 159 #define CONFIG_SYS_MAXARGS      16
 160 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 161 #define CONFIG_SYS_LONGHELP     1
 162 #define CONFIG_CMDLINE_EDITING  1
 163
 164 /*
 165  * Size of malloc() pool
 166  */
 167 #define CONFIG_SYS_MALLOC_LEN   ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
 168
 169 #endif