include/configs/sbc8548.h

   1 /*
   2  * Copyright 2007 Wind River Systems <www.windriver.com>
   3  * Copyright 2007 Embedded Specialties, Inc.
   4  * Copyright 2004, 2007 Freescale Semiconductor.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * sbc8548 board configuration file
  27  *
  28  * Please refer to doc/README.sbc85xx for more info.
  29  *
  30  */
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 /* High Level Configuration Options */
  35 #define CONFIG_BOOKE            1       /* BOOKE */
  36 #define CONFIG_E500             1       /* BOOKE e500 family */
  37 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  38 #define CONFIG_MPC8548          1       /* MPC8548 specific */
  39 #define CONFIG_SBC8548          1       /* SBC8548 board specific */
  40
  41 #undef CONFIG_PCI               /* enable any pci type devices */
  42 #undef CONFIG_PCI1              /* PCI controller 1 */
  43 #undef CONFIG_PCIE1             /* PCIE controler 1 (slot 1) */
  44 #undef CONFIG_RIO
  45 #undef CONFIG_FSL_PCI_INIT              /* Use common FSL init code */
  46
  47 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  48 #define CONFIG_ENV_OVERWRITE
  49
  50 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  51
  52 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  53
  54 #define CONFIG_SYS_CLK_FREQ     66000000 /* SBC8548 default SYSCLK */
  55
  56 /*
  57  * These can be toggled for performance analysis, otherwise use default.
  58  */
  59 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  60 #define CONFIG_BTB                      /* toggle branch predition */
  61
  62 /*
  63  * Only possible on E500 Version 2 or newer cores.
  64  */
  65 #define CONFIG_ENABLE_36BIT_PHYS        1
  66
  67 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  68
  69 #undef  CONFIG_SYS_DRAM_TEST                    /* memory test, takes time */
  70 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  71 #define CONFIG_SYS_MEMTEST_END          0x00400000
  72
  73 /*
  74  * Base addresses -- Note these are effective addresses where the
  75  * actual resources get mapped (not physical addresses)
  76  */
  77 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  78 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  79 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
  80 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  81
  82 #define CONFIG_SYS_PCI1_ADDR    (CONFIG_SYS_CCSRBAR+0x8000)
  83 #define CONFIG_SYS_PCI2_ADDR    (CONFIG_SYS_CCSRBAR+0x9000)
  84 #define CONFIG_SYS_PCIE1_ADDR   (CONFIG_SYS_CCSRBAR+0xa000)
  85
  86 /* DDR Setup */
  87 #define CONFIG_FSL_DDR2
  88 #undef CONFIG_FSL_DDR_INTERACTIVE
  89 #undef CONFIG_SPD_EEPROM                /* Use SPD EEPROM for DDR setup */
  90 #undef CONFIG_DDR_SPD
  91 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  92
  93 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  94 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  95
  96 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  97 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  98 #define CONFIG_VERY_BIG_RAM
  99
 100 #define CONFIG_NUM_DDR_CONTROLLERS      1
 101 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 102 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 103
 104 /* I2C addresses of SPD EEPROMs */
 105 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 106
 107 /*
 108  * Make sure required options are set
 109  */
 110 #ifndef CONFIG_SPD_EEPROM
 111         #define CONFIG_SYS_SDRAM_SIZE   256             /* DDR is 256MB */
 112 #endif
 113
 114 #undef CONFIG_CLOCKS_IN_MHZ
 115
 116 /*
 117  * FLASH on the Local Bus
 118  * Two banks, one 8MB the other 64MB, using the CFI driver.
 119  * Boot from BR0/OR0 bank at 0xff80_0000
 120  * Alternate BR6/OR6 bank at 0xfb80_0000
 121  *
 122  * BR0:
 123  *    Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
 124  *    Port Size = 8 bits = BRx[19:20] = 01
 125  *    Use GPCM = BRx[24:26] = 000
 126  *    Valid = BRx[31] = 1
 127  *
 128  * 0    4    8    12   16   20   24   28
 129  * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801    BR0
 130  *
 131  * BR6:
 132  *    Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0
 133  *    Port Size = 32 bits = BRx[19:20] = 11
 134  *    Use GPCM = BRx[24:26] = 000
 135  *    Valid = BRx[31] = 1
 136  *
 137  * 0    4    8    12   16   20   24   28
 138  * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801    BR6
 139  *
 140  * OR0:
 141  *    Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
 142  *    XAM = OR0[17:18] = 11
 143  *    CSNT = OR0[20] = 1
 144  *    ACS = half cycle delay = OR0[21:22] = 11
 145  *    SCY = 6 = OR0[24:27] = 0110
 146  *    TRLX = use relaxed timing = OR0[29] = 1
 147  *    EAD = use external address latch delay = OR0[31] = 1
 148  *
 149  * 0    4    8    12   16   20   24   28
 150  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR0
 151  *
 152  * OR6:
 153  *    Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0
 154  *    XAM = OR6[17:18] = 11
 155  *    CSNT = OR6[20] = 1
 156  *    ACS = half cycle delay = OR6[21:22] = 11
 157  *    SCY = 6 = OR6[24:27] = 0110
 158  *    TRLX = use relaxed timing = OR6[29] = 1
 159  *    EAD = use external address latch delay = OR6[31] = 1
 160  *
 161  * 0    4    8    12   16   20   24   28
 162  * 1111 1000 0000 0000 0110 1110 0110 0101 = f8006e65    OR6
 163  */
 164
 165 #define CONFIG_SYS_BOOT_BLOCK           0xff800000      /* start of 8MB Flash */
 166 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_BOOT_BLOCK   /* start of FLASH 16M */
 167
 168 #define CONFIG_SYS_BR0_PRELIM           0xff800801
 169 #define CONFIG_SYS_BR6_PRELIM           0xfb801801
 170
 171 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 172 #define CONFIG_SYS_OR6_PRELIM           0xf8006e65
 173
 174 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
 175 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 176 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 177 #undef  CONFIG_SYS_FLASH_CHECKSUM
 178 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 179 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 180
 181 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 182
 183 #define CONFIG_FLASH_CFI_DRIVER
 184 #define CONFIG_SYS_FLASH_CFI
 185 #define CONFIG_SYS_FLASH_EMPTY_INFO
 186
 187 /* CS5 = Local bus peripherals controlled by the EPLD */
 188
 189 #define CONFIG_SYS_BR5_PRELIM           0xf8000801
 190 #define CONFIG_SYS_OR5_PRELIM           0xff006e65
 191 #define CONFIG_SYS_EPLD_BASE            0xf8000000
 192 #define CONFIG_SYS_LED_DISP_BASE        0xf8000000
 193 #define CONFIG_SYS_USER_SWITCHES_BASE   0xf8100000
 194 #define CONFIG_SYS_BD_REV               0xf8300000
 195 #define CONFIG_SYS_EEPROM_BASE          0xf8b00000
 196
 197 /*
 198  * SDRAM on the Local Bus
 199  */
 200 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 201 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 202
 203 /*
 204  * Base Register 3 and Option Register 3 configure SDRAM.
 205  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 206  *
 207  * For BR3, need:
 208  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 209  *    port-size = 32-bits = BR2[19:20] = 11
 210  *    no parity checking = BR2[21:22] = 00
 211  *    SDRAM for MSEL = BR2[24:26] = 011
 212  *    Valid = BR[31] = 1
 213  *
 214  * 0    4    8    12   16   20   24   28
 215  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 216  *
 217  */
 218
 219 #define CONFIG_SYS_BR3_PRELIM           0xf0001861
 220
 221 /*
 222  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 223  *
 224  * For OR3, need:
 225  *    64MB mask for AM, OR3[0:7] = 1111 1100
 226  *                 XAM, OR3[17:18] = 11
 227  *    10 columns OR3[19-21] = 011
 228  *    12 rows   OR3[23-25] = 011
 229  *    EAD set for extra time OR[31] = 0
 230  *
 231  * 0    4    8    12   16   20   24   28
 232  * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
 233  */
 234
 235 #define CONFIG_SYS_OR3_PRELIM           0xfc006cc0
 236
 237 #define CONFIG_SYS_LBC_LCRR             0x00000002    /* LB clock ratio reg */
 238 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 239 #define CONFIG_SYS_LBC_LSRT             0x20000000  /* LB sdram refresh timer */
 240 #define CONFIG_SYS_LBC_MRTPR            0x00000000  /* LB refresh timer prescal*/
 241
 242 /*
 243  * Common settings for all Local Bus SDRAM commands.
 244  * At run time, either BSMA1516 (for CPU 1.1)
 245  *                  or BSMA1617 (for CPU 1.0) (old)
 246  * is OR'ed in too.
 247  */
 248 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 249                                 | LSDMR_PRETOACT7       \
 250                                 | LSDMR_ACTTORW7        \
 251                                 | LSDMR_BL8             \
 252                                 | LSDMR_WRC4            \
 253                                 | LSDMR_CL3             \
 254                                 | LSDMR_RFEN            \
 255                                 )
 256
 257 #define CONFIG_SYS_INIT_RAM_LOCK        1
 258 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 259 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End of used area in RAM */
 260
 261 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000      /* relocate boot L2SRAM */
 262
 263 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 264 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 265 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 266
 267 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 268 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 269
 270 /* Serial Port */
 271 #define CONFIG_CONS_INDEX       1
 272 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 273 #define CONFIG_SYS_NS16550
 274 #define CONFIG_SYS_NS16550_SERIAL
 275 #define CONFIG_SYS_NS16550_REG_SIZE     1
 276 #define CONFIG_SYS_NS16550_CLK          400000000 /* get_bus_freq(0) */
 277
 278 #define CONFIG_SYS_BAUDRATE_TABLE \
 279         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 280
 281 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 282 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 283
 284 /* Use the HUSH parser */
 285 #define CONFIG_SYS_HUSH_PARSER
 286 #ifdef  CONFIG_SYS_HUSH_PARSER
 287 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 288 #endif
 289
 290 /* pass open firmware flat tree */
 291 #define CONFIG_OF_LIBFDT                1
 292 #define CONFIG_OF_BOARD_SETUP           1
 293 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 294
 295 /*
 296  * I2C
 297  */
 298 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 299 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 300 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 301 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 302 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 303 #define CONFIG_SYS_I2C_SLAVE            0x7F
 304 #define CONFIG_SYS_I2C_OFFSET           0x3000
 305
 306 /*
 307  * General PCI
 308  * Memory space is mapped 1-1, but I/O space must start from 0.
 309  */
 310 #define CONFIG_SYS_PCI_PHYS             0x80000000      /* 1G PCI TLB */
 311
 312 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 313 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 314 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 315 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 316 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 317 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 318
 319 #ifdef CONFIG_PCI2
 320 #define CONFIG_SYS_PCI2_MEM_BASE        0xa0000000
 321 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 322 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 323 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
 324 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
 325 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000      /* 1M */
 326 #endif
 327
 328 #ifdef CONFIG_PCIE1
 329 #define CONFIG_SYS_PCIE1_MEM_BASE       0xa0000000
 330 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BASE
 331 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 332 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 333 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe3000000
 334 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00100000      /*   1M */
 335 #endif
 336
 337 #ifdef CONFIG_RIO
 338 /*
 339  * RapidIO MMU
 340  */
 341 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
 342 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 512M */
 343 #endif
 344
 345 #if defined(CONFIG_PCI)
 346
 347 #define CONFIG_NET_MULTI
 348 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 349
 350 #undef CONFIG_EEPRO100
 351 #undef CONFIG_TULIP
 352
 353 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 354
 355 #endif  /* CONFIG_PCI */
 356
 357
 358 #if defined(CONFIG_TSEC_ENET)
 359
 360 #ifndef CONFIG_NET_MULTI
 361 #define CONFIG_NET_MULTI        1
 362 #endif
 363
 364 #define CONFIG_MII              1       /* MII PHY management */
 365 #define CONFIG_TSEC1    1
 366 #define CONFIG_TSEC1_NAME       "eTSEC0"
 367 #define CONFIG_TSEC2    1
 368 #define CONFIG_TSEC2_NAME       "eTSEC1"
 369 #undef CONFIG_MPC85XX_FEC
 370
 371 #define TSEC1_PHY_ADDR          0x19
 372 #define TSEC2_PHY_ADDR          0x1a
 373
 374 #define TSEC1_PHYIDX            0
 375 #define TSEC2_PHYIDX            0
 376
 377 #define TSEC1_FLAGS             TSEC_GIGABIT
 378 #define TSEC2_FLAGS             TSEC_GIGABIT
 379
 380 /* Options are: eTSEC[0-3] */
 381 #define CONFIG_ETHPRIME         "eTSEC0"
 382 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 383 #endif  /* CONFIG_TSEC_ENET */
 384
 385 /*
 386  * Environment
 387  */
 388 #define CONFIG_ENV_IS_IN_FLASH  1
 389 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 390 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 391 #define CONFIG_ENV_SIZE         0x2000
 392
 393 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 394 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 395
 396 /*
 397  * BOOTP options
 398  */
 399 #define CONFIG_BOOTP_BOOTFILESIZE
 400 #define CONFIG_BOOTP_BOOTPATH
 401 #define CONFIG_BOOTP_GATEWAY
 402 #define CONFIG_BOOTP_HOSTNAME
 403
 404
 405 /*
 406  * Command line configuration.
 407  */
 408 #include <config_cmd_default.h>
 409
 410 #define CONFIG_CMD_PING
 411 #define CONFIG_CMD_I2C
 412 #define CONFIG_CMD_MII
 413 #define CONFIG_CMD_ELF
 414
 415 #if defined(CONFIG_PCI)
 416     #define CONFIG_CMD_PCI
 417 #endif
 418
 419
 420 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 421
 422 /*
 423  * Miscellaneous configurable options
 424  */
 425 #define CONFIG_CMDLINE_EDITING                  /* undef to save memory */
 426 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 427 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 428 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 429 #if defined(CONFIG_CMD_KGDB)
 430 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 431 #else
 432 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 433 #endif
 434 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 435 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 436 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 437 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 438
 439 /*
 440  * For booting Linux, the board info and command line data
 441  * have to be in the first 8 MB of memory, since this is
 442  * the maximum mapped by the Linux kernel during initialization.
 443  */
 444 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 445
 446 /*
 447  * Internal Definitions
 448  *
 449  * Boot Flags
 450  */
 451 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 452 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 453
 454 #if defined(CONFIG_CMD_KGDB)
 455 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 456 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 457 #endif
 458
 459 /*
 460  * Environment Configuration
 461  */
 462
 463 /* The mac addresses for all ethernet interface */
 464 #if defined(CONFIG_TSEC_ENET)
 465 #define CONFIG_HAS_ETH0
 466 #define CONFIG_ETHADDR   02:E0:0C:00:00:FD
 467 #define CONFIG_HAS_ETH1
 468 #define CONFIG_ETH1ADDR  02:E0:0C:00:01:FD
 469 #endif
 470
 471 #define CONFIG_IPADDR    192.168.0.55
 472
 473 #define CONFIG_HOSTNAME  sbc8548
 474 #define CONFIG_ROOTPATH  /opt/eldk/ppc_85xx
 475 #define CONFIG_BOOTFILE  /uImage
 476 #define CONFIG_UBOOTPATH /u-boot.bin    /* TFTP server */
 477
 478 #define CONFIG_SERVERIP  192.168.0.2
 479 #define CONFIG_GATEWAYIP 192.168.0.1
 480 #define CONFIG_NETMASK   255.255.255.0
 481
 482 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 483
 484 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 485 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs*/
 486
 487 #define CONFIG_BAUDRATE 115200
 488
 489 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 490  "netdev=eth0\0"                                                \
 491  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 492  "tftpflash=tftpboot $loadaddr $uboot; "                        \
 493         "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 494         "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 495         "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 496         "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 497         "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 498  "consoledev=ttyS0\0"                           \
 499  "ramdiskaddr=2000000\0"                        \
 500  "ramdiskfile=uRamdisk\0"                       \
 501  "fdtaddr=c00000\0"                             \
 502  "fdtfile=sbc8548.dtb\0"
 503
 504 #define CONFIG_NFSBOOTCOMMAND                                           \
 505    "setenv bootargs root=/dev/nfs rw "                                  \
 506       "nfsroot=$serverip:$rootpath "                                    \
 507       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 508       "console=$consoledev,$baudrate $othbootargs;"                     \
 509    "tftp $loadaddr $bootfile;"                                          \
 510    "tftp $fdtaddr $fdtfile;"                                            \
 511    "bootm $loadaddr - $fdtaddr"
 512
 513
 514 #define CONFIG_RAMBOOTCOMMAND \
 515    "setenv bootargs root=/dev/ram rw "                                  \
 516       "console=$consoledev,$baudrate $othbootargs;"                     \
 517    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 518    "tftp $loadaddr $bootfile;"                                          \
 519    "tftp $fdtaddr $fdtfile;"                                            \
 520    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 521
 522 #define CONFIG_BOOTCOMMAND      CONFIG_RAMBOOTCOMMAND
 523
 524 #endif  /* __CONFIG_H */