include/configs/sbc8548.h

   1 /*
   2  * Copyright 2007 Wind River Systems <www.windriver.com>
   3  * Copyright 2007 Embedded Specialties, Inc.
   4  * Copyright 2004, 2007 Freescale Semiconductor.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * sbc8548 board configuration file
  27  *
  28  * Please refer to doc/README.sbc85xx for more info.
  29  *
  30  */
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 /* High Level Configuration Options */
  35 #define CONFIG_BOOKE            1       /* BOOKE */
  36 #define CONFIG_E500             1       /* BOOKE e500 family */
  37 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  38 #define CONFIG_MPC8548          1       /* MPC8548 specific */
  39 #define CONFIG_SBC8548          1       /* SBC8548 board specific */
  40
  41 #undef CONFIG_PCI               /* enable any pci type devices */
  42 #undef CONFIG_PCI1              /* PCI controller 1 */
  43 #undef CONFIG_PCIE1             /* PCIE controler 1 (slot 1) */
  44 #undef CONFIG_RIO
  45 #undef CONFIG_PCI2
  46 #undef CONFIG_FSL_PCI_INIT              /* Use common FSL init code */
  47
  48 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  49 #define CONFIG_ENV_OVERWRITE
  50
  51 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  52
  53 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  54
  55 #define CONFIG_SYS_CLK_FREQ     66000000 /* SBC8548 default SYSCLK */
  56
  57 /*
  58  * These can be toggled for performance analysis, otherwise use default.
  59  */
  60 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  61 #define CONFIG_BTB                      /* toggle branch predition */
  62 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
  63 #define CONFIG_CLEAR_LAW0               /* Clear LAW0 in cpu_init_r */
  64
  65 /*
  66  * Only possible on E500 Version 2 or newer cores.
  67  */
  68 #define CONFIG_ENABLE_36BIT_PHYS        1
  69
  70 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  71
  72 #undef  CONFIG_SYS_DRAM_TEST                    /* memory test, takes time */
  73 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  74 #define CONFIG_SYS_MEMTEST_END          0x00400000
  75
  76 /*
  77  * Base addresses -- Note these are effective addresses where the
  78  * actual resources get mapped (not physical addresses)
  79  */
  80 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  81 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  82 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
  83 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  84
  85 #define CONFIG_SYS_PCI1_ADDR    (CONFIG_SYS_CCSRBAR+0x8000)
  86 #define CONFIG_SYS_PCI2_ADDR    (CONFIG_SYS_CCSRBAR+0x9000)
  87 #define CONFIG_SYS_PCIE1_ADDR   (CONFIG_SYS_CCSRBAR+0xa000)
  88
  89 /* DDR Setup */
  90 #define CONFIG_FSL_DDR2
  91 #undef CONFIG_FSL_DDR_INTERACTIVE
  92 #undef CONFIG_SPD_EEPROM                /* Use SPD EEPROM for DDR setup */
  93 #undef CONFIG_DDR_SPD
  94 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  95
  96 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  97 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  98
  99 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 100 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 101 #define CONFIG_VERY_BIG_RAM
 102
 103 #define CONFIG_NUM_DDR_CONTROLLERS      1
 104 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 105 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 106
 107 /* I2C addresses of SPD EEPROMs */
 108 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 109
 110 /*
 111  * Make sure required options are set
 112  */
 113 #ifndef CONFIG_SPD_EEPROM
 114         #define CONFIG_SYS_SDRAM_SIZE   256             /* DDR is 256MB */
 115 #endif
 116
 117 #undef CONFIG_CLOCKS_IN_MHZ
 118
 119 /*
 120  * FLASH on the Local Bus
 121  * Two banks, one 8MB the other 64MB, using the CFI driver.
 122  * Boot from BR0/OR0 bank at 0xff80_0000
 123  * Alternate BR6/OR6 bank at 0xfb80_0000
 124  *
 125  * BR0:
 126  *    Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
 127  *    Port Size = 8 bits = BRx[19:20] = 01
 128  *    Use GPCM = BRx[24:26] = 000
 129  *    Valid = BRx[31] = 1
 130  *
 131  * 0    4    8    12   16   20   24   28
 132  * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801    BR0
 133  *
 134  * BR6:
 135  *    Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0
 136  *    Port Size = 32 bits = BRx[19:20] = 11
 137  *    Use GPCM = BRx[24:26] = 000
 138  *    Valid = BRx[31] = 1
 139  *
 140  * 0    4    8    12   16   20   24   28
 141  * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801    BR6
 142  *
 143  * OR0:
 144  *    Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
 145  *    XAM = OR0[17:18] = 11
 146  *    CSNT = OR0[20] = 1
 147  *    ACS = half cycle delay = OR0[21:22] = 11
 148  *    SCY = 6 = OR0[24:27] = 0110
 149  *    TRLX = use relaxed timing = OR0[29] = 1
 150  *    EAD = use external address latch delay = OR0[31] = 1
 151  *
 152  * 0    4    8    12   16   20   24   28
 153  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR0
 154  *
 155  * OR6:
 156  *    Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0
 157  *    XAM = OR6[17:18] = 11
 158  *    CSNT = OR6[20] = 1
 159  *    ACS = half cycle delay = OR6[21:22] = 11
 160  *    SCY = 6 = OR6[24:27] = 0110
 161  *    TRLX = use relaxed timing = OR6[29] = 1
 162  *    EAD = use external address latch delay = OR6[31] = 1
 163  *
 164  * 0    4    8    12   16   20   24   28
 165  * 1111 1000 0000 0000 0110 1110 0110 0101 = f8006e65    OR6
 166  */
 167
 168 #define CONFIG_SYS_BOOT_BLOCK           0xff800000      /* start of 8MB Flash */
 169 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_BOOT_BLOCK   /* start of FLASH 16M */
 170
 171 #define CONFIG_SYS_BR0_PRELIM           0xff800801
 172 #define CONFIG_SYS_BR6_PRELIM           0xfb801801
 173
 174 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 175 #define CONFIG_SYS_OR6_PRELIM           0xf8006e65
 176
 177 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
 178 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 179 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 180 #undef  CONFIG_SYS_FLASH_CHECKSUM
 181 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 182 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 183
 184 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 185
 186 #define CONFIG_FLASH_CFI_DRIVER
 187 #define CONFIG_SYS_FLASH_CFI
 188 #define CONFIG_SYS_FLASH_EMPTY_INFO
 189
 190 /* CS5 = Local bus peripherals controlled by the EPLD */
 191
 192 #define CONFIG_SYS_BR5_PRELIM           0xf8000801
 193 #define CONFIG_SYS_OR5_PRELIM           0xff006e65
 194 #define CONFIG_SYS_EPLD_BASE            0xf8000000
 195 #define CONFIG_SYS_LED_DISP_BASE        0xf8000000
 196 #define CONFIG_SYS_USER_SWITCHES_BASE   0xf8100000
 197 #define CONFIG_SYS_BD_REV               0xf8300000
 198 #define CONFIG_SYS_EEPROM_BASE          0xf8b00000
 199
 200 /*
 201  * SDRAM on the Local Bus
 202  */
 203 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 204 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 205
 206 /*
 207  * Base Register 3 and Option Register 3 configure SDRAM.
 208  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 209  *
 210  * For BR3, need:
 211  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 212  *    port-size = 32-bits = BR2[19:20] = 11
 213  *    no parity checking = BR2[21:22] = 00
 214  *    SDRAM for MSEL = BR2[24:26] = 011
 215  *    Valid = BR[31] = 1
 216  *
 217  * 0    4    8    12   16   20   24   28
 218  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 219  *
 220  */
 221
 222 #define CONFIG_SYS_BR3_PRELIM           0xf0001861
 223
 224 /*
 225  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 226  *
 227  * For OR3, need:
 228  *    64MB mask for AM, OR3[0:7] = 1111 1100
 229  *                 XAM, OR3[17:18] = 11
 230  *    10 columns OR3[19-21] = 011
 231  *    12 rows   OR3[23-25] = 011
 232  *    EAD set for extra time OR[31] = 0
 233  *
 234  * 0    4    8    12   16   20   24   28
 235  * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
 236  */
 237
 238 #define CONFIG_SYS_OR3_PRELIM           0xfc006cc0
 239
 240 #define CONFIG_SYS_LBC_LCRR             0x00000002    /* LB clock ratio reg */
 241 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 242 #define CONFIG_SYS_LBC_LSRT             0x20000000  /* LB sdram refresh timer */
 243 #define CONFIG_SYS_LBC_MRTPR            0x00000000  /* LB refresh timer prescal*/
 244
 245 /*
 246  * LSDMR masks
 247  */
 248 #define CONFIG_SYS_LBC_LSDMR_RFEN       (1 << (31 -  1))
 249 #define CONFIG_SYS_LBC_LSDMR_BSMA1516   (3 << (31 - 10))
 250 #define CONFIG_SYS_LBC_LSDMR_BSMA1617   (4 << (31 - 10))
 251 #define CONFIG_SYS_LBC_LSDMR_RFCR16     (7 << (31 - 16))
 252 #define CONFIG_SYS_LBC_LSDMR_PRETOACT7  (7 << (31 - 19))
 253 #define CONFIG_SYS_LBC_LSDMR_ACTTORW7   (7 << (31 - 22))
 254 #define CONFIG_SYS_LBC_LSDMR_ACTTORW6   (6 << (31 - 22))
 255 #define CONFIG_SYS_LBC_LSDMR_BL8        (1 << (31 - 23))
 256 #define CONFIG_SYS_LBC_LSDMR_WRC4       (0 << (31 - 27))
 257 #define CONFIG_SYS_LBC_LSDMR_CL3        (3 << (31 - 31))
 258
 259 #define CONFIG_SYS_LBC_LSDMR_OP_NORMAL  (0 << (31 - 4))
 260 #define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH  (1 << (31 - 4))
 261 #define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH  (2 << (31 - 4))
 262 #define CONFIG_SYS_LBC_LSDMR_OP_MRW     (3 << (31 - 4))
 263 #define CONFIG_SYS_LBC_LSDMR_OP_PRECH   (4 << (31 - 4))
 264 #define CONFIG_SYS_LBC_LSDMR_OP_PCHALL  (5 << (31 - 4))
 265 #define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK  (6 << (31 - 4))
 266 #define CONFIG_SYS_LBC_LSDMR_OP_RWINV   (7 << (31 - 4))
 267
 268 /*
 269  * Common settings for all Local Bus SDRAM commands.
 270  * At run time, either BSMA1516 (for CPU 1.1)
 271  *                  or BSMA1617 (for CPU 1.0) (old)
 272  * is OR'ed in too.
 273  */
 274 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( CONFIG_SYS_LBC_LSDMR_RFCR16           \
 275                                 | CONFIG_SYS_LBC_LSDMR_PRETOACT7        \
 276                                 | CONFIG_SYS_LBC_LSDMR_ACTTORW7 \
 277                                 | CONFIG_SYS_LBC_LSDMR_BL8              \
 278                                 | CONFIG_SYS_LBC_LSDMR_WRC4             \
 279                                 | CONFIG_SYS_LBC_LSDMR_CL3              \
 280                                 | CONFIG_SYS_LBC_LSDMR_RFEN             \
 281                                 )
 282
 283 #define CONFIG_L1_INIT_RAM
 284 #define CONFIG_SYS_INIT_RAM_LOCK        1
 285 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 286 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End of used area in RAM */
 287
 288 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000      /* relocate boot L2SRAM */
 289
 290 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 291 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 292 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 293
 294 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 295 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 296
 297 /* Serial Port */
 298 #define CONFIG_CONS_INDEX       1
 299 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 300 #define CONFIG_SYS_NS16550
 301 #define CONFIG_SYS_NS16550_SERIAL
 302 #define CONFIG_SYS_NS16550_REG_SIZE     1
 303 #define CONFIG_SYS_NS16550_CLK          400000000 /* get_bus_freq(0) */
 304
 305 #define CONFIG_SYS_BAUDRATE_TABLE \
 306         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 307
 308 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 309 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 310
 311 /* Use the HUSH parser */
 312 #define CONFIG_SYS_HUSH_PARSER
 313 #ifdef  CONFIG_SYS_HUSH_PARSER
 314 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 315 #endif
 316
 317 /* pass open firmware flat tree */
 318 #define CONFIG_OF_LIBFDT                1
 319 #define CONFIG_OF_BOARD_SETUP           1
 320 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 321
 322 /*
 323  * I2C
 324  */
 325 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 326 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 327 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 328 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 329 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 330 #define CONFIG_SYS_I2C_SLAVE            0x7F
 331 #define CONFIG_SYS_I2C_OFFSET           0x3000
 332
 333 /*
 334  * General PCI
 335  * Memory space is mapped 1-1, but I/O space must start from 0.
 336  */
 337 #define CONFIG_SYS_PCI_PHYS             0x80000000      /* 1G PCI TLB */
 338
 339 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 340 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 341 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 342 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 343 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 344 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 345
 346 #ifdef CONFIG_PCI2
 347 #define CONFIG_SYS_PCI2_MEM_BASE        0xa0000000
 348 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 349 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 350 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
 351 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
 352 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000      /* 1M */
 353 #endif
 354
 355 #ifdef CONFIG_PCIE1
 356 #define CONFIG_SYS_PCIE1_MEM_BASE       0xa0000000
 357 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BASE
 358 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 359 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 360 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe3000000
 361 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00100000      /*   1M */
 362 #endif
 363
 364 #ifdef CONFIG_RIO
 365 /*
 366  * RapidIO MMU
 367  */
 368 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
 369 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 512M */
 370 #endif
 371
 372 #ifdef CONFIG_LEGACY
 373 #define BRIDGE_ID 17
 374 #define VIA_ID 2
 375 #else
 376 #define BRIDGE_ID 28
 377 #define VIA_ID 4
 378 #endif
 379
 380 #if defined(CONFIG_PCI)
 381
 382 #define CONFIG_NET_MULTI
 383 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 384
 385 #undef CONFIG_EEPRO100
 386 #undef CONFIG_TULIP
 387
 388 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 389
 390 /* PCI view of System Memory */
 391 #define CONFIG_SYS_PCI_MEMORY_BUS       0x00000000
 392 #define CONFIG_SYS_PCI_MEMORY_PHYS      0x00000000
 393 #define CONFIG_SYS_PCI_MEMORY_SIZE      0x80000000
 394
 395 #endif  /* CONFIG_PCI */
 396
 397
 398 #if defined(CONFIG_TSEC_ENET)
 399
 400 #ifndef CONFIG_NET_MULTI
 401 #define CONFIG_NET_MULTI        1
 402 #endif
 403
 404 #define CONFIG_MII              1       /* MII PHY management */
 405 #define CONFIG_TSEC1    1
 406 #define CONFIG_TSEC1_NAME       "eTSEC0"
 407 #define CONFIG_TSEC2    1
 408 #define CONFIG_TSEC2_NAME       "eTSEC1"
 409 #define CONFIG_TSEC3    1
 410 #define CONFIG_TSEC3_NAME       "eTSEC2"
 411 #define CONFIG_TSEC4
 412 #define CONFIG_TSEC4_NAME       "eTSEC3"
 413 #undef CONFIG_MPC85XX_FEC
 414
 415 #define TSEC1_PHY_ADDR          0
 416 #define TSEC2_PHY_ADDR          1
 417 #define TSEC3_PHY_ADDR          2
 418 #define TSEC4_PHY_ADDR          3
 419
 420 #define TSEC1_PHYIDX            0
 421 #define TSEC2_PHYIDX            0
 422 #define TSEC3_PHYIDX            0
 423 #define TSEC4_PHYIDX            0
 424 #define TSEC1_FLAGS             TSEC_GIGABIT
 425 #define TSEC2_FLAGS             TSEC_GIGABIT
 426 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 427 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 428
 429 /* Options are: eTSEC[0-3] */
 430 #define CONFIG_ETHPRIME         "eTSEC0"
 431 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 432 #endif  /* CONFIG_TSEC_ENET */
 433
 434 /*
 435  * Environment
 436  */
 437 #define CONFIG_ENV_IS_IN_FLASH  1
 438 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 439 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 440 #define CONFIG_ENV_SIZE         0x2000
 441
 442 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 443 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 444
 445 /*
 446  * BOOTP options
 447  */
 448 #define CONFIG_BOOTP_BOOTFILESIZE
 449 #define CONFIG_BOOTP_BOOTPATH
 450 #define CONFIG_BOOTP_GATEWAY
 451 #define CONFIG_BOOTP_HOSTNAME
 452
 453
 454 /*
 455  * Command line configuration.
 456  */
 457 #include <config_cmd_default.h>
 458
 459 #define CONFIG_CMD_PING
 460 #define CONFIG_CMD_I2C
 461 #define CONFIG_CMD_MII
 462 #define CONFIG_CMD_ELF
 463
 464 #if defined(CONFIG_PCI)
 465     #define CONFIG_CMD_PCI
 466 #endif
 467
 468
 469 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 470
 471 /*
 472  * Miscellaneous configurable options
 473  */
 474 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 475 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 476 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 477 #if defined(CONFIG_CMD_KGDB)
 478 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 479 #else
 480 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 481 #endif
 482 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 483 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 484 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 485 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 486
 487 /*
 488  * For booting Linux, the board info and command line data
 489  * have to be in the first 8 MB of memory, since this is
 490  * the maximum mapped by the Linux kernel during initialization.
 491  */
 492 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 493
 494 /*
 495  * Internal Definitions
 496  *
 497  * Boot Flags
 498  */
 499 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 500 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 501
 502 #if defined(CONFIG_CMD_KGDB)
 503 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 504 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 505 #endif
 506
 507 /*
 508  * Environment Configuration
 509  */
 510
 511 /* The mac addresses for all ethernet interface */
 512 #if defined(CONFIG_TSEC_ENET)
 513 #define CONFIG_HAS_ETH0
 514 #define CONFIG_ETHADDR   02:E0:0C:00:00:FD
 515 #define CONFIG_HAS_ETH1
 516 #define CONFIG_ETH1ADDR  02:E0:0C:00:01:FD
 517 #define CONFIG_HAS_ETH2
 518 #define CONFIG_ETH2ADDR  02:E0:0C:00:02:FD
 519 #define CONFIG_HAS_ETH3
 520 #define CONFIG_ETH3ADDR  02:E0:0C:00:03:FD
 521 #endif
 522
 523 #define CONFIG_IPADDR    192.168.0.55
 524
 525 #define CONFIG_HOSTNAME  sbc8548
 526 #define CONFIG_ROOTPATH  /opt/eldk/ppc_85xx
 527 #define CONFIG_BOOTFILE  /uImage
 528 #define CONFIG_UBOOTPATH /u-boot.bin    /* TFTP server */
 529
 530 #define CONFIG_SERVERIP  192.168.0.2
 531 #define CONFIG_GATEWAYIP 192.168.0.1
 532 #define CONFIG_NETMASK   255.255.255.0
 533
 534 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 535
 536 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 537 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs*/
 538
 539 #define CONFIG_BAUDRATE 115200
 540
 541 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 542  "netdev=eth0\0"                                                \
 543  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 544  "tftpflash=tftpboot $loadaddr $uboot; "                        \
 545         "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 546         "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 547         "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 548         "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 549         "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 550  "consoledev=ttyS0\0"                           \
 551  "ramdiskaddr=2000000\0"                        \
 552  "ramdiskfile=uRamdisk\0"                       \
 553  "fdtaddr=c00000\0"                             \
 554  "fdtfile=sbc8548.dtb\0"
 555
 556 #define CONFIG_NFSBOOTCOMMAND                                           \
 557    "setenv bootargs root=/dev/nfs rw "                                  \
 558       "nfsroot=$serverip:$rootpath "                                    \
 559       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 560       "console=$consoledev,$baudrate $othbootargs;"                     \
 561    "tftp $loadaddr $bootfile;"                                          \
 562    "tftp $fdtaddr $fdtfile;"                                            \
 563    "bootm $loadaddr - $fdtaddr"
 564
 565
 566 #define CONFIG_RAMBOOTCOMMAND \
 567    "setenv bootargs root=/dev/ram rw "                                  \
 568       "console=$consoledev,$baudrate $othbootargs;"                     \
 569    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 570    "tftp $loadaddr $bootfile;"                                          \
 571    "tftp $fdtaddr $fdtfile;"                                            \
 572    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 573
 574 #define CONFIG_BOOTCOMMAND      CONFIG_RAMBOOTCOMMAND
 575
 576 #endif  /* __CONFIG_H */