include/configs/sbc8548.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2007,2009 Wind River Systems <www.windriver.com>
   4  * Copyright 2007 Embedded Specialties, Inc.
   5  * Copyright 2004, 2007 Freescale Semiconductor.
   6  */
   7
   8 /*
   9  * sbc8548 board configuration file
  10  * Please refer to doc/README.sbc8548 for more info.
  11  */
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * Top level Makefile configuration choices
  17  */
  18 #ifdef CONFIG_PCI
  19 #define CONFIG_PCI_INDIRECT_BRIDGE
  20 #define CONFIG_PCI1
  21 #endif
  22
  23 #ifdef CONFIG_66
  24 #define CONFIG_SYS_CLK_DIV 1
  25 #endif
  26
  27 #ifdef CONFIG_33
  28 #define CONFIG_SYS_CLK_DIV 2
  29 #endif
  30
  31 #ifdef CONFIG_PCIE
  32 #define CONFIG_PCIE1
  33 #endif
  34
  35 /*
  36  * High Level Configuration Options
  37  */
  38
  39 /*
  40  * If you want to boot from the SODIMM flash, instead of the soldered
  41  * on flash, set this, and change JP12, SW2:8 accordingly.
  42  */
  43 #undef CONFIG_SYS_ALT_BOOT
  44
  45 #undef CONFIG_RIO
  46
  47 #ifdef CONFIG_PCI
  48 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  49 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  50 #endif
  51 #ifdef CONFIG_PCIE1
  52 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  53 #endif
  54
  55 #define CONFIG_ENV_OVERWRITE
  56
  57 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  58
  59 /*
  60  * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
  61  */
  62 #ifndef CONFIG_SYS_CLK_DIV
  63 #define CONFIG_SYS_CLK_DIV      1       /* 2, if 33MHz PCI card installed */
  64 #endif
  65 #define CONFIG_SYS_CLK_FREQ     (66000000 / CONFIG_SYS_CLK_DIV)
  66
  67 /*
  68  * These can be toggled for performance analysis, otherwise use default.
  69  */
  70 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  71 #define CONFIG_BTB                      /* toggle branch predition */
  72
  73 /*
  74  * Only possible on E500 Version 2 or newer cores.
  75  */
  76 #define CONFIG_ENABLE_36BIT_PHYS        1
  77
  78 #undef  CONFIG_SYS_DRAM_TEST                    /* memory test, takes time */
  79 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  80 #define CONFIG_SYS_MEMTEST_END          0x00400000
  81
  82 #define CONFIG_SYS_CCSRBAR              0xe0000000
  83 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  84
  85 /* DDR Setup */
  86 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  87 /*
  88  * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
  89  * to collide, meaning you couldn't reliably read either. So
  90  * physically remove the LBC PC100 SDRAM module from the board
  91  * before enabling the two SPD options below, or check that you
  92  * have the hardware fix on your board via "i2c probe" and looking
  93  * for a device at 0x53.
  94  */
  95 #undef CONFIG_SPD_EEPROM                /* Use SPD EEPROM for DDR setup */
  96 #undef CONFIG_DDR_SPD
  97
  98 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  99 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 100
 101 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 102 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 103 #define CONFIG_VERY_BIG_RAM
 104
 105 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 106 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 107
 108 /*
 109  * The hardware fix for the I2C address collision puts the DDR
 110  * SPD at 0x53, but if we are running on an older board w/o the
 111  * fix, it will still be at 0x51.  We check 0x53 1st.
 112  */
 113 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 114 #define ALT_SPD_EEPROM_ADDRESS  0x53    /* CTLR 0 DIMM 0 */
 115
 116 /*
 117  * Make sure required options are set
 118  */
 119 #ifndef CONFIG_SPD_EEPROM
 120         #define CONFIG_SYS_SDRAM_SIZE   256             /* DDR is 256MB */
 121         #define CONFIG_SYS_DDR_CONTROL  0xc300c000
 122 #endif
 123
 124 #undef CONFIG_CLOCKS_IN_MHZ
 125
 126 /*
 127  * FLASH on the Local Bus
 128  * Two banks, one 8MB the other 64MB, using the CFI driver.
 129  * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have
 130  * CS0 the 8MB boot flash, and CS6 the 64MB flash.
 131  *
 132  *      Default:
 133  *      ec00_0000       efff_ffff       64MB SODIMM
 134  *      ff80_0000       ffff_ffff       8MB soldered flash
 135  *
 136  *      Alternate:
 137  *      ef80_0000       efff_ffff       8MB soldered flash
 138  *      fc00_0000       ffff_ffff       64MB SODIMM
 139  *
 140  * BR0_8M:
 141  *    Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
 142  *    Port Size = 8 bits = BRx[19:20] = 01
 143  *    Use GPCM = BRx[24:26] = 000
 144  *    Valid = BRx[31] = 1
 145  *
 146  * BR0_64M:
 147  *    Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
 148  *    Port Size = 32 bits = BRx[19:20] = 11
 149  *
 150  * 0    4    8    12   16   20   24   28
 151  * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801    BR0_8M
 152  * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801    BR0_64M
 153  */
 154 #define CONFIG_SYS_BR0_8M       0xff800801
 155 #define CONFIG_SYS_BR0_64M      0xfc001801
 156
 157 /*
 158  * BR6_8M:
 159  *    Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
 160  *    Port Size = 8 bits = BRx[19:20] = 01
 161  *    Use GPCM = BRx[24:26] = 000
 162  *    Valid = BRx[31] = 1
 163
 164  * BR6_64M:
 165  *    Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
 166  *    Port Size = 32 bits = BRx[19:20] = 11
 167  *
 168  * 0    4    8    12   16   20   24   28
 169  * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801    BR6_8M
 170  * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801    BR6_64M
 171  */
 172 #define CONFIG_SYS_BR6_8M       0xef800801
 173 #define CONFIG_SYS_BR6_64M      0xec001801
 174
 175 /*
 176  * OR0_8M:
 177  *    Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
 178  *    XAM = OR0[17:18] = 11
 179  *    CSNT = OR0[20] = 1
 180  *    ACS = half cycle delay = OR0[21:22] = 11
 181  *    SCY = 6 = OR0[24:27] = 0110
 182  *    TRLX = use relaxed timing = OR0[29] = 1
 183  *    EAD = use external address latch delay = OR0[31] = 1
 184  *
 185  * OR0_64M:
 186  *    Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
 187  *
 188  *
 189  * 0    4    8    12   16   20   24   28
 190  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR0_8M
 191  * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR0_64M
 192  */
 193 #define CONFIG_SYS_OR0_8M       0xff806e65
 194 #define CONFIG_SYS_OR0_64M      0xfc006e65
 195
 196 /*
 197  * OR6_8M:
 198  *    Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
 199  *    XAM = OR6[17:18] = 11
 200  *    CSNT = OR6[20] = 1
 201  *    ACS = half cycle delay = OR6[21:22] = 11
 202  *    SCY = 6 = OR6[24:27] = 0110
 203  *    TRLX = use relaxed timing = OR6[29] = 1
 204  *    EAD = use external address latch delay = OR6[31] = 1
 205  *
 206  * OR6_64M:
 207  *    Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
 208  *
 209  * 0    4    8    12   16   20   24   28
 210  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR6_8M
 211  * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR6_64M
 212  */
 213 #define CONFIG_SYS_OR6_8M       0xff806e65
 214 #define CONFIG_SYS_OR6_64M      0xfc006e65
 215
 216 #ifndef CONFIG_SYS_ALT_BOOT             /* JP12 in default position */
 217 #define CONFIG_SYS_BOOT_BLOCK           0xff800000      /* start of 8MB Flash */
 218 #define CONFIG_SYS_ALT_FLASH            0xec000000      /* 64MB "user" flash */
 219
 220 #define CONFIG_SYS_BR0_PRELIM           CONFIG_SYS_BR0_8M
 221 #define CONFIG_SYS_OR0_PRELIM           CONFIG_SYS_OR0_8M
 222
 223 #define CONFIG_SYS_BR6_PRELIM           CONFIG_SYS_BR6_64M
 224 #define CONFIG_SYS_OR6_PRELIM           CONFIG_SYS_OR6_64M
 225 #else                                   /* JP12 in alternate position */
 226 #define CONFIG_SYS_BOOT_BLOCK           0xfc000000      /* start 64MB Flash */
 227 #define CONFIG_SYS_ALT_FLASH            0xef800000      /* 8MB soldered flash */
 228
 229 #define CONFIG_SYS_BR0_PRELIM           CONFIG_SYS_BR0_64M
 230 #define CONFIG_SYS_OR0_PRELIM           CONFIG_SYS_OR0_64M
 231
 232 #define CONFIG_SYS_BR6_PRELIM           CONFIG_SYS_BR6_8M
 233 #define CONFIG_SYS_OR6_PRELIM           CONFIG_SYS_OR6_8M
 234 #endif
 235
 236 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_BOOT_BLOCK
 237 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, \
 238                                          CONFIG_SYS_ALT_FLASH}
 239 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 240 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* sectors per device */
 241 #undef  CONFIG_SYS_FLASH_CHECKSUM
 242 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 243 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 244
 245 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 246
 247 #define CONFIG_SYS_FLASH_EMPTY_INFO
 248
 249 /* CS5 = Local bus peripherals controlled by the EPLD */
 250
 251 #define CONFIG_SYS_BR5_PRELIM           0xf8000801
 252 #define CONFIG_SYS_OR5_PRELIM           0xff006e65
 253 #define CONFIG_SYS_EPLD_BASE            0xf8000000
 254 #define CONFIG_SYS_LED_DISP_BASE        0xf8000000
 255 #define CONFIG_SYS_USER_SWITCHES_BASE   0xf8100000
 256 #define CONFIG_SYS_BD_REV               0xf8300000
 257 #define CONFIG_SYS_EEPROM_BASE          0xf8b00000
 258
 259 /*
 260  * SDRAM on the Local Bus (CS3 and CS4)
 261  * Note that most boards have a hardware errata where both the
 262  * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
 263  * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
 264  * A hardware workaround is also available, see README.sbc8548 file.
 265  */
 266 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 267 #define CONFIG_SYS_LBC_SDRAM_SIZE       128             /* LBC SDRAM is 128MB */
 268
 269 /*
 270  * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
 271  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 272  *
 273  * For BR3, need:
 274  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 275  *    port-size = 32-bits = BR2[19:20] = 11
 276  *    no parity checking = BR2[21:22] = 00
 277  *    SDRAM for MSEL = BR2[24:26] = 011
 278  *    Valid = BR[31] = 1
 279  *
 280  * 0    4    8    12   16   20   24   28
 281  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 282  *
 283  */
 284
 285 #define CONFIG_SYS_BR3_PRELIM           0xf0001861
 286
 287 /*
 288  * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 289  *
 290  * For OR3, need:
 291  *    64MB mask for AM, OR3[0:7] = 1111 1100
 292  *                 XAM, OR3[17:18] = 11
 293  *    10 columns OR3[19-21] = 011
 294  *    12 rows   OR3[23-25] = 011
 295  *    EAD set for extra time OR[31] = 0
 296  *
 297  * 0    4    8    12   16   20   24   28
 298  * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
 299  */
 300
 301 #define CONFIG_SYS_OR3_PRELIM           0xfc006cc0
 302
 303 /*
 304  * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
 305  * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
 306  *
 307  * For BR4, need:
 308  *    Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
 309  *    port-size = 32-bits = BR2[19:20] = 11
 310  *    no parity checking = BR2[21:22] = 00
 311  *    SDRAM for MSEL = BR2[24:26] = 011
 312  *    Valid = BR[31] = 1
 313  *
 314  * 0    4    8    12   16   20   24   28
 315  * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
 316  *
 317  */
 318
 319 #define CONFIG_SYS_BR4_PRELIM           0xf4001861
 320
 321 /*
 322  * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 323  *
 324  * For OR4, need:
 325  *    64MB mask for AM, OR3[0:7] = 1111 1100
 326  *                 XAM, OR3[17:18] = 11
 327  *    10 columns OR3[19-21] = 011
 328  *    12 rows   OR3[23-25] = 011
 329  *    EAD set for extra time OR[31] = 0
 330  *
 331  * 0    4    8    12   16   20   24   28
 332  * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
 333  */
 334
 335 #define CONFIG_SYS_OR4_PRELIM           0xfc006cc0
 336
 337 #define CONFIG_SYS_LBC_LCRR             0x00000002    /* LB clock ratio reg */
 338 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 339 #define CONFIG_SYS_LBC_LSRT             0x20000000  /* LB sdram refresh timer */
 340 #define CONFIG_SYS_LBC_MRTPR            0x00000000  /* LB refresh timer prescal*/
 341
 342 /*
 343  * Common settings for all Local Bus SDRAM commands.
 344  */
 345 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 346                                 | LSDMR_BSMA1516        \
 347                                 | LSDMR_PRETOACT3       \
 348                                 | LSDMR_ACTTORW3        \
 349                                 | LSDMR_BUFCMD          \
 350                                 | LSDMR_BL8             \
 351                                 | LSDMR_WRC2            \
 352                                 | LSDMR_CL3             \
 353                                 )
 354
 355 #define CONFIG_SYS_LBC_LSDMR_PCHALL     \
 356          (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 357 #define CONFIG_SYS_LBC_LSDMR_ARFRSH     \
 358          (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 359 #define CONFIG_SYS_LBC_LSDMR_MRW        \
 360          (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 361 #define CONFIG_SYS_LBC_LSDMR_RFEN       \
 362          (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN)
 363
 364 #define CONFIG_SYS_INIT_RAM_LOCK        1
 365 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 366 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 367
 368 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000      /* relocate boot L2SRAM */
 369
 370 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 371 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 372
 373 /*
 374  * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
 375  * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total).  For SODIMM
 376  * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
 377  * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total).  This dynamically sets the right
 378  * thing for MONITOR_LEN in both cases.
 379  */
 380 #define CONFIG_SYS_MONITOR_LEN          (~CONFIG_SYS_TEXT_BASE + 1)
 381 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024) /* Reserved for malloc */
 382
 383 /* Serial Port */
 384 #define CONFIG_SYS_NS16550_SERIAL
 385 #define CONFIG_SYS_NS16550_REG_SIZE     1
 386 #define CONFIG_SYS_NS16550_CLK          (400000000 / CONFIG_SYS_CLK_DIV)
 387
 388 #define CONFIG_SYS_BAUDRATE_TABLE \
 389         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 390
 391 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 392 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 393
 394 /*
 395  * I2C
 396  */
 397 #define CONFIG_SYS_I2C
 398 #define CONFIG_SYS_I2C_FSL
 399 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 400 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 401 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 402 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 403
 404 /*
 405  * General PCI
 406  * Memory space is mapped 1-1, but I/O space must start from 0.
 407  */
 408 #define CONFIG_SYS_PCI_VIRT             0x80000000      /* 1G PCI TLB */
 409 #define CONFIG_SYS_PCI_PHYS             0x80000000      /* 1G PCI TLB */
 410
 411 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 412 #define CONFIG_SYS_PCI1_MEM_BUS         0x80000000
 413 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 414 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 415 #define CONFIG_SYS_PCI1_IO_VIRT         0xe2000000
 416 #define CONFIG_SYS_PCI1_IO_BUS          0x00000000
 417 #define CONFIG_SYS_PCI1_IO_PHYS         0xe2000000
 418 #define CONFIG_SYS_PCI1_IO_SIZE         0x00800000      /* 8M */
 419
 420 #ifdef CONFIG_PCIE1
 421 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 422 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 423 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 424 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 425 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe2800000
 426 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 427 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe2800000
 428 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 429 #endif
 430
 431 #ifdef CONFIG_RIO
 432 /*
 433  * RapidIO MMU
 434  */
 435 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
 436 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 512M */
 437 #endif
 438
 439 #if defined(CONFIG_PCI)
 440 #undef CONFIG_EEPRO100
 441 #undef CONFIG_TULIP
 442
 443 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 444
 445 #endif  /* CONFIG_PCI */
 446
 447 #if defined(CONFIG_TSEC_ENET)
 448
 449 #define CONFIG_TSEC1    1
 450 #define CONFIG_TSEC1_NAME       "eTSEC0"
 451 #define CONFIG_TSEC2    1
 452 #define CONFIG_TSEC2_NAME       "eTSEC1"
 453 #undef CONFIG_MPC85XX_FEC
 454
 455 #define TSEC1_PHY_ADDR          0x19
 456 #define TSEC2_PHY_ADDR          0x1a
 457
 458 #define TSEC1_PHYIDX            0
 459 #define TSEC2_PHYIDX            0
 460
 461 #define TSEC1_FLAGS             TSEC_GIGABIT
 462 #define TSEC2_FLAGS             TSEC_GIGABIT
 463
 464 /* Options are: eTSEC[0-3] */
 465 #define CONFIG_ETHPRIME         "eTSEC0"
 466 #endif  /* CONFIG_TSEC_ENET */
 467
 468 /*
 469  * Environment
 470  */
 471 #define CONFIG_ENV_SIZE         0x2000
 472 #if CONFIG_SYS_TEXT_BASE == 0xfff00000  /* Boot from 64MB SODIMM */
 473 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x80000)
 474 #define CONFIG_ENV_SECT_SIZE    0x80000 /* 512K(one sector) for env */
 475 #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000        /* Boot from 8MB soldered flash */
 476 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 477 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 478 #else
 479 #warning undefined environment size/location.
 480 #endif
 481
 482 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 483 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 484
 485 /*
 486  * BOOTP options
 487  */
 488 #define CONFIG_BOOTP_BOOTFILESIZE
 489
 490 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 491
 492 /*
 493  * Miscellaneous configurable options
 494  */
 495 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 496
 497 /*
 498  * For booting Linux, the board info and command line data
 499  * have to be in the first 8 MB of memory, since this is
 500  * the maximum mapped by the Linux kernel during initialization.
 501  */
 502 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 503
 504 #if defined(CONFIG_CMD_KGDB)
 505 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 506 #endif
 507
 508 /*
 509  * Environment Configuration
 510  */
 511 #if defined(CONFIG_TSEC_ENET)
 512 #define CONFIG_HAS_ETH0
 513 #define CONFIG_HAS_ETH1
 514 #endif
 515
 516 #define CONFIG_IPADDR    192.168.0.55
 517
 518 #define CONFIG_HOSTNAME  "sbc8548"
 519 #define CONFIG_ROOTPATH  "/opt/eldk/ppc_85xx"
 520 #define CONFIG_BOOTFILE  "/uImage"
 521 #define CONFIG_UBOOTPATH /u-boot.bin    /* TFTP server */
 522
 523 #define CONFIG_SERVERIP  192.168.0.2
 524 #define CONFIG_GATEWAYIP 192.168.0.1
 525 #define CONFIG_NETMASK   255.255.255.0
 526
 527 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 528
 529 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 530 "netdev=eth0\0"                                         \
 531 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                             \
 532 "tftpflash=tftpboot $loadaddr $uboot; "                 \
 533         "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 534         "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "      \
 535         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
 536         "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 537         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
 538 "consoledev=ttyS0\0"                            \
 539 "ramdiskaddr=2000000\0"                 \
 540 "ramdiskfile=uRamdisk\0"                        \
 541 "fdtaddr=1e00000\0"                             \
 542 "fdtfile=sbc8548.dtb\0"
 543
 544 #define CONFIG_NFSBOOTCOMMAND                                           \
 545    "setenv bootargs root=/dev/nfs rw "                                  \
 546       "nfsroot=$serverip:$rootpath "                                    \
 547       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 548       "console=$consoledev,$baudrate $othbootargs;"                     \
 549    "tftp $loadaddr $bootfile;"                                          \
 550    "tftp $fdtaddr $fdtfile;"                                            \
 551    "bootm $loadaddr - $fdtaddr"
 552
 553 #define CONFIG_RAMBOOTCOMMAND \
 554    "setenv bootargs root=/dev/ram rw "                                  \
 555       "console=$consoledev,$baudrate $othbootargs;"                     \
 556    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 557    "tftp $loadaddr $bootfile;"                                          \
 558    "tftp $fdtaddr $fdtfile;"                                            \
 559    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 560
 561 #define CONFIG_BOOTCOMMAND      CONFIG_RAMBOOTCOMMAND
 562
 563 #endif  /* __CONFIG_H */