include/configs/sbc8548.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2007,2009 Wind River Systems <www.windriver.com>
   4  * Copyright 2007 Embedded Specialties, Inc.
   5  * Copyright 2004, 2007 Freescale Semiconductor.
   6  */
   7
   8 /*
   9  * sbc8548 board configuration file
  10  * Please refer to doc/README.sbc8548 for more info.
  11  */
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * Top level Makefile configuration choices
  17  */
  18 #ifdef CONFIG_PCI
  19 #define CONFIG_PCI_INDIRECT_BRIDGE
  20 #define CONFIG_PCI1
  21 #endif
  22
  23 #ifdef CONFIG_66
  24 #define CONFIG_SYS_CLK_DIV 1
  25 #endif
  26
  27 #ifdef CONFIG_33
  28 #define CONFIG_SYS_CLK_DIV 2
  29 #endif
  30
  31 #ifdef CONFIG_PCIE
  32 #define CONFIG_PCIE1
  33 #endif
  34
  35 /*
  36  * High Level Configuration Options
  37  */
  38
  39 /*
  40  * If you want to boot from the SODIMM flash, instead of the soldered
  41  * on flash, set this, and change JP12, SW2:8 accordingly.
  42  */
  43 #undef CONFIG_SYS_ALT_BOOT
  44
  45 #undef CONFIG_RIO
  46
  47 #ifdef CONFIG_PCI
  48 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  49 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  50 #endif
  51
  52 #define CONFIG_ENV_OVERWRITE
  53
  54 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  55
  56 /*
  57  * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
  58  */
  59 #ifndef CONFIG_SYS_CLK_DIV
  60 #define CONFIG_SYS_CLK_DIV      1       /* 2, if 33MHz PCI card installed */
  61 #endif
  62 #define CONFIG_SYS_CLK_FREQ     (66000000 / CONFIG_SYS_CLK_DIV)
  63
  64 /*
  65  * These can be toggled for performance analysis, otherwise use default.
  66  */
  67 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  68 #define CONFIG_BTB                      /* toggle branch predition */
  69
  70 /*
  71  * Only possible on E500 Version 2 or newer cores.
  72  */
  73 #define CONFIG_ENABLE_36BIT_PHYS        1
  74
  75 #undef  CONFIG_SYS_DRAM_TEST                    /* memory test, takes time */
  76 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  77 #define CONFIG_SYS_MEMTEST_END          0x00400000
  78
  79 #define CONFIG_SYS_CCSRBAR              0xe0000000
  80 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  81
  82 /* DDR Setup */
  83 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  84 /*
  85  * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
  86  * to collide, meaning you couldn't reliably read either. So
  87  * physically remove the LBC PC100 SDRAM module from the board
  88  * before enabling the two SPD options below, or check that you
  89  * have the hardware fix on your board via "i2c probe" and looking
  90  * for a device at 0x53.
  91  */
  92 #undef CONFIG_SPD_EEPROM                /* Use SPD EEPROM for DDR setup */
  93 #undef CONFIG_DDR_SPD
  94
  95 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  96 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  97
  98 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  99 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 100 #define CONFIG_VERY_BIG_RAM
 101
 102 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 103 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 104
 105 /*
 106  * The hardware fix for the I2C address collision puts the DDR
 107  * SPD at 0x53, but if we are running on an older board w/o the
 108  * fix, it will still be at 0x51.  We check 0x53 1st.
 109  */
 110 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 111 #define ALT_SPD_EEPROM_ADDRESS  0x53    /* CTLR 0 DIMM 0 */
 112
 113 /*
 114  * Make sure required options are set
 115  */
 116 #ifndef CONFIG_SPD_EEPROM
 117         #define CONFIG_SYS_SDRAM_SIZE   256             /* DDR is 256MB */
 118         #define CONFIG_SYS_DDR_CONTROL  0xc300c000
 119 #endif
 120
 121 #undef CONFIG_CLOCKS_IN_MHZ
 122
 123 /*
 124  * FLASH on the Local Bus
 125  * Two banks, one 8MB the other 64MB, using the CFI driver.
 126  * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have
 127  * CS0 the 8MB boot flash, and CS6 the 64MB flash.
 128  *
 129  *      Default:
 130  *      ec00_0000       efff_ffff       64MB SODIMM
 131  *      ff80_0000       ffff_ffff       8MB soldered flash
 132  *
 133  *      Alternate:
 134  *      ef80_0000       efff_ffff       8MB soldered flash
 135  *      fc00_0000       ffff_ffff       64MB SODIMM
 136  *
 137  * BR0_8M:
 138  *    Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
 139  *    Port Size = 8 bits = BRx[19:20] = 01
 140  *    Use GPCM = BRx[24:26] = 000
 141  *    Valid = BRx[31] = 1
 142  *
 143  * BR0_64M:
 144  *    Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
 145  *    Port Size = 32 bits = BRx[19:20] = 11
 146  *
 147  * 0    4    8    12   16   20   24   28
 148  * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801    BR0_8M
 149  * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801    BR0_64M
 150  */
 151 #define CONFIG_SYS_BR0_8M       0xff800801
 152 #define CONFIG_SYS_BR0_64M      0xfc001801
 153
 154 /*
 155  * BR6_8M:
 156  *    Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
 157  *    Port Size = 8 bits = BRx[19:20] = 01
 158  *    Use GPCM = BRx[24:26] = 000
 159  *    Valid = BRx[31] = 1
 160
 161  * BR6_64M:
 162  *    Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
 163  *    Port Size = 32 bits = BRx[19:20] = 11
 164  *
 165  * 0    4    8    12   16   20   24   28
 166  * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801    BR6_8M
 167  * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801    BR6_64M
 168  */
 169 #define CONFIG_SYS_BR6_8M       0xef800801
 170 #define CONFIG_SYS_BR6_64M      0xec001801
 171
 172 /*
 173  * OR0_8M:
 174  *    Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
 175  *    XAM = OR0[17:18] = 11
 176  *    CSNT = OR0[20] = 1
 177  *    ACS = half cycle delay = OR0[21:22] = 11
 178  *    SCY = 6 = OR0[24:27] = 0110
 179  *    TRLX = use relaxed timing = OR0[29] = 1
 180  *    EAD = use external address latch delay = OR0[31] = 1
 181  *
 182  * OR0_64M:
 183  *    Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
 184  *
 185  *
 186  * 0    4    8    12   16   20   24   28
 187  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR0_8M
 188  * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR0_64M
 189  */
 190 #define CONFIG_SYS_OR0_8M       0xff806e65
 191 #define CONFIG_SYS_OR0_64M      0xfc006e65
 192
 193 /*
 194  * OR6_8M:
 195  *    Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
 196  *    XAM = OR6[17:18] = 11
 197  *    CSNT = OR6[20] = 1
 198  *    ACS = half cycle delay = OR6[21:22] = 11
 199  *    SCY = 6 = OR6[24:27] = 0110
 200  *    TRLX = use relaxed timing = OR6[29] = 1
 201  *    EAD = use external address latch delay = OR6[31] = 1
 202  *
 203  * OR6_64M:
 204  *    Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
 205  *
 206  * 0    4    8    12   16   20   24   28
 207  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR6_8M
 208  * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR6_64M
 209  */
 210 #define CONFIG_SYS_OR6_8M       0xff806e65
 211 #define CONFIG_SYS_OR6_64M      0xfc006e65
 212
 213 #ifndef CONFIG_SYS_ALT_BOOT             /* JP12 in default position */
 214 #define CONFIG_SYS_BOOT_BLOCK           0xff800000      /* start of 8MB Flash */
 215 #define CONFIG_SYS_ALT_FLASH            0xec000000      /* 64MB "user" flash */
 216
 217 #define CONFIG_SYS_BR0_PRELIM           CONFIG_SYS_BR0_8M
 218 #define CONFIG_SYS_OR0_PRELIM           CONFIG_SYS_OR0_8M
 219
 220 #define CONFIG_SYS_BR6_PRELIM           CONFIG_SYS_BR6_64M
 221 #define CONFIG_SYS_OR6_PRELIM           CONFIG_SYS_OR6_64M
 222 #else                                   /* JP12 in alternate position */
 223 #define CONFIG_SYS_BOOT_BLOCK           0xfc000000      /* start 64MB Flash */
 224 #define CONFIG_SYS_ALT_FLASH            0xef800000      /* 8MB soldered flash */
 225
 226 #define CONFIG_SYS_BR0_PRELIM           CONFIG_SYS_BR0_64M
 227 #define CONFIG_SYS_OR0_PRELIM           CONFIG_SYS_OR0_64M
 228
 229 #define CONFIG_SYS_BR6_PRELIM           CONFIG_SYS_BR6_8M
 230 #define CONFIG_SYS_OR6_PRELIM           CONFIG_SYS_OR6_8M
 231 #endif
 232
 233 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_BOOT_BLOCK
 234 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, \
 235                                          CONFIG_SYS_ALT_FLASH}
 236 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 237 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* sectors per device */
 238 #undef  CONFIG_SYS_FLASH_CHECKSUM
 239 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 240 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 241
 242 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 243
 244 #define CONFIG_SYS_FLASH_EMPTY_INFO
 245
 246 /* CS5 = Local bus peripherals controlled by the EPLD */
 247
 248 #define CONFIG_SYS_BR5_PRELIM           0xf8000801
 249 #define CONFIG_SYS_OR5_PRELIM           0xff006e65
 250 #define CONFIG_SYS_EPLD_BASE            0xf8000000
 251 #define CONFIG_SYS_LED_DISP_BASE        0xf8000000
 252 #define CONFIG_SYS_USER_SWITCHES_BASE   0xf8100000
 253 #define CONFIG_SYS_BD_REV               0xf8300000
 254 #define CONFIG_SYS_EEPROM_BASE          0xf8b00000
 255
 256 /*
 257  * SDRAM on the Local Bus (CS3 and CS4)
 258  * Note that most boards have a hardware errata where both the
 259  * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
 260  * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
 261  * A hardware workaround is also available, see README.sbc8548 file.
 262  */
 263 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 264 #define CONFIG_SYS_LBC_SDRAM_SIZE       128             /* LBC SDRAM is 128MB */
 265
 266 /*
 267  * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
 268  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 269  *
 270  * For BR3, need:
 271  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 272  *    port-size = 32-bits = BR2[19:20] = 11
 273  *    no parity checking = BR2[21:22] = 00
 274  *    SDRAM for MSEL = BR2[24:26] = 011
 275  *    Valid = BR[31] = 1
 276  *
 277  * 0    4    8    12   16   20   24   28
 278  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 279  *
 280  */
 281
 282 #define CONFIG_SYS_BR3_PRELIM           0xf0001861
 283
 284 /*
 285  * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 286  *
 287  * For OR3, need:
 288  *    64MB mask for AM, OR3[0:7] = 1111 1100
 289  *                 XAM, OR3[17:18] = 11
 290  *    10 columns OR3[19-21] = 011
 291  *    12 rows   OR3[23-25] = 011
 292  *    EAD set for extra time OR[31] = 0
 293  *
 294  * 0    4    8    12   16   20   24   28
 295  * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
 296  */
 297
 298 #define CONFIG_SYS_OR3_PRELIM           0xfc006cc0
 299
 300 /*
 301  * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
 302  * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
 303  *
 304  * For BR4, need:
 305  *    Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
 306  *    port-size = 32-bits = BR2[19:20] = 11
 307  *    no parity checking = BR2[21:22] = 00
 308  *    SDRAM for MSEL = BR2[24:26] = 011
 309  *    Valid = BR[31] = 1
 310  *
 311  * 0    4    8    12   16   20   24   28
 312  * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
 313  *
 314  */
 315
 316 #define CONFIG_SYS_BR4_PRELIM           0xf4001861
 317
 318 /*
 319  * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 320  *
 321  * For OR4, need:
 322  *    64MB mask for AM, OR3[0:7] = 1111 1100
 323  *                 XAM, OR3[17:18] = 11
 324  *    10 columns OR3[19-21] = 011
 325  *    12 rows   OR3[23-25] = 011
 326  *    EAD set for extra time OR[31] = 0
 327  *
 328  * 0    4    8    12   16   20   24   28
 329  * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
 330  */
 331
 332 #define CONFIG_SYS_OR4_PRELIM           0xfc006cc0
 333
 334 #define CONFIG_SYS_LBC_LCRR             0x00000002    /* LB clock ratio reg */
 335 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 336 #define CONFIG_SYS_LBC_LSRT             0x20000000  /* LB sdram refresh timer */
 337 #define CONFIG_SYS_LBC_MRTPR            0x00000000  /* LB refresh timer prescal*/
 338
 339 /*
 340  * Common settings for all Local Bus SDRAM commands.
 341  */
 342 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 343                                 | LSDMR_BSMA1516        \
 344                                 | LSDMR_PRETOACT3       \
 345                                 | LSDMR_ACTTORW3        \
 346                                 | LSDMR_BUFCMD          \
 347                                 | LSDMR_BL8             \
 348                                 | LSDMR_WRC2            \
 349                                 | LSDMR_CL3             \
 350                                 )
 351
 352 #define CONFIG_SYS_LBC_LSDMR_PCHALL     \
 353          (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 354 #define CONFIG_SYS_LBC_LSDMR_ARFRSH     \
 355          (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 356 #define CONFIG_SYS_LBC_LSDMR_MRW        \
 357          (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 358 #define CONFIG_SYS_LBC_LSDMR_RFEN       \
 359          (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN)
 360
 361 #define CONFIG_SYS_INIT_RAM_LOCK        1
 362 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 363 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 364
 365 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000      /* relocate boot L2SRAM */
 366
 367 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 368 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 369
 370 /*
 371  * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
 372  * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total).  For SODIMM
 373  * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
 374  * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total).  This dynamically sets the right
 375  * thing for MONITOR_LEN in both cases.
 376  */
 377 #define CONFIG_SYS_MONITOR_LEN          (~CONFIG_SYS_TEXT_BASE + 1)
 378 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024) /* Reserved for malloc */
 379
 380 /* Serial Port */
 381 #define CONFIG_SYS_NS16550_SERIAL
 382 #define CONFIG_SYS_NS16550_REG_SIZE     1
 383 #define CONFIG_SYS_NS16550_CLK          (400000000 / CONFIG_SYS_CLK_DIV)
 384
 385 #define CONFIG_SYS_BAUDRATE_TABLE \
 386         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 387
 388 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 389 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 390
 391 /*
 392  * I2C
 393  */
 394 #define CONFIG_SYS_I2C
 395 #define CONFIG_SYS_I2C_FSL
 396 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 397 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 398 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 399 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 400
 401 /*
 402  * General PCI
 403  * Memory space is mapped 1-1, but I/O space must start from 0.
 404  */
 405 #define CONFIG_SYS_PCI_VIRT             0x80000000      /* 1G PCI TLB */
 406 #define CONFIG_SYS_PCI_PHYS             0x80000000      /* 1G PCI TLB */
 407
 408 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 409 #define CONFIG_SYS_PCI1_MEM_BUS         0x80000000
 410 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 411 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 412 #define CONFIG_SYS_PCI1_IO_VIRT         0xe2000000
 413 #define CONFIG_SYS_PCI1_IO_BUS          0x00000000
 414 #define CONFIG_SYS_PCI1_IO_PHYS         0xe2000000
 415 #define CONFIG_SYS_PCI1_IO_SIZE         0x00800000      /* 8M */
 416
 417 #ifdef CONFIG_PCIE1
 418 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 419 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 420 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 421 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 422 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe2800000
 423 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 424 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe2800000
 425 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 426 #endif
 427
 428 #ifdef CONFIG_RIO
 429 /*
 430  * RapidIO MMU
 431  */
 432 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
 433 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 512M */
 434 #endif
 435
 436 #if defined(CONFIG_PCI)
 437 #undef CONFIG_EEPRO100
 438 #undef CONFIG_TULIP
 439
 440 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 441
 442 #endif  /* CONFIG_PCI */
 443
 444 #if defined(CONFIG_TSEC_ENET)
 445
 446 #define CONFIG_TSEC1    1
 447 #define CONFIG_TSEC1_NAME       "eTSEC0"
 448 #define CONFIG_TSEC2    1
 449 #define CONFIG_TSEC2_NAME       "eTSEC1"
 450 #undef CONFIG_MPC85XX_FEC
 451
 452 #define TSEC1_PHY_ADDR          0x19
 453 #define TSEC2_PHY_ADDR          0x1a
 454
 455 #define TSEC1_PHYIDX            0
 456 #define TSEC2_PHYIDX            0
 457
 458 #define TSEC1_FLAGS             TSEC_GIGABIT
 459 #define TSEC2_FLAGS             TSEC_GIGABIT
 460
 461 /* Options are: eTSEC[0-3] */
 462 #define CONFIG_ETHPRIME         "eTSEC0"
 463 #endif  /* CONFIG_TSEC_ENET */
 464
 465 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 466 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 467
 468 /*
 469  * BOOTP options
 470  */
 471 #define CONFIG_BOOTP_BOOTFILESIZE
 472
 473 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 474
 475 /*
 476  * Miscellaneous configurable options
 477  */
 478 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 479
 480 /*
 481  * For booting Linux, the board info and command line data
 482  * have to be in the first 8 MB of memory, since this is
 483  * the maximum mapped by the Linux kernel during initialization.
 484  */
 485 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 486
 487 #if defined(CONFIG_CMD_KGDB)
 488 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 489 #endif
 490
 491 /*
 492  * Environment Configuration
 493  */
 494 #if defined(CONFIG_TSEC_ENET)
 495 #define CONFIG_HAS_ETH0
 496 #define CONFIG_HAS_ETH1
 497 #endif
 498
 499 #define CONFIG_IPADDR    192.168.0.55
 500
 501 #define CONFIG_HOSTNAME  "sbc8548"
 502 #define CONFIG_ROOTPATH  "/opt/eldk/ppc_85xx"
 503 #define CONFIG_BOOTFILE  "/uImage"
 504 #define CONFIG_UBOOTPATH /u-boot.bin    /* TFTP server */
 505
 506 #define CONFIG_SERVERIP  192.168.0.2
 507 #define CONFIG_GATEWAYIP 192.168.0.1
 508 #define CONFIG_NETMASK   255.255.255.0
 509
 510 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 511
 512 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 513 "netdev=eth0\0"                                         \
 514 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                             \
 515 "tftpflash=tftpboot $loadaddr $uboot; "                 \
 516         "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 517         "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "      \
 518         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
 519         "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 520         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
 521 "consoledev=ttyS0\0"                            \
 522 "ramdiskaddr=2000000\0"                 \
 523 "ramdiskfile=uRamdisk\0"                        \
 524 "fdtaddr=1e00000\0"                             \
 525 "fdtfile=sbc8548.dtb\0"
 526
 527 #define CONFIG_NFSBOOTCOMMAND                                           \
 528    "setenv bootargs root=/dev/nfs rw "                                  \
 529       "nfsroot=$serverip:$rootpath "                                    \
 530       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 531       "console=$consoledev,$baudrate $othbootargs;"                     \
 532    "tftp $loadaddr $bootfile;"                                          \
 533    "tftp $fdtaddr $fdtfile;"                                            \
 534    "bootm $loadaddr - $fdtaddr"
 535
 536 #define CONFIG_RAMBOOTCOMMAND \
 537    "setenv bootargs root=/dev/ram rw "                                  \
 538       "console=$consoledev,$baudrate $othbootargs;"                     \
 539    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 540    "tftp $loadaddr $bootfile;"                                          \
 541    "tftp $fdtaddr $fdtfile;"                                            \
 542    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 543
 544 #define CONFIG_BOOTCOMMAND      CONFIG_RAMBOOTCOMMAND
 545
 546 #endif  /* __CONFIG_H */