include/configs/sbc8560.h

   1 /*
   2  * (C) Copyright 2002,2003 Motorola,Inc.
   3  * Xianghua Xiao <X.Xiao@motorola.com>
   4  *
   5  * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
   6  * Added support for Wind River SBC8560 board
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /* sbc8560 board configuration file */
  28 /* please refer to doc/README.sbc8560 for more info */
  29 /* make sure you change the MAC address and other network params first,
  30  * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
  31  */
  32
  33 #ifndef __CONFIG_H
  34 #define __CONFIG_H
  35
  36 /* High Level Configuration Options */
  37 #define CONFIG_BOOKE            1       /* BOOKE                        */
  38 #define CONFIG_E500             1       /* BOOKE e500 family            */
  39 #define CONFIG_MPC85xx          1       /* MPC8540/MPC8560              */
  40 #define CONFIG_MPC85xx_REV1     1       /* MPC85xx Rev 1.0 chip         */
  41
  42
  43 #define CONFIG_CPM2             1       /* has CPM2 */
  44 #define CONFIG_SBC8560          1       /* configuration for SBC8560 board */
  45 #define CONFIG_MPC8560          1
  46
  47 /* XXX flagging this as something I might want to delete */
  48 #define CONFIG_MPC8560ADS       1       /* MPC8560ADS board specific    */
  49
  50 #define CONFIG_TSEC_ENET                /* tsec ethernet support        */
  51 #undef  CONFIG_PCI                      /* pci ethernet support         */
  52 #undef  CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support     */
  53
  54 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  55
  56 #define CONFIG_ENV_OVERWRITE
  57
  58 /* Using Localbus SDRAM to emulate flash before we can program the flash,
  59  * normally you need a flash-boot image(u-boot.bin), if so undef this.
  60  */
  61 #undef CONFIG_RAM_AS_FLASH
  62
  63 #if defined(CONFIG_PCI_66)              /* some PCI card is 33Mhz only  */
  64   #define CONFIG_SYS_CLK_FREQ   66000000/* sysclk for MPC85xx           */
  65 #else
  66   #define CONFIG_SYS_CLK_FREQ   33000000/* most pci cards are 33Mhz     */
  67 #endif
  68
  69 /* below can be toggled for performance analysis. otherwise use default */
  70 #define CONFIG_L2_CACHE                     /* toggle L2 cache          */
  71 #undef  CONFIG_BTB                          /* toggle branch predition  */
  72
  73 #define CONFIG_BOARD_EARLY_INIT_F 1         /* Call board_early_init_f  */
  74
  75 #undef  CONFIG_SYS_DRAM_TEST                        /* memory test, takes time  */
  76 #define CONFIG_SYS_MEMTEST_START        0x00200000  /* memtest region */
  77 #define CONFIG_SYS_MEMTEST_END          0x00400000
  78
  79 #if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
  80      defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
  81      defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
  82 #error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
  83 #endif
  84
  85 /*
  86  * Base addresses -- Note these are effective addresses where the
  87  * actual resources get mapped (not physical addresses)
  88  */
  89 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default      */
  90
  91 #if XXX
  92   #define CONFIG_SYS_CCSRBAR            0xfdf00000      /* relocated CCSRBAR    */
  93 #else
  94   #define CONFIG_SYS_CCSRBAR            0xff700000      /* default CCSRBAR      */
  95 #endif
  96 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
  97 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR    */
  98
  99 #define CONFIG_SYS_SDRAM_SIZE           512             /* DDR is 512MB */
 100
 101 /* DDR Setup */
 102 #define CONFIG_FSL_DDR1
 103 #undef CONFIG_FSL_DDR_INTERACTIVE
 104 #undef  CONFIG_DDR_ECC                          /* only for ECC DDR module      */
 105 #undef  CONFIG_SPD_EEPROM                       /* Use SPD EEPROM for DDR setup */
 106 #undef  CONFIG_DDR_SPD
 107
 108 #if defined(CONFIG_MPC85xx_REV1)
 109   #define CONFIG_DDR_DLL                        /* possible DLL fix needed      */
 110 #endif
 111
 112 #undef  CONFIG_DDR_ECC                      /* only for ECC DDR module */
 113 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER        /* DDR controller or DMA? */
 114 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 115
 116 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 117 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 118 #define CONFIG_VERY_BIG_RAM
 119
 120 #define CONFIG_NUM_DDR_CONTROLLERS      1
 121 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 122 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 123
 124 /* I2C addresses of SPD EEPROMs */
 125 #define SPD_EEPROM_ADDRESS      0x55    /* CTLR 0 DIMM 0 */
 126
 127 #undef CONFIG_CLOCKS_IN_MHZ
 128
 129 #if defined(CONFIG_RAM_AS_FLASH)
 130   #define CONFIG_SYS_LBC_SDRAM_BASE     0xfc000000      /* Localbus SDRAM */
 131   #define CONFIG_SYS_FLASH_BASE 0xf8000000      /* start of FLASH 8M  */
 132   #define CONFIG_SYS_BR0_PRELIM 0xf8000801      /* port size 8bit */
 133   #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7      /* 8MB Flash            */
 134 #else /* Boot from real Flash */
 135   #define CONFIG_SYS_LBC_SDRAM_BASE     0xf8000000      /* Localbus SDRAM */
 136   #define CONFIG_SYS_FLASH_BASE 0xff800000      /* start of FLASH 8M    */
 137   #define CONFIG_SYS_BR0_PRELIM 0xff800801      /* port size 8bit      */
 138   #define CONFIG_SYS_OR0_PRELIM 0xff800ff7      /* 8MB Flash            */
 139 #endif
 140 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB    */
 141
 142 /* local bus definitions */
 143 #define CONFIG_SYS_BR1_PRELIM           0xe4001801      /* 64M, 32-bit flash */
 144 #define CONFIG_SYS_OR1_PRELIM           0xfc000ff7
 145
 146 #define CONFIG_SYS_BR2_PRELIM           0x00000000      /* CS2 not used */
 147 #define CONFIG_SYS_OR2_PRELIM           0x00000000
 148
 149 #define CONFIG_SYS_BR3_PRELIM           0xf0001861      /* 64MB localbus SDRAM  */
 150 #define CONFIG_SYS_OR3_PRELIM           0xfc000cc1
 151
 152 #if defined(CONFIG_RAM_AS_FLASH)
 153   #define CONFIG_SYS_BR4_PRELIM 0xf4001861      /* 64M localbus SDRAM */
 154 #else
 155   #define CONFIG_SYS_BR4_PRELIM 0xf8001861      /* 64M localbus SDRAM */
 156 #endif
 157 #define CONFIG_SYS_OR4_PRELIM           0xfc000cc1
 158
 159 #define CONFIG_SYS_BR5_PRELIM           0xfc000801      /* 16M CS5 misc devices */
 160 #if 1
 161   #define CONFIG_SYS_OR5_PRELIM 0xff000ff7
 162 #else
 163   #define CONFIG_SYS_OR5_PRELIM 0xff0000f0
 164 #endif
 165
 166 #define CONFIG_SYS_BR6_PRELIM           0xe0001801      /* 64M, 32-bit flash */
 167 #define CONFIG_SYS_OR6_PRELIM           0xfc000ff7
 168 #define CONFIG_SYS_LBC_LCRR             0x00030002      /* local bus freq       */
 169 #define CONFIG_SYS_LBC_LBCR             0x00000000
 170 #define CONFIG_SYS_LBC_LSRT             0x20000000
 171 #define CONFIG_SYS_LBC_MRTPR            0x20000000
 172 #define CONFIG_SYS_LBC_LSDMR_1          0x2861b723
 173 #define CONFIG_SYS_LBC_LSDMR_2          0x0861b723
 174 #define CONFIG_SYS_LBC_LSDMR_3          0x0861b723
 175 #define CONFIG_SYS_LBC_LSDMR_4          0x1861b723
 176 #define CONFIG_SYS_LBC_LSDMR_5          0x4061b723
 177
 178 /* just hijack the MOT BCSR def for SBC8560 misc devices */
 179 #define CONFIG_SYS_BCSR         ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
 180 /* the size of CS5 needs to be >= 16M for TLB and LAW setups */
 181
 182 #define CONFIG_SYS_INIT_RAM_LOCK        1
 183 #define CONFIG_SYS_INIT_RAM_ADDR        0x70000000      /* Initial RAM address  */
 184 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End of used area in RAM */
 185
 186 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 187 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 188 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 189
 190 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 191 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 192
 193 /* Serial Port */
 194 #undef  CONFIG_CONS_ON_SCC      /* define if console on SCC */
 195 #undef  CONFIG_CONS_NONE        /* define if console on something else */
 196
 197 #define CONFIG_CONS_INDEX       1
 198 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 199 #define CONFIG_SYS_NS16550
 200 #define CONFIG_SYS_NS16550_SERIAL
 201 #define CONFIG_SYS_NS16550_REG_SIZE     1
 202 #define CONFIG_SYS_NS16550_CLK          1843200 /* get_bus_freq(0) */
 203 #define CONFIG_BAUDRATE         9600
 204
 205 #define CONFIG_SYS_BAUDRATE_TABLE  \
 206         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 207
 208 #define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000)
 209 #define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000)
 210
 211 /* Use the HUSH parser */
 212 #define CONFIG_SYS_HUSH_PARSER
 213 #ifdef  CONFIG_SYS_HUSH_PARSER
 214 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 215 #endif
 216
 217 /* pass open firmware flat tree */
 218 #define CONFIG_OF_LIBFDT                1
 219 #define CONFIG_OF_BOARD_SETUP           1
 220 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 221
 222 /*
 223  * I2C
 224  */
 225 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 226 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 227 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 228 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 229 #define CONFIG_SYS_I2C_SLAVE            0x7F
 230 #define CONFIG_SYS_I2C_NOPROBES {0x69}  /* Don't probe these addrs */
 231 #define CONFIG_SYS_I2C_OFFSET           0x3000
 232
 233 #define CONFIG_SYS_PCI_MEM_BASE 0xC0000000
 234 #define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000
 235 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
 236
 237 #ifdef CONFIG_TSEC_ENET
 238
 239 #ifndef CONFIG_NET_MULTI
 240 #define CONFIG_NET_MULTI        1
 241 #endif
 242
 243 #ifndef CONFIG_MII
 244 #define CONFIG_MII              1       /* MII PHY management */
 245 #endif
 246 #define CONFIG_TSEC1    1
 247 #define CONFIG_TSEC1_NAME       "TSEC0"
 248 #define CONFIG_TSEC2    1
 249 #define CONFIG_TSEC2_NAME       "TSEC1"
 250 #define TSEC1_PHY_ADDR          0x19
 251 #define TSEC2_PHY_ADDR          0x1a
 252 #define TSEC1_PHYIDX            0
 253 #define TSEC2_PHYIDX            0
 254 #define TSEC1_FLAGS             TSEC_GIGABIT
 255 #define TSEC2_FLAGS             TSEC_GIGABIT
 256
 257 /* Options are: TSEC[0-1] */
 258 #define CONFIG_ETHPRIME         "TSEC0"
 259
 260 #elif defined(CONFIG_ETHER_ON_FCC)      /* CPM FCC Ethernet */
 261
 262   #undef  CONFIG_ETHER_NONE             /* define if ether on something else */
 263   #define CONFIG_ETHER_ON_FCC2          /* cpm FCC ethernet support     */
 264   #define CONFIG_ETHER_INDEX    2       /* which channel for ether  */
 265
 266   #if (CONFIG_ETHER_INDEX == 2)
 267     /*
 268      * - Rx-CLK is CLK13
 269      * - Tx-CLK is CLK14
 270      * - Select bus for bd/buffers
 271      * - Full duplex
 272      */
 273     #define CONFIG_SYS_CMXFCR_MASK      (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 274     #define CONFIG_SYS_CMXFCR_VALUE     (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 275     #define CONFIG_SYS_CPMFCR_RAMTYPE   0
 276     #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
 277
 278   #elif (CONFIG_ETHER_INDEX == 3)
 279     /* need more definitions here for FE3 */
 280   #endif                                /* CONFIG_ETHER_INDEX */
 281
 282   #define CONFIG_MII                    /* MII PHY management */
 283   #define CONFIG_BITBANGMII             /* bit-bang MII PHY management  */
 284   /*
 285    * GPIO pins used for bit-banged MII communications
 286    */
 287   #define MDIO_PORT     2               /* Port C */
 288   #define MDIO_ACTIVE   (iop->pdir |=  0x00400000)
 289   #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
 290   #define MDIO_READ     ((iop->pdat &  0x00400000) != 0)
 291
 292   #define MDIO(bit)     if(bit) iop->pdat |=  0x00400000; \
 293                         else    iop->pdat &= ~0x00400000
 294
 295   #define MDC(bit)      if(bit) iop->pdat |=  0x00200000; \
 296                         else    iop->pdat &= ~0x00200000
 297
 298   #define MIIDELAY      udelay(1)
 299
 300 #endif
 301
 302 /*-----------------------------------------------------------------------
 303  * FLASH and environment organization
 304  */
 305
 306 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant      */
 307 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver        */
 308 #if 0
 309 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)   */
 310 #define CONFIG_SYS_FLASH_PROTECTION             /* use hardware protection      */
 311 #endif
 312 #define CONFIG_SYS_MAX_FLASH_SECT       64      /* max number of sectors on one chip */
 313 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks   */
 314
 315 #undef  CONFIG_SYS_FLASH_CHECKSUM
 316 #define CONFIG_SYS_FLASH_ERASE_TOUT     200000  /* Timeout for Flash Erase (in ms) */
 317 #define CONFIG_SYS_FLASH_WRITE_TOUT     50000   /* Timeout for Flash Write (in ms) */
 318
 319 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor   */
 320
 321 #if 0
 322 /* XXX This doesn't work and I don't want to fix it */
 323 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 324   #define CONFIG_SYS_RAMBOOT
 325 #else
 326   #undef  CONFIG_SYS_RAMBOOT
 327 #endif
 328 #endif
 329
 330 /* Environment */
 331 #if !defined(CONFIG_SYS_RAMBOOT)
 332   #if defined(CONFIG_RAM_AS_FLASH)
 333     #define CONFIG_ENV_IS_NOWHERE
 334     #define CONFIG_ENV_ADDR     (CONFIG_SYS_FLASH_BASE + 0x100000)
 335     #define CONFIG_ENV_SIZE     0x2000
 336   #else
 337     #define CONFIG_ENV_IS_IN_FLASH      1
 338     #define CONFIG_ENV_SECT_SIZE        0x20000 /* 128K(one sector) for env */
 339     #define CONFIG_ENV_ADDR     (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 340     #define CONFIG_ENV_SIZE     0x2000 /* CONFIG_ENV_SECT_SIZE */
 341   #endif
 342 #else
 343   #define CONFIG_SYS_NO_FLASH           1       /* Flash is not usable now      */
 344   #define CONFIG_ENV_IS_NOWHERE 1       /* Store ENV in memory only     */
 345   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 346   #define CONFIG_ENV_SIZE               0x2000
 347 #endif
 348
 349 #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=dhcp console=ttyS0,9600"
 350 /*#define CONFIG_BOOTARGS      "root=/dev/ram rw console=ttyS0,115200"*/
 351 #define CONFIG_BOOTDELAY        5       /* -1 disable autoboot */
 352
 353 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 354 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 355
 356
 357 /*
 358  * BOOTP options
 359  */
 360 #define CONFIG_BOOTP_BOOTFILESIZE
 361 #define CONFIG_BOOTP_BOOTPATH
 362 #define CONFIG_BOOTP_GATEWAY
 363 #define CONFIG_BOOTP_HOSTNAME
 364
 365
 366 /*
 367  * Command line configuration.
 368  */
 369 #include <config_cmd_default.h>
 370
 371 #define CONFIG_CMD_PING
 372 #define CONFIG_CMD_I2C
 373
 374 #if defined(CONFIG_PCI)
 375     #define CONFIG_CMD_PCI
 376 #endif
 377
 378 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 379     #define CONFIG_CMD_MII
 380 #endif
 381
 382 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
 383     #undef CONFIG_CMD_ENV
 384     #undef CONFIG_CMD_LOADS
 385 #endif
 386
 387
 388 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 389
 390 /*
 391  * Miscellaneous configurable options
 392  */
 393 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 394 #define CONFIG_SYS_PROMPT       "SBC8560=> " /* Monitor Command Prompt  */
 395 #if defined(CONFIG_CMD_KGDB)
 396   #define CONFIG_SYS_CBSIZE     1024            /* Console I/O Buffer Size      */
 397 #else
 398   #define CONFIG_SYS_CBSIZE     256             /* Console I/O Buffer Size      */
 399 #endif
 400 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 401 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 402 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 403 #define CONFIG_SYS_LOAD_ADDR    0x1000000       /* default load address */
 404 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 405
 406 /*
 407  * For booting Linux, the board info and command line data
 408  * have to be in the first 8 MB of memory, since this is
 409  * the maximum mapped by the Linux kernel during initialization.
 410  */
 411 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 412
 413 /*
 414  * Internal Definitions
 415  *
 416  * Boot Flags
 417  */
 418 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 419 #define BOOTFLAG_WARM   0x02            /* Software reboot              */
 420
 421 #if defined(CONFIG_CMD_KGDB)
 422 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 423 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 424 #endif
 425
 426 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 427 #define CONFIG_HAS_ETH0
 428 #define CONFIG_HAS_ETH1
 429 #endif
 430
 431 /* You can compile in a MAC address and your custom net settings by using
 432  * the following syntax.  Your board should be marked with the assigned
 433  * MAC addresses directly on it.
 434  *
 435  * #define CONFIG_ETHADDR               de:ad:be:ef:00:00
 436  * #define CONFIG_ETH1ADDR              fa:ke:ad:dr:es:s!
 437  * #define CONFIG_SERVERIP              <server ip>
 438  * #define CONFIG_IPADDR                <board ip>
 439  * #define CONFIG_GATEWAYIP             <gateway ip>
 440  * #define CONFIG_NETMASK               <your netmask>
 441  */
 442
 443 #define CONFIG_HOSTNAME         SBC8560
 444 #define CONFIG_ROOTPATH         /home/ppc
 445 #define CONFIG_BOOTFILE         uImage
 446
 447 #define CONFIG_EXTRA_ENV_SETTINGS               \
 448         "netdev=eth0\0"                         \
 449         "consoledev=ttyS0\0"                            \
 450         "ramdiskaddr=2000000\0"                 \
 451         "ramdiskfile=ramdisk.uboot\0"                   \
 452         "fdtaddr=c00000\0"                              \
 453         "fdtfile=sbc8560.dtb\0"
 454
 455 #define CONFIG_NFSBOOTCOMMAND                                           \
 456         "setenv bootargs root=/dev/nfs rw "                             \
 457                 "nfsroot=$serverip:$rootpath "                          \
 458                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 459                 "console=$consoledev,$baudrate $othbootargs;"           \
 460         "tftp $loadaddr $bootfile;"                                     \
 461         "tftp $fdtaddr $fdtfile;"                                       \
 462         "bootm $loadaddr - $fdtaddr"
 463
 464
 465 #define CONFIG_RAMBOOTCOMMAND \
 466         "setenv bootargs root=/dev/ram rw "                             \
 467                 "console=$consoledev,$baudrate $othbootargs;"           \
 468         "tftp $ramdiskaddr $ramdiskfile;"                               \
 469         "tftp $loadaddr $bootfile;"                                     \
 470         "tftp $fdtaddr $fdtfile;"                                       \
 471         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 472
 473 #define CONFIG_BOOTCOMMAND      CONFIG_NFSBOOTCOMMAND
 474
 475 #endif  /* __CONFIG_H */