include/configs/sbc8641d.h

   1 /*
   2  * Copyright 2007 Wind River Systems <www.windriver.com>
   3  * Copyright 2007 Embedded Specialties, Inc.
   4  * Joe Hamman <joe.hamman@embeddedspecialties.com>
   5  *
   6  * Copyright 2006 Freescale Semiconductor.
   7  *
   8  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 /*
  30  * SBC8641D board configuration file
  31  *
  32  * Make sure you change the MAC address and other network params first,
  33  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /* High Level Configuration Options */
  40 #define CONFIG_MPC86xx          1       /* MPC86xx */
  41 #define CONFIG_MPC8641          1       /* MPC8641 specific */
  42 #define CONFIG_SBC8641D         1       /* SBC8641D board specific */
  43 #define CONFIG_NUM_CPUS         2       /* Number of CPUs in the system */
  44 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  45
  46 #ifdef RUN_DIAG
  47 #define CFG_DIAG_ADDR        0xff800000
  48 #endif
  49
  50 #define CFG_RESET_ADDRESS    0xfff00100
  51
  52 #define CONFIG_PCI              1       /* Enable PCIE */
  53 #define CONFIG_PCI1             1       /* PCIE controler 1 (slot 1) */
  54 #define CONFIG_PCI2             1       /* PCIE controler 2 (slot 2) */
  55 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  56
  57 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  58 #define CONFIG_ENV_OVERWRITE
  59
  60 #undef CONFIG_SPD_EEPROM                /* Do not use SPD EEPROM for DDR setup*/
  61 #undef CONFIG_DDR_DLL                   /* possible DLL fix needed */
  62 #define CONFIG_DDR_2T_TIMING            /* Sets the 2T timing bit */
  63 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  64 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  65 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  66 #define CONFIG_NUM_DDR_CONTROLLERS     2
  67 #define CACHE_LINE_INTERLEAVING         0x20000000
  68 #define PAGE_INTERLEAVING               0x21000000
  69 #define BANK_INTERLEAVING               0x22000000
  70 #define SUPER_BANK_INTERLEAVING         0x23000000
  71
  72
  73 #define CONFIG_ALTIVEC          1
  74
  75 /*
  76  * L2CR setup -- make sure this is right for your board!
  77  */
  78 #define CFG_L2
  79 #define L2_INIT         0
  80 #define L2_ENABLE       (L2CR_L2E)
  81
  82 #ifndef CONFIG_SYS_CLK_FREQ
  83 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  84 #endif
  85
  86 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  87
  88 #undef  CFG_DRAM_TEST                           /* memory test, takes time */
  89 #define CFG_MEMTEST_START       0x00200000      /* memtest region */
  90 #define CFG_MEMTEST_END         0x00400000
  91
  92 /*
  93  * Base addresses -- Note these are effective addresses where the
  94  * actual resources get mapped (not physical addresses)
  95  */
  96 #define CFG_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default */
  97 #define CFG_CCSRBAR             0xf8000000      /* relocated CCSRBAR */
  98 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR */
  99
 100 #define CFG_PCI1_ADDR           (CFG_CCSRBAR+0x8000)
 101 #define CFG_PCI2_ADDR           (CFG_CCSRBAR+0x9000)
 102
 103 /*
 104  * DDR Setup
 105  */
 106 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory */
 107 #define CFG_DDR_SDRAM_BASE2     0x10000000      /* DDR bank 2 */
 108 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
 109 #define CFG_SDRAM_BASE2         CFG_DDR_SDRAM_BASE2
 110 #define CONFIG_VERY_BIG_RAM
 111
 112 #define MPC86xx_DDR_SDRAM_CLK_CNTL
 113
 114 #if defined(CONFIG_SPD_EEPROM)
 115     /*
 116      * Determine DDR configuration from I2C interface.
 117      */
 118     #define SPD_EEPROM_ADDRESS1         0x51            /* DDR DIMM */
 119     #define SPD_EEPROM_ADDRESS2         0x52            /* DDR DIMM */
 120     #define SPD_EEPROM_ADDRESS3         0x53            /* DDR DIMM */
 121     #define SPD_EEPROM_ADDRESS4         0x54            /* DDR DIMM */
 122
 123 #else
 124     /*
 125      * Manually set up DDR1 & DDR2 parameters
 126      */
 127
 128     #define CFG_SDRAM_SIZE      512             /* DDR is 512MB */
 129
 130     #define CFG_DDR_CS0_BNDS    0x0000000F
 131     #define CFG_DDR_CS1_BNDS    0x00000000
 132     #define CFG_DDR_CS2_BNDS    0x00000000
 133     #define CFG_DDR_CS3_BNDS    0x00000000
 134     #define CFG_DDR_CS0_CONFIG  0x80010102
 135     #define CFG_DDR_CS1_CONFIG  0x00000000
 136     #define CFG_DDR_CS2_CONFIG  0x00000000
 137     #define CFG_DDR_CS3_CONFIG  0x00000000
 138     #define CFG_DDR_EXT_REFRESH 0x00000000
 139     #define CFG_DDR_TIMING_0    0x00220802
 140     #define CFG_DDR_TIMING_1    0x38377322
 141     #define CFG_DDR_TIMING_2    0x002040c7
 142     #define CFG_DDR_CFG_1A      0x43008008
 143     #define CFG_DDR_CFG_2       0x24401000
 144     #define CFG_DDR_MODE_1      0x23c00542
 145     #define CFG_DDR_MODE_2      0x00000000
 146     #define CFG_DDR_MODE_CTL    0x00000000
 147     #define CFG_DDR_INTERVAL    0x05080100
 148     #define CFG_DDR_DATA_INIT   0x00000000
 149     #define CFG_DDR_CLK_CTRL    0x03800000
 150     #define CFG_DDR_CFG_1B      0xC3008008
 151
 152     #define CFG_DDR2_CS0_BNDS   0x0010001F
 153     #define CFG_DDR2_CS1_BNDS   0x00000000
 154     #define CFG_DDR2_CS2_BNDS   0x00000000
 155     #define CFG_DDR2_CS3_BNDS   0x00000000
 156     #define CFG_DDR2_CS0_CONFIG 0x80010102
 157     #define CFG_DDR2_CS1_CONFIG 0x00000000
 158     #define CFG_DDR2_CS2_CONFIG 0x00000000
 159     #define CFG_DDR2_CS3_CONFIG 0x00000000
 160     #define CFG_DDR2_EXT_REFRESH 0x00000000
 161     #define CFG_DDR2_TIMING_0   0x00220802
 162     #define CFG_DDR2_TIMING_1   0x38377322
 163     #define CFG_DDR2_TIMING_2   0x002040c7
 164     #define CFG_DDR2_CFG_1A     0x43008008
 165     #define CFG_DDR2_CFG_2      0x24401000
 166     #define CFG_DDR2_MODE_1     0x23c00542
 167     #define CFG_DDR2_MODE_2     0x00000000
 168     #define CFG_DDR2_MODE_CTL   0x00000000
 169     #define CFG_DDR2_INTERVAL   0x05080100
 170     #define CFG_DDR2_DATA_INIT  0x00000000
 171     #define CFG_DDR2_CLK_CTRL   0x03800000
 172     #define CFG_DDR2_CFG_1B     0xC3008008
 173
 174
 175 #endif
 176
 177 /* #define CFG_ID_EEPROM        1
 178 #define ID_EEPROM_ADDR 0x57 */
 179
 180 /*
 181  * The SBC8641D contains 16MB flash space at ff000000.
 182  */
 183 #define CFG_FLASH_BASE      0xff000000  /* start of FLASH 16M */
 184
 185 /* Flash */
 186 #define CFG_BR0_PRELIM          0xff001001      /* port size 16bit */
 187 #define CFG_OR0_PRELIM          0xff006e65      /* 16MB Boot Flash area */
 188
 189 /* 64KB EEPROM */
 190 #define CFG_BR1_PRELIM          0xf0000801      /* port size 16bit */
 191 #define CFG_OR1_PRELIM          0xffff6e65      /* 64K EEPROM area */
 192
 193 /* EPLD - User switches, board id, LEDs */
 194 #define CFG_BR2_PRELIM          0xf1000801      /* port size 16bit */
 195 #define CFG_OR2_PRELIM          0xfff06e65      /* EPLD (switches, board ID, LEDs) area */
 196
 197 /* Local bus SDRAM 128MB */
 198 #define CFG_BR3_PRELIM          0xe0001861      /* port size ?bit */
 199 #define CFG_OR3_PRELIM          0xfc006cc0      /* 128MB local bus SDRAM area (1st half) */
 200 #define CFG_BR4_PRELIM          0xe4001861      /* port size ?bit */
 201 #define CFG_OR4_PRELIM          0xfc006cc0      /* 128MB local bus SDRAM area (2nd half) */
 202
 203 /* Disk on Chip (DOC) 128MB */
 204 #define CFG_BR5_PRELIM          0xe8001001      /* port size ?bit */
 205 #define CFG_OR5_PRELIM          0xf8006e65      /* 128MB local bus SDRAM area (2nd half) */
 206
 207 /* LCD */
 208 #define CFG_BR6_PRELIM          0xf4000801      /* port size ?bit */
 209 #define CFG_OR6_PRELIM          0xfff06e65      /* 128MB local bus SDRAM area (2nd half) */
 210
 211 /* Control logic & misc peripherals */
 212 #define CFG_BR7_PRELIM          0xf2000801      /* port size ?bit */
 213 #define CFG_OR7_PRELIM          0xfff06e65      /* 128MB local bus SDRAM area (2nd half) */
 214
 215 #define CFG_MAX_FLASH_BANKS     1               /* number of banks */
 216 #define CFG_MAX_FLASH_SECT      131             /* sectors per device */
 217
 218 #undef  CFG_FLASH_CHECKSUM
 219 #define CFG_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 220 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
 221 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 222
 223 #define CFG_FLASH_CFI_DRIVER
 224 #define CFG_FLASH_CFI
 225 #define CFG_WRITE_SWAPPED_DATA
 226 #define CFG_FLASH_EMPTY_INFO
 227 #define CFG_FLASH_PROTECTION
 228
 229 #undef CONFIG_CLOCKS_IN_MHZ
 230
 231 #define CONFIG_L1_INIT_RAM
 232 #define CFG_INIT_RAM_LOCK       1
 233 #ifndef CFG_INIT_RAM_LOCK
 234 #define CFG_INIT_RAM_ADDR       0x0fd00000      /* Initial RAM address */
 235 #else
 236 #define CFG_INIT_RAM_ADDR       0xf8400000      /* Initial RAM address */
 237 #endif
 238 #define CFG_INIT_RAM_END        0x4000          /* End of used area in RAM */
 239
 240 #define CFG_GBL_DATA_SIZE       128             /* num bytes initial data */
 241 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 242 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 243
 244 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Mon */
 245 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserved for malloc */
 246
 247 /* Serial Port */
 248 #define CONFIG_CONS_INDEX     1
 249 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 250 #define CFG_NS16550
 251 #define CFG_NS16550_SERIAL
 252 #define CFG_NS16550_REG_SIZE    1
 253 #define CFG_NS16550_CLK         get_bus_freq(0)
 254
 255 #define CFG_BAUDRATE_TABLE  \
 256         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 257
 258 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 259 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 260
 261 /* Use the HUSH parser */
 262 #define CFG_HUSH_PARSER
 263 #ifdef  CFG_HUSH_PARSER
 264 #define CFG_PROMPT_HUSH_PS2 "> "
 265 #endif
 266
 267 /*
 268  * Pass open firmware flat tree to kernel
 269  */
 270 #define CONFIG_OF_FLAT_TREE     1
 271 #define CONFIG_OF_BOARD_SETUP   1
 272
 273 /* maximum size of the flat tree (8K) */
 274 #define OF_FLAT_TREE_MAX_SIZE   8192
 275
 276 #define OF_CPU          "PowerPC,8641@0"
 277 #define OF_SOC          "soc@f8000000"
 278 #define OF_TBCLK        (bd->bi_busfreq / 4)
 279 #define OF_STDOUT_PATH  "/soc@f8000000/serial@4500"
 280
 281 #define CFG_64BIT_VSPRINTF      1
 282 #define CFG_64BIT_STRTOUL       1
 283
 284 /*
 285  * I2C
 286  */
 287 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 288 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 289 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 290 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 291 #define CFG_I2C_SLAVE           0x7F
 292 #define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs */
 293 #define CFG_I2C_OFFSET          0x3100
 294
 295 /*
 296  * RapidIO MMU
 297  */
 298 #define CFG_RIO_MEM_BASE        0xc0000000      /* base address */
 299 #define CFG_RIO_MEM_PHYS        CFG_RIO_MEM_BASE
 300 #define CFG_RIO_MEM_SIZE        0x20000000      /* 128M */
 301
 302 /*
 303  * General PCI
 304  * Addresses are mapped 1-1.
 305  */
 306 #define CFG_PCI1_MEM_BASE       0x80000000
 307 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 308 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
 309 #define CFG_PCI1_IO_BASE        0xe2000000
 310 #define CFG_PCI1_IO_PHYS        CFG_PCI1_IO_BASE
 311 #define CFG_PCI1_IO_SIZE        0x1000000       /* 16M */
 312
 313 /* PCI view of System Memory */
 314 #define CFG_PCI_MEMORY_BUS      0x00000000
 315 #define CFG_PCI_MEMORY_PHYS     0x00000000
 316 #define CFG_PCI_MEMORY_SIZE     0x80000000
 317
 318 #define CFG_PCI2_MEM_BASE       0xa0000000
 319 #define CFG_PCI2_MEM_PHYS       CFG_PCI2_MEM_BASE
 320 #define CFG_PCI2_MEM_SIZE       0x10000000      /* 256M */
 321 #define CFG_PCI2_IO_BASE        0xe3000000
 322 #define CFG_PCI2_IO_PHYS        CFG_PCI2_IO_BASE
 323 #define CFG_PCI2_IO_SIZE        0x1000000       /* 16M */
 324
 325 #if defined(CONFIG_PCI)
 326
 327 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 328
 329 #undef CFG_SCSI_SCAN_BUS_REVERSE
 330
 331 #define CONFIG_NET_MULTI
 332 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 333
 334 #undef CONFIG_EEPRO100
 335 #undef CONFIG_TULIP
 336
 337 #if !defined(CONFIG_PCI_PNP)
 338     #define PCI_ENET0_IOADDR    0xe0000000
 339     #define PCI_ENET0_MEMADDR   0xe0000000
 340     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 341 #endif
 342
 343 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 344
 345 #define CONFIG_DOS_PARTITION
 346 #undef CONFIG_SCSI_AHCI
 347
 348 #ifdef CONFIG_SCSI_AHCI
 349 #define CONFIG_SATA_ULI5288
 350 #define CFG_SCSI_MAX_SCSI_ID    4
 351 #define CFG_SCSI_MAX_LUN        1
 352 #define CFG_SCSI_MAX_DEVICE     (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
 353 #define CFG_SCSI_MAXDEVICE      CFG_SCSI_MAX_DEVICE
 354 #endif
 355
 356 #endif  /* CONFIG_PCI */
 357
 358 #if defined(CONFIG_TSEC_ENET)
 359
 360 #ifndef CONFIG_NET_MULTI
 361 #define CONFIG_NET_MULTI        1
 362 #endif
 363
 364 /* #define CONFIG_MII           1 */    /* MII PHY management */
 365
 366 #define CONFIG_TSEC1    1
 367 #define CONFIG_TSEC1_NAME       "eTSEC1"
 368 #define CONFIG_TSEC2    1
 369 #define CONFIG_TSEC2_NAME       "eTSEC2"
 370 #define CONFIG_TSEC3    1
 371 #define CONFIG_TSEC3_NAME       "eTSEC3"
 372 #define CONFIG_TSEC4    1
 373 #define CONFIG_TSEC4_NAME       "eTSEC4"
 374
 375 #define TSEC1_PHY_ADDR          0x1F
 376 #define TSEC2_PHY_ADDR          0x00
 377 #define TSEC3_PHY_ADDR          0x01
 378 #define TSEC4_PHY_ADDR          0x02
 379 #define TSEC1_PHYIDX            0
 380 #define TSEC2_PHYIDX            0
 381 #define TSEC3_PHYIDX            0
 382 #define TSEC4_PHYIDX            0
 383
 384 #define CFG_TBIPA_VALUE 0x1e    /* Set TBI address not to conflict with TSEC1_PHY_ADDR */
 385
 386 #define CONFIG_ETHPRIME         "eTSEC1"
 387
 388 #endif  /* CONFIG_TSEC_ENET */
 389
 390 /*
 391  * BAT0         2G     Cacheable, non-guarded
 392  * 0x0000_0000  2G     DDR
 393  */
 394 #define CFG_DBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE)
 395 #define CFG_DBAT0U      (BATU_BL_2G | BATU_VS | BATU_VP)
 396 #define CFG_IBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE )
 397 #define CFG_IBAT0U      CFG_DBAT0U
 398
 399 /*
 400  * BAT1         1G     Cache-inhibited, guarded
 401  * 0x8000_0000  512M   PCI-Express 1 Memory
 402  * 0xa000_0000  512M   PCI-Express 2 Memory
 403  *      Changed it for operating from 0xd0000000
 404  */
 405 #define CFG_DBAT1L      ( CFG_PCI1_MEM_BASE | BATL_PP_RW \
 406                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 407 #define CFG_DBAT1U      (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 408 #define CFG_IBAT1L      (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 409 #define CFG_IBAT1U      CFG_DBAT1U
 410
 411 /*
 412  * BAT2         512M   Cache-inhibited, guarded
 413  * 0xc000_0000  512M   RapidIO Memory
 414  */
 415 #define CFG_DBAT2L      (CFG_RIO_MEM_BASE | BATL_PP_RW \
 416                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 417 #define CFG_DBAT2U      (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
 418 #define CFG_IBAT2L      (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 419 #define CFG_IBAT2U      CFG_DBAT2U
 420
 421 /*
 422  * BAT3         4M     Cache-inhibited, guarded
 423  * 0xf800_0000  4M     CCSR
 424  */
 425 #define CFG_DBAT3L      ( CFG_CCSRBAR | BATL_PP_RW \
 426                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 427 #define CFG_DBAT3U      (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
 428 #define CFG_IBAT3L      (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 429 #define CFG_IBAT3U      CFG_DBAT3U
 430
 431 /*
 432  * BAT4         32M    Cache-inhibited, guarded
 433  * 0xe200_0000  16M    PCI-Express 1 I/O
 434  * 0xe300_0000  16M    PCI-Express 2 I/0
 435  *    Note that this is at 0xe0000000
 436  */
 437 #define CFG_DBAT4L      ( CFG_PCI1_IO_BASE | BATL_PP_RW \
 438                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 439 #define CFG_DBAT4U      (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
 440 #define CFG_IBAT4L      (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 441 #define CFG_IBAT4U      CFG_DBAT4U
 442
 443 /*
 444  * BAT5         128K   Cacheable, non-guarded
 445  * 0xe401_0000  128K   Init RAM for stack in the CPU DCache (no backing memory)
 446  */
 447 #define CFG_DBAT5L      (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 448 #define CFG_DBAT5U      (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 449 #define CFG_IBAT5L      CFG_DBAT5L
 450 #define CFG_IBAT5U      CFG_DBAT5U
 451
 452 /*
 453  * BAT6         32M    Cache-inhibited, guarded
 454  * 0xfe00_0000  32M    FLASH
 455  */
 456 #define CFG_DBAT6L      ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
 457                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 458 #define CFG_DBAT6U      ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
 459 #define CFG_IBAT6L      ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
 460 #define CFG_IBAT6U      CFG_DBAT6U
 461
 462 #define CFG_DBAT7L      0x00000000
 463 #define CFG_DBAT7U      0x00000000
 464 #define CFG_IBAT7L      0x00000000
 465 #define CFG_IBAT7U      0x00000000
 466
 467 /*
 468  * Environment
 469  */
 470 #define CFG_ENV_IS_IN_FLASH     1
 471 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + 0x40000)
 472 #define CFG_ENV_SECT_SIZE       0x40000 /* 256K(one sector) for env */
 473 #define CFG_ENV_SIZE            0x2000
 474
 475 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 476 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 477
 478 #include <config_cmd_default.h>
 479     #define CONFIG_CMD_PING
 480     #define CONFIG_CMD_I2C
 481
 482 #if defined(CONFIG_PCI)
 483     #define CONFIG_CMD_PCI
 484 #endif
 485
 486 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 487
 488 /*
 489  * Miscellaneous configurable options
 490  */
 491 #define CFG_LONGHELP                    /* undef to save memory */
 492 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 493 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt */
 494
 495 #if defined(CONFIG_CMD_KGDB)
 496     #define CFG_CBSIZE  1024            /* Console I/O Buffer Size */
 497 #else
 498     #define CFG_CBSIZE  256             /* Console I/O Buffer Size */
 499 #endif
 500
 501 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 502 #define CFG_MAXARGS     16              /* max number of command args */
 503 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 504 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 505
 506 /*
 507  * For booting Linux, the board info and command line data
 508  * have to be in the first 8 MB of memory, since this is
 509  * the maximum mapped by the Linux kernel during initialization.
 510  */
 511 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux*/
 512
 513 /* Cache Configuration */
 514 #define CFG_DCACHE_SIZE         32768
 515 #define CFG_CACHELINE_SIZE      32
 516 #if defined(CONFIG_CMD_KGDB)
 517 #define CFG_CACHELINE_SHIFT     5       /*log base 2 of the above value*/
 518 #endif
 519
 520 /*
 521  * Internal Definitions
 522  *
 523  * Boot Flags
 524  */
 525 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 526 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 527
 528 #if defined(CONFIG_CMD_KGDB)
 529 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 530 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 531 #endif
 532
 533 /*
 534  * Environment Configuration
 535  */
 536
 537 /* The mac addresses for all ethernet interface */
 538 #if defined(CONFIG_TSEC_ENET)
 539 #define CONFIG_ETHADDR   02:E0:0C:00:00:01
 540 #define CONFIG_ETH1ADDR  02:E0:0C:00:01:FD
 541 #define CONFIG_ETH2ADDR  02:E0:0C:00:02:FD
 542 #define CONFIG_ETH3ADDR  02:E0:0C:00:03:FD
 543 #endif
 544
 545 #define CONFIG_HAS_ETH1         1
 546 #define CONFIG_HAS_ETH2         1
 547 #define CONFIG_HAS_ETH3         1
 548
 549 #define CONFIG_IPADDR           192.168.0.50
 550
 551 #define CONFIG_HOSTNAME         sbc8641d
 552 #define CONFIG_ROOTPATH         /opt/eldk/ppc_74xx
 553 #define CONFIG_BOOTFILE         uImage
 554
 555 #define CONFIG_SERVERIP         192.168.0.2
 556 #define CONFIG_GATEWAYIP        192.168.0.1
 557 #define CONFIG_NETMASK          255.255.255.0
 558
 559 /* default location for tftp and bootm */
 560 #define CONFIG_LOADADDR         1000000
 561
 562 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 563 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 564
 565 #define CONFIG_BAUDRATE 115200
 566
 567 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 568    "netdev=eth0\0"                                                      \
 569    "consoledev=ttyS0\0"                                                 \
 570    "ramdiskaddr=2000000\0"                                              \
 571    "ramdiskfile=uRamdisk\0"                                             \
 572    "dtbaddr=400000\0"                                                   \
 573    "dtbfile=sbc8641d.dtb\0"                                             \
 574    "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0"     \
 575    "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0"    \
 576    "maxcpus=1"
 577
 578 #define CONFIG_NFSBOOTCOMMAND                                           \
 579    "setenv bootargs root=/dev/nfs rw "                                  \
 580       "nfsroot=$serverip:$rootpath "                                    \
 581       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 582       "console=$consoledev,$baudrate $othbootargs;"                     \
 583    "tftp $loadaddr $bootfile;"                                          \
 584    "tftp $dtbaddr $dtbfile;"                                            \
 585    "bootm $loadaddr - $dtbaddr"
 586
 587 #define CONFIG_RAMBOOTCOMMAND                                           \
 588    "setenv bootargs root=/dev/ram rw "                                  \
 589       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 590       "console=$consoledev,$baudrate $othbootargs;"                     \
 591    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 592    "tftp $loadaddr $bootfile;"                                          \
 593    "tftp $dtbaddr $dtbfile;"                                            \
 594    "bootm $loadaddr $ramdiskaddr $dtbaddr"
 595
 596 #define CONFIG_FLASHBOOTCOMMAND                                         \
 597    "setenv bootargs root=/dev/ram rw "                                  \
 598       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 599       "console=$consoledev,$baudrate $othbootargs;"                     \
 600    "bootm ffd00000 ffb00000 ffa00000"
 601
 602 #define CONFIG_BOOTCOMMAND  CONFIG_FLASHBOOTCOMMAND
 603
 604 #endif  /* __CONFIG_H */