include/configs/sc3.h

   1 /*
   2  * (C) Copyright 2007
   3  * Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
   4  *
   5  * From:
   6  * (C) Copyright 2003
   7  * Juergen Beisert, EuroDesign embedded technologies, jbeisert@eurodsn.de
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 #undef USE_VGA_GRAPHICS
  32
  33 /* Memory Map
  34  * 0x00000000 .... 0x03FFFFFF -> RAM (up to 128MiB)
  35  * 0x74000000 .... 0x740FFFFF -> CS#6
  36  * 0x74100000 .... 0x741FFFFF -> CS#7
  37  * 0x74200000 .... 0x742FFFFF -> CS4# if no internal USB
  38  * 0x74300000 .... 0x743FFFFF -> CS5# if no boosted IDE
  39  * 0x77C00000 .... 0x77CFFFFF -> CS4# USB HC (1 MiB)
  40  * 0x77D00000 .... 0x77DFFFFF -> CS1# NAND-Flash (1 MiB)
  41  * 0x78000000 .... 0x78FFFFFF -> CS2# ISA-Bus Speicherzugriff (16 MiB)
  42  * 0x79000000 .... 0x7900FFFF -> CS2# ISA-Bus IO-Zugriff (16 MiB, mapped: 64kiB)
  43  * 0x79010000 .... 0x79FFFFFF -> CS2# ISA-Bus IO-Zugriff (mirrored)
  44  * 0x7A000000 .... 0x7A0FFFFF -> CS5# IDE emulation (1MiB)
  45  *
  46  * 0x80000000 .... 0x9FFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 1:1)
  47  * 0xA0000000 .... 0xBFFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 0x00000000...0x1FFFFFFF)
  48  * 0xE8000000 .... 0xE800FFFF -> PCI-Bus IO-Zugriff (64kiB, translated to PCI: 0x0000...0xFFFF)
  49  * 0xE8800000 .... 0xEBFFFFFF -> PCI-Bus IO-Zugriff (56MiB, translated to PCI: 0x00800000...0x3FFFFFF)
  50  * 0xEED00000 .... 0xEED00003 -> PCI-Bus
  51  * 0xEF400000 .... 0xEF40003F -> PCI-Bus Local Configuration Registers
  52  * 0xEF40003F .... 0xEF5FFFFF -> reserved
  53  * 0xEF600000 .... 0xEFFFFFFF -> 405GP internal Devices (10 MiB)
  54  * 0xF0000000 .... 0xF01FFFFF -> Flash-ROM (2 MiB)
  55  * 0xF0200000 .... 0xF7FFFFFF -> free for flash devices
  56  * 0xF8000000 .... 0xF8000FFF -> OnChipMemory (4kiB)
  57  * 0xF8001000 .... 0xFFDFFFFF -> free for flash devices
  58  * 0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB)
  59  */
  60
  61 #define CONFIG_SOLIDCARD3       1
  62 #define CONFIG_4xx      1
  63 #define CONFIG_405GP    1
  64
  65 #define CONFIG_BOARD_EARLY_INIT_F       1
  66
  67 /*
  68  * Define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range
  69  * If undefined, IDE access uses a seperat emulation with higher access speed.
  70  * Consider to inform your Linux IDE driver about the different addresses!
  71  * IDE_USES_ISA_EMULATION is only used if your CONFIG_COMMANDS macro includes
  72  * the CFG_CMD_IDE macro!
  73  */
  74 #define IDE_USES_ISA_EMULATION
  75
  76 /*-----------------------------------------------------------------------
  77  * Serial Port
  78  *----------------------------------------------------------------------*/
  79 #define CONFIG_SERIAL_MULTI
  80 #undef CONFIG_SERIAL_SOFTWARE_FIFO
  81 /*
  82  * define CONFIG_POWER_DOWN if your cpu should power down while waiting for your input
  83  * Works only, if you have enabled the CONFIG_SERIAL_SOFTWARE_FIFO feature
  84  */
  85 #if CONFIG_SERIAL_SOFTWARE_FIFO
  86  #define CONFIG_POWER_DOWN
  87 #endif
  88
  89 /*
  90  * define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz
  91  */
  92 #define CONFIG_SYS_CLK_FREQ     33333333
  93
  94 /*
  95  * define CONFIG_BAUDRATE to the baudrate value you want to use as default
  96  */
  97 #define CONFIG_BAUDRATE         115200
  98 #define CONFIG_BOOTDELAY        3 /* autoboot after 3 seconds         */
  99
 100 #define CONFIG_PREBOOT  "echo;" \
 101         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 102         "echo"
 103
 104 #undef  CONFIG_BOOTARGS
 105
 106 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 107         "netdev=eth0\0"                                                 \
 108         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 109                 "nfsroot=${serverip}:${rootpath}\0"                     \
 110         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 111         "nand_args=setenv bootargs root=/dev/mtdblock5 rw"              \
 112                 "rootfstype=jffs2\0"                                    \
 113         "addip=setenv bootargs ${bootargs} "                            \
 114                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 115                 ":${hostname}:${netdev}:off panic=1\0"                  \
 116         "flash_nfs=run nfsargs addip;"                                  \
 117                 "bootm ${kernel_addr}\0"                                \
 118         "flash_nand=nand_args addip addcon;bootm ${kernel_addr}\0"      \
 119         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 120         "rootpath=/opt/eldk/ppc_4xx\0"                                  \
 121         "bootfile=/tftpboot/sc3/uImage\0"                               \
 122         "kernel_addr=FFE08000\0"                                        \
 123         ""
 124 #undef CONFIG_BOOTCOMMAND
 125
 126 #define CONFIG_SILENT_CONSOLE   1       /* enable silent startup */
 127 #define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
 128
 129 #if 1   /* feel free to disable for development */
 130 #define CONFIG_AUTOBOOT_KEYED           /* Enable password protection   */
 131 #define CONFIG_AUTOBOOT_PROMPT          "\nSC3 - booting... stop with S\n"
 132 #define CONFIG_AUTOBOOT_DELAY_STR       "S"     /* 1st "password"       */
 133 #endif
 134
 135 /*
 136  * define CONFIG_BOOTCOMMAND to the autoboot commands. They will running after
 137  * the CONFIG_BOOTDELAY delay to boot your machine
 138  */
 139 #define CONFIG_BOOTCOMMAND      "bootp;dcache on;bootm"
 140
 141 /*
 142  * define CONFIG_BOOTARGS to the default kernel parameters. They will used if you don't
 143  * set different values at the u-boot prompt
 144  */
 145 #ifdef USE_VGA_GRAPHICS
 146  #define CONFIG_BOOTARGS        "root=/dev/nfs rw ip=bootp nfsroot=/tftpboot/solidcard3re"
 147 #else
 148  #define CONFIG_BOOTARGS        "console=ttyS0,115200 root=/dev/nfs rw ip=bootp"
 149 #endif
 150 /*
 151  * Is the USB host controller assembled? If yes define CONFIG_ISP1161_PRESENT
 152  * This reserves memory bank #4 for this purpose
 153  */
 154 #undef CONFIG_ISP1161_PRESENT
 155
 156 #undef CONFIG_LOADS_ECHO   /* no echo on for serial download    */
 157 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 158
 159 #define CONFIG_NET_MULTI
 160 /* #define CONFIG_EEPRO100_SROM_WRITE */
 161 /* #define CONFIG_SHOW_MAC */
 162 #define CONFIG_EEPRO100
 163 #define CONFIG_MII 1                    /* add 405GP MII PHY management         */
 164 #define CONFIG_PHY_ADDR 1       /* the connected Phy defaults to address 1 */
 165
 166 #define CONFIG_COMMANDS   \
 167            (CONFIG_CMD_DFL      | \
 168                         CFG_CMD_PCI     | \
 169                         CFG_CMD_IRQ     | \
 170                         CFG_CMD_NET     | \
 171                         CFG_CMD_MII     | \
 172                         CFG_CMD_PING    | \
 173                         CFG_CMD_NAND    | \
 174                         CFG_CMD_JFFS2   | \
 175                         CFG_CMD_I2C     | \
 176                         CFG_CMD_IDE     | \
 177                         CFG_CMD_DATE    | \
 178                         CFG_CMD_DHCP    | \
 179                         CFG_CMD_CACHE   | \
 180                         CFG_CMD_ELF     )
 181
 182 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 183 #include <cmd_confdefs.h>
 184
 185 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 186
 187 /*
 188  * Miscellaneous configurable options
 189  */
 190 #define CFG_LONGHELP    1               /* undef to save memory         */
 191 #define CFG_PROMPT      "SC3> " /* Monitor Command Prompt       */
 192 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 193
 194 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 195
 196 #define CFG_MAXARGS     16              /* max number of command args   */
 197 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 198
 199 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 200 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 201
 202 /*
 203  * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
 204  * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
 205  * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
 206  * The Linux BASE_BAUD define should match this configuration.
 207  *    baseBaud = cpuClock/(uartDivisor*16)
 208  * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
 209  * set Linux BASE_BAUD to 403200.
 210  *
 211  * Consider the OPB clock! If it get lower the BASE_BAUD must be lower to
 212  * (see 405GP datasheet for descritpion)
 213  */
 214 #undef  CFG_EXT_SERIAL_CLOCK            /* external serial clock */
 215 #undef  CFG_405_UART_ERRATA_59          /* 405GP/CR Rev. D silicon */
 216 #define CFG_BASE_BAUD           921600  /* internal clock */
 217
 218 /* The following table includes the supported baudrates */
 219 #define CFG_BAUDRATE_TABLE  \
 220     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 221
 222 #define CFG_LOAD_ADDR           0x1000000       /* default load address */
 223 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 224
 225 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 226
 227 /*-----------------------------------------------------------------------
 228  * IIC stuff
 229  *-----------------------------------------------------------------------
 230  */
 231 #define  CONFIG_HARD_I2C                /* I2C with hardware support    */
 232 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 233
 234 #define I2C_INIT
 235 #define I2C_ACTIVE 0
 236 #define I2C_TRISTATE 0
 237
 238 #define CFG_I2C_SPEED           100000  /* use the standard 100kHz speed */
 239 #define CFG_I2C_SLAVE           0x7F            /* mask valid bits */
 240
 241 #define CONFIG_RTC_DS1337
 242 #define CFG_I2C_RTC_ADDR 0x68
 243
 244 /*-----------------------------------------------------------------------
 245  * PCI stuff
 246  *-----------------------------------------------------------------------
 247  */
 248 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 249 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 250 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 251
 252 #define CONFIG_PCI                      /* include pci support          */
 253 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 254 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 255                                         /* resource configuration       */
 256
 257 /* If you want to see, whats connected to your PCI bus */
 258 /* #define CONFIG_PCI_SCAN_SHOW */
 259
 260 #define CFG_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
 261 #define CFG_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
 262 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 263 #define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
 264 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 265 #define CFG_PCI_PTM2LA  0x00000000      /* disabled                     */
 266 #define CFG_PCI_PTM2MS  0x00000000      /* disabled                     */
 267 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 268
 269 /*-----------------------------------------------------------------------
 270  * External peripheral base address
 271  *-----------------------------------------------------------------------
 272  */
 273 #if !(CONFIG_COMMANDS & CFG_CMD_IDE)
 274
 275 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 276 #undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
 277
 278 /*-----------------------------------------------------------------------
 279  * IDE/ATA stuff
 280  *-----------------------------------------------------------------------
 281  */
 282 #else /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */
 283 #define CONFIG_START_IDE        1       /* check, if use IDE */
 284
 285 #undef  CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
 286 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 287 #undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
 288
 289 #define CONFIG_ATAPI
 290 #define CONFIG_DOS_PARTITION
 291 #define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 292
 293 #ifndef IDE_USES_ISA_EMULATION
 294
 295 /* New and faster access */
 296 #define CFG_ATA_BASE_ADDR               0x7A000000      /* start of ISA IO emulation */
 297
 298 /* How many IDE busses are available */
 299 #define CFG_IDE_MAXBUS          1
 300
 301 /* What IDE ports are available */
 302 #define CFG_ATA_IDE0_OFFSET     0x000           /* first is available */
 303 #undef  CFG_ATA_IDE1_OFFSET                     /* second not available */
 304
 305 /* access to the data port is calculated:
 306    CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
 307 #define CFG_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O */
 308
 309 /* access to the registers is calculated:
 310    CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
 311 #define CFG_ATA_REG_OFFSET      0x0000  /* Offset for normal register accesses  */
 312
 313 /* access to the alternate register is calculated:
 314    CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
 315 #define CFG_ATA_ALT_OFFSET      0x008           /* Offset for alternate registers       */
 316
 317 #else /* IDE_USES_ISA_EMULATION */
 318
 319 #define CFG_ATA_BASE_ADDR               0x79000000      /* start of ISA IO emulation */
 320
 321 /* How many IDE busses are available */
 322 #define CFG_IDE_MAXBUS          1
 323
 324 /* What IDE ports are available */
 325 #define CFG_ATA_IDE0_OFFSET     0x01F0  /* first is available */
 326 #undef  CFG_ATA_IDE1_OFFSET                             /* second not available */
 327
 328 /* access to the data port is calculated:
 329    CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
 330 #define CFG_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O */
 331
 332 /* access to the registers is calculated:
 333    CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
 334 #define CFG_ATA_REG_OFFSET      0x0000  /* Offset for normal register accesses  */
 335
 336 /* access to the alternate register is calculated:
 337    CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
 338 #define CFG_ATA_ALT_OFFSET      0x03F0          /* Offset for alternate registers       */
 339
 340 #endif /* IDE_USES_ISA_EMULATION */
 341
 342 #endif /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */
 343
 344 /*
 345 #define CFG_KEY_REG_BASE_ADDR   0xF0100000
 346 #define CFG_IR_REG_BASE_ADDR    0xF0200000
 347 #define CFG_FPGA_REG_BASE_ADDR  0xF0300000
 348 */
 349
 350 /*-----------------------------------------------------------------------
 351  * Start addresses for the final memory configuration
 352  * (Set up by the startup code)
 353  * Please note that CFG_SDRAM_BASE _must_ start at 0
 354  *
 355  * CFG_FLASH_BASE   -> start address of internal flash
 356  * CFG_MONITOR_BASE -> start of u-boot
 357  */
 358 #ifndef __ASSEMBLER__
 359 extern unsigned long offsetOfBigFlash;
 360 extern unsigned long offsetOfEnvironment;
 361 #endif
 362
 363 #define CFG_SDRAM_BASE          0x00000000
 364 #define CFG_FLASH_BASE          0xFFE00000
 365 #define CFG_MONITOR_BASE        0xFFFC0000     /* placed last 256k */
 366 #define CFG_MONITOR_LEN         (224 * 1024)    /* Reserve 224 KiB for Monitor  */
 367 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserve 128 KiB for malloc() */
 368
 369 /*
 370  * For booting Linux, the board info and command line data
 371  * have to be in the first 8 MiB of memory, since this is
 372  * the maximum mapped by the Linux kernel during initialization.
 373  */
 374 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 375 /*-----------------------------------------------------------------------
 376  * FLASH organization ## FIXME: lookup in datasheet
 377  */
 378 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 379 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 380
 381 #define CFG_FLASH_CFI                   /* flash is CFI compat. */
 382 #define CFG_FLASH_CFI_DRIVER            /* Use common CFI driver*/
 383 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector   */
 384 #define CFG_FLASH_QUIET_TEST    1       /* don't warn upon unknown flash*/
 385 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 386 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 387
 388 #define CFG_ENV_IS_IN_FLASH     1
 389 #if CFG_ENV_IS_IN_FLASH
 390 #define CFG_ENV_OFFSET          0x00000000  /* Offset of Environment Sector in bottom type */
 391 #define CFG_ENV_SIZE            0x4000      /* Total Size of Environment Sector */
 392 #define CFG_ENV_SECT_SIZE       0x4000      /* see README - env sector total size       */
 393
 394 /* Address and size of Redundant Environment Sector     */
 395 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SIZE)
 396 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 397
 398 #endif
 399 /* let us changing anything in our environment */
 400 #define CONFIG_ENV_OVERWRITE
 401
 402 /*
 403  * NAND-FLASH stuff
 404  */
 405 #define CFG_MAX_NAND_DEVICE     1
 406 #define NAND_MAX_CHIPS          1
 407 #define CFG_NAND_BASE           0x77D00000
 408
 409
 410 #define CONFIG_JFFS2_NAND 1                     /* jffs2 on nand support */
 411
 412 /* No command line, one static partition Partition 3 contains jffs2 rootfs */
 413 #undef  CONFIG_JFFS2_CMDLINE
 414 #define CONFIG_JFFS2_DEV                "nand0"
 415 #define CONFIG_JFFS2_PART_SIZE          0x00400000
 416 #define CONFIG_JFFS2_PART_OFFSET        0x00c00000
 417
 418 /*-----------------------------------------------------------------------
 419  * Cache Configuration
 420  *
 421  * CFG_DCACHE_SIZE -> size of data cache:
 422  * - 405GP 8k
 423  * - 405GPr 16k
 424  * How to handle the difference in chache size?
 425  * CFG_CACHELINE_SIZE -> size of one cache line: 32 bytes
 426  * (used in cpu/ppc4xx/start.S)
 427 */
 428 #define CFG_DCACHE_SIZE    16384
 429
 430 #define CFG_CACHELINE_SIZE 32
 431
 432 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 433  #define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 434 #endif
 435
 436 /*
 437  * Init Memory Controller:
 438  *
 439  */
 440
 441 #define FLASH_BASE0_PRELIM      CFG_FLASH_BASE
 442 #define FLASH_BASE1_PRELIM      0
 443
 444 /*-----------------------------------------------------------------------
 445  * Some informations about the internal SRAM (OCM=On Chip Memory)
 446  *
 447  * CFG_OCM_DATA_ADDR -> location
 448  * CFG_OCM_DATA_SIZE -> size
 449 */
 450
 451 #define CFG_TEMP_STACK_OCM      1
 452 #define CFG_OCM_DATA_ADDR       0xF8000000
 453 #define CFG_OCM_DATA_SIZE       0x1000
 454
 455 /*-----------------------------------------------------------------------
 456  * Definitions for initial stack pointer and data area (in DPRAM):
 457  * - we are using the internal 4k SRAM, so we don't need data cache mapping
 458  * - internal SRAM (OCM=On Chip Memory) is placed to CFG_OCM_DATA_ADDR
 459  * - Stackpointer will be located to
 460  *   (CFG_INIT_RAM_ADDR&0xFFFF0000) | (CFG_INIT_SP_OFFSET&0x0000FFFF)
 461  *   in cpu/ppc4xx/start.S
 462  */
 463
 464 #undef CFG_INIT_DCACHE_CS
 465 /* Where the internal SRAM starts */
 466 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR
 467 /* Where the internal SRAM ends (only offset) */
 468 #define CFG_INIT_RAM_END        0x0F00
 469
 470 /*
 471
 472  CFG_INIT_RAM_ADDR ------> ------------ lower address
 473                            |          |
 474                            |  ^       |
 475                            |  |       |
 476                            |  | Stack |
 477  CFG_GBL_DATA_OFFSET ----> ------------
 478                            |          |
 479                            | 64 Bytes |
 480                            |          |
 481  CFG_INIT_RAM_END  ------> ------------ higher address
 482   (offset only)
 483
 484 */
 485 /* size in bytes reserved for initial data */
 486 #define CFG_GBL_DATA_SIZE     64
 487 #define CFG_GBL_DATA_OFFSET   (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 488 /* Initial value of the stack pointern in internal SRAM */
 489 #define CFG_INIT_SP_OFFSET    CFG_GBL_DATA_OFFSET
 490
 491 /*
 492  * Internal Definitions
 493  *
 494  * Boot Flags
 495  */
 496 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 497 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 498
 499 /* ################################################################################### */
 500 /* These defines will be used in cpu/ppc4xx/cpu_init.c to setup external chip selects  */
 501 /* They are currently undefined cause they are initiaized in board/solidcard3/init.S   */
 502
 503 /* This chip select accesses the boot device */
 504 /* It depends on boot select switch if this device is 16 or 8 bit */
 505
 506 #undef CFG_EBC_PB0AP
 507 #undef CFG_EBC_PB0CR
 508
 509 #undef CFG_EBC_PB1AP
 510 #undef CFG_EBC_PB1CR
 511
 512 #undef CFG_EBC_PB2AP
 513 #undef CFG_EBC_PB2CR
 514
 515 #undef CFG_EBC_PB3AP
 516 #undef CFG_EBC_PB3CR
 517
 518 #undef CFG_EBC_PB4AP
 519 #undef CFG_EBC_PB4CR
 520
 521 #undef CFG_EBC_PB5AP
 522 #undef CFG_EBC_PB5CR
 523
 524 #undef CFG_EBC_PB6AP
 525 #undef CFG_EBC_PB6CR
 526
 527 #undef CFG_EBC_PB7AP
 528 #undef CFG_EBC_PB7CR
 529
 530 #define CFG_EBC_CFG    0xb84ef000
 531
 532 #define CONFIG_SDRAM_BANK0      /* use the standard SDRAM initialization */
 533 #undef CONFIG_SPD_EEPROM
 534
 535 /*
 536  * Define this to get more information about system configuration
 537  */
 538 /* #define SC3_DEBUGOUT */
 539 #undef SC3_DEBUGOUT
 540
 541 /***********************************************************************
 542  * External peripheral base address
 543  ***********************************************************************/
 544
 545 #define CFG_ISA_MEM_BASE_ADDRESS 0x78000000
 546 /*
 547  Die Grafik-Treiber greifen über die Adresse in diesem Macro auf den Chip zu.
 548  Das funktioniert bei deren Karten, weil sie eine PCI-Bridge benutzen, die
 549  das gleiche Mapping durchführen kann, wie der SC520 (also Aufteilen von IO-Zugriffen
 550  auf ISA- und PCI-Zyklen)
 551  */
 552 #define CFG_ISA_IO_BASE_ADDRESS  0xE8000000
 553 /*#define CFG_ISA_IO_BASE_ADDRESS  0x79000000 */
 554
 555 /************************************************************
 556  * Video support
 557  ************************************************************/
 558
 559 #ifdef USE_VGA_GRAPHICS
 560 #define CONFIG_VIDEO            /* To enable video controller support */
 561 #define CONFIG_VIDEO_CT69000
 562 #define CONFIG_CFB_CONSOLE
 563 /* #define CONFIG_VIDEO_LOGO */
 564 #define CONFIG_VGA_AS_SINGLE_DEVICE
 565 #define CONFIG_VIDEO_SW_CURSOR
 566 /* #define CONFIG_VIDEO_HW_CURSOR */
 567 #define CONFIG_VIDEO_ONBOARD    /* Video controller is on-board */
 568
 569 #define VIDEO_HW_RECTFILL
 570 #define VIDEO_HW_BITBLT
 571
 572 #endif
 573
 574 /************************************************************
 575  * Ident
 576  ************************************************************/
 577 #define CONFIG_SC3_VERSION "r1.4"
 578
 579 #define POST_OUT(x) (*((volatile unsigned char*)(0x79000080))=x)
 580
 581 #endif  /* __CONFIG_H */