include/configs/sequoia.h

   1 /*
   2  * (C) Copyright 2006-2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2006
   6  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   7  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /************************************************************************
  26  * sequoia.h - configuration for Sequoia & Rainier boards
  27  ***********************************************************************/
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*-----------------------------------------------------------------------
  32  * High Level Configuration Options
  33  *----------------------------------------------------------------------*/
  34 /* This config file is used for Sequoia (440EPx) and Rainier (440GRx)   */
  35 #ifndef CONFIG_RAINIER
  36 #define CONFIG_440EPX           1               /* Specific PPC440EPx   */
  37 #else
  38 #define CONFIG_440GRX           1               /* Specific PPC440GRx   */
  39 #endif
  40 #define CONFIG_440              1               /* ... PPC440 family    */
  41 #define CONFIG_4xx              1               /* ... PPC4xx family    */
  42 /* Detect Sequoia PLL input clock automatically via CPLD bit            */
  43 #define CONFIG_SYS_CLK_FREQ    ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
  44                                 33333333 : 33000000)
  45
  46 #if 0
  47 /*
  48  * 44x dcache supported is working now on sequoia, but we don't enable
  49  * it yet since it needs further testing
  50  */
  51 #define CONFIG_4xx_DCACHE                       /* enable dcache        */
  52 #endif
  53
  54 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  55 #define CONFIG_MISC_INIT_R      1               /* Call misc_init_r     */
  56
  57 /*-----------------------------------------------------------------------
  58  * Base addresses -- Note these are effective addresses where the
  59  * actual resources get mapped (not physical addresses)
  60  *----------------------------------------------------------------------*/
  61 #define CFG_MONITOR_LEN         (384 * 1024)    /* Reserve 384 kB for Monitor   */
  62 #define CFG_MALLOC_LEN          (256 * 1024)    /* Reserve 256 kB for malloc()  */
  63
  64 #define CFG_BOOT_BASE_ADDR      0xf0000000
  65 #define CFG_SDRAM_BASE          0x00000000      /* _must_ be 0          */
  66 #define CFG_FLASH_BASE          0xfc000000      /* start of FLASH       */
  67 #define CFG_MONITOR_BASE        TEXT_BASE
  68 #define CFG_NAND_ADDR           0xd0000000      /* NAND Flash           */
  69 #define CFG_OCM_BASE            0xe0010000      /* ocm                  */
  70 #define CFG_OCM_DATA_ADDR       CFG_OCM_BASE
  71 #define CFG_PCI_BASE            0xe0000000      /* Internal PCI regs    */
  72 #define CFG_PCI_MEMBASE         0x80000000      /* mapped pci memory    */
  73 #define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
  74 #define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
  75 #define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
  76
  77 /* Don't change either of these */
  78 #define CFG_PERIPHERAL_BASE     0xef600000      /* internal peripherals */
  79
  80 #define CFG_USB2D0_BASE         0xe0000100
  81 #define CFG_USB_DEVICE          0xe0000000
  82 #define CFG_USB_HOST            0xe0000400
  83 #define CFG_BCSR_BASE           0xc0000000
  84
  85 /*-----------------------------------------------------------------------
  86  * Initial RAM & stack pointer
  87  *----------------------------------------------------------------------*/
  88 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache     */
  89 #define CFG_INIT_RAM_ADDR       CFG_OCM_BASE    /* OCM                  */
  90 #define CFG_INIT_RAM_END        (4 << 10)
  91 #define CFG_GBL_DATA_SIZE       256             /* num bytes initial data */
  92 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  93 #define CFG_INIT_SP_OFFSET      CFG_POST_WORD_ADDR
  94
  95 /*-----------------------------------------------------------------------
  96  * Serial Port
  97  *----------------------------------------------------------------------*/
  98 #define CFG_EXT_SERIAL_CLOCK    11059200        /* ext. 11.059MHz clk   */
  99 #define CONFIG_BAUDRATE         115200
 100 #define CONFIG_SERIAL_MULTI     1
 101 /* define this if you want console on UART1 */
 102 #undef CONFIG_UART1_CONSOLE
 103
 104 #define CFG_BAUDRATE_TABLE                                              \
 105         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 106
 107 /*-----------------------------------------------------------------------
 108  * Environment
 109  *----------------------------------------------------------------------*/
 110 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 111 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environment vars       */
 112 #else
 113 #define CFG_ENV_IS_IN_NAND      1       /* use NAND for environment vars        */
 114 #define CFG_ENV_IS_EMBEDDED     1       /* use embedded environment */
 115 #endif
 116
 117 /*-----------------------------------------------------------------------
 118  * FLASH related
 119  *----------------------------------------------------------------------*/
 120 #define CFG_FLASH_CFI                           /* The flash is CFI compatible  */
 121 #define CFG_FLASH_CFI_DRIVER                    /* Use common CFI driver        */
 122
 123 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
 124
 125 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 126 #define CFG_MAX_FLASH_SECT      512     /* max number of sectors on one chip    */
 127
 128 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 129 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 130
 131 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
 132 #define CFG_FLASH_PROTECTION    1       /* use hardware flash protection        */
 133
 134 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 135 #define CFG_FLASH_QUIET_TEST    1       /* don't warn upon unknown flash        */
 136
 137 #ifdef CFG_ENV_IS_IN_FLASH
 138 #define CFG_ENV_SECT_SIZE       0x20000 /* size of one complete sector          */
 139 #define CFG_ENV_ADDR            ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
 140 #define CFG_ENV_SIZE            0x2000  /* Total Size of Environment Sector     */
 141
 142 /* Address and size of Redundant Environment Sector     */
 143 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 144 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 145 #endif
 146
 147 /*
 148  * IPL (Initial Program Loader, integrated inside CPU)
 149  * Will load first 4k from NAND (SPL) into cache and execute it from there.
 150  *
 151  * SPL (Secondary Program Loader)
 152  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 153  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 154  * controller and the NAND controller so that the special U-Boot image can be
 155  * loaded from NAND to SDRAM.
 156  *
 157  * NUB (NAND U-Boot)
 158  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 159  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 160  *
 161  * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 162  * set up. While still running from cache, I experienced problems accessing
 163  * the NAND controller. sr - 2006-08-25
 164  */
 165 #define CFG_NAND_BOOT_SPL_SRC   0xfffff000      /* SPL location                 */
 166 #define CFG_NAND_BOOT_SPL_SIZE  (4 << 10)       /* SPL size                     */
 167 #define CFG_NAND_BOOT_SPL_DST   (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here    */
 168 #define CFG_NAND_U_BOOT_DST     0x01000000      /* Load NUB to this addr        */
 169 #define CFG_NAND_U_BOOT_START   CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
 170 #define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
 171
 172 /*
 173  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 174  */
 175 #define CFG_NAND_U_BOOT_OFFS    (16 << 10)      /* Offset to RAM U-Boot image   */
 176 #define CFG_NAND_U_BOOT_SIZE    (384 << 10)     /* Size of RAM U-Boot image     */
 177
 178 /*
 179  * Now the NAND chip has to be defined (no autodetection used!)
 180  */
 181 #define CFG_NAND_PAGE_SIZE      512             /* NAND chip page size          */
 182 #define CFG_NAND_BLOCK_SIZE     (16 << 10)      /* NAND chip block size         */
 183 #define CFG_NAND_PAGE_COUNT     32              /* NAND chip page count         */
 184 #define CFG_NAND_BAD_BLOCK_POS  5               /* Location of bad block marker */
 185 #undef CFG_NAND_4_ADDR_CYCLE                    /* No fourth addr used (<=32MB) */
 186
 187 #define CFG_NAND_ECCSIZE        256
 188 #define CFG_NAND_ECCBYTES       3
 189 #define CFG_NAND_ECCSTEPS       (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
 190 #define CFG_NAND_OOBSIZE        16
 191 #define CFG_NAND_ECCTOTAL       (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
 192 #define CFG_NAND_ECCPOS         {0, 1, 2, 3, 6, 7}
 193
 194 #ifdef CFG_ENV_IS_IN_NAND
 195 /*
 196  * For NAND booting the environment is embedded in the U-Boot image. Please take
 197  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
 198  */
 199 #define CFG_ENV_SIZE            CFG_NAND_BLOCK_SIZE
 200 #define CFG_ENV_OFFSET          (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
 201 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET + CFG_ENV_SIZE)
 202 #endif
 203
 204 /*-----------------------------------------------------------------------
 205  * DDR SDRAM
 206  *----------------------------------------------------------------------*/
 207 #define CFG_MBYTES_SDRAM        (256)           /* 256MB                        */
 208 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 209 #define CONFIG_DDR_DATA_EYE                     /* use DDR2 optimization        */
 210 #endif
 211
 212 /*-----------------------------------------------------------------------
 213  * I2C
 214  *----------------------------------------------------------------------*/
 215 #define CONFIG_HARD_I2C         1               /* I2C with hardware support    */
 216 #undef  CONFIG_SOFT_I2C                         /* I2C bit-banged               */
 217 #define CFG_I2C_SPEED           400000          /* I2C speed and slave address  */
 218 #define CFG_I2C_SLAVE           0x7F
 219
 220 #define CFG_I2C_MULTI_EEPROMS
 221 #define CFG_I2C_EEPROM_ADDR     (0xa8>>1)
 222 #define CFG_I2C_EEPROM_ADDR_LEN 1
 223 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 224 #define CFG_EEPROM_PAGE_WRITE_BITS 3
 225 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
 226
 227 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 228 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 229 #define CONFIG_DTT_AD7414       1               /* use AD7414           */
 230 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 231 #define CFG_DTT_MAX_TEMP        70
 232 #define CFG_DTT_LOW_TEMP        -30
 233 #define CFG_DTT_HYSTERESIS      3
 234
 235 #define CONFIG_PREBOOT  "echo;"                                         \
 236         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 237         "echo"
 238
 239 #undef  CONFIG_BOOTARGS
 240
 241 /* Setup some board specific values for the default environment variables */
 242 #ifndef CONFIG_RAINIER
 243 #define CONFIG_HOSTNAME         sequoia
 244 #define CFG_BOOTFILE            "bootfile=/tftpboot/sequoia/uImage\0"
 245 #define CFG_ROOTPATH            "rootpath=/opt/eldk/ppc_4xxFP\0"
 246 #else
 247 #define CONFIG_HOSTNAME         rainier
 248 #define CFG_BOOTFILE            "bootfile=/tftpboot/rainier/uImage\0"
 249 #define CFG_ROOTPATH            "rootpath=/opt/eldk/ppc_4xx\0"
 250 #endif
 251
 252 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 253         CFG_BOOTFILE                                                    \
 254         CFG_ROOTPATH                                                    \
 255         "netdev=eth0\0"                                                 \
 256         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 257                 "nfsroot=${serverip}:${rootpath}\0"                     \
 258         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 259         "addip=setenv bootargs ${bootargs} "                            \
 260                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 261                 ":${hostname}:${netdev}:off panic=1\0"                  \
 262         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 263         "flash_nfs=run nfsargs addip addtty;"                           \
 264                 "bootm ${kernel_addr}\0"                                \
 265         "flash_self=run ramargs addip addtty;"                          \
 266                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 267         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 268                 "bootm\0"                                               \
 269         "kernel_addr=FC000000\0"                                        \
 270         "ramdisk_addr=FC180000\0"                                       \
 271         "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"           \
 272         "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"   \
 273                 "cp.b 200000 FFFA0000 60000\0"                          \
 274         "upd=run load;run update\0"                                     \
 275         ""
 276 #define CONFIG_BOOTCOMMAND      "run flash_self"
 277
 278 #if 0
 279 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
 280 #else
 281 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 282 #endif
 283
 284 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 285 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 286
 287 #define CONFIG_M88E1111_PHY     1
 288 #define CONFIG_IBM_EMAC4_V4     1
 289 #define CONFIG_MII              1       /* MII PHY management           */
 290 #define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 291
 292 #define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
 293 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 294
 295 #define CONFIG_HAS_ETH0
 296 #define CFG_RX_ETH_BUFFER       32      /* Number of ethernet rx buffers & descriptors */
 297
 298 #define CONFIG_NET_MULTI        1
 299 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 300 #define CONFIG_PHY1_ADDR        1
 301
 302 /* USB */
 303 #ifdef CONFIG_440EPX
 304 #define CONFIG_USB_OHCI_NEW
 305 #define CONFIG_USB_STORAGE
 306 #define CFG_OHCI_BE_CONTROLLER
 307
 308 #undef CFG_USB_OHCI_BOARD_INIT
 309 #define CFG_USB_OHCI_CPU_INIT   1
 310 #define CFG_USB_OHCI_REGS_BASE  CFG_USB_HOST
 311 #define CFG_USB_OHCI_SLOT_NAME  "ppc440"
 312 #define CFG_USB_OHCI_MAX_ROOT_PORTS 15
 313
 314 /* Comment this out to enable USB 1.1 device */
 315 #define USB_2_0_DEVICE
 316
 317 #endif /* CONFIG_440EPX */
 318
 319 /* Partitions */
 320 #define CONFIG_MAC_PARTITION
 321 #define CONFIG_DOS_PARTITION
 322 #define CONFIG_ISO_PARTITION
 323
 324
 325 /*
 326  * BOOTP options
 327  */
 328 #define CONFIG_BOOTP_BOOTFILESIZE
 329 #define CONFIG_BOOTP_BOOTPATH
 330 #define CONFIG_BOOTP_GATEWAY
 331 #define CONFIG_BOOTP_HOSTNAME
 332 #define CONFIG_BOOTP_SUBNETMASK
 333
 334
 335 /*
 336  * Command line configuration.
 337  */
 338 #include <config_cmd_default.h>
 339
 340 #define CONFIG_CMD_ASKENV
 341 #define CONFIG_CMD_DHCP
 342 #define CONFIG_CMD_DTT
 343 #define CONFIG_CMD_DIAG
 344 #define CONFIG_CMD_EEPROM
 345 #define CONFIG_CMD_ELF
 346 #define CONFIG_CMD_FAT
 347 #define CONFIG_CMD_I2C
 348 #define CONFIG_CMD_IRQ
 349 #define CONFIG_CMD_MII
 350 #define CONFIG_CMD_NAND
 351 #define CONFIG_CMD_NET
 352 #define CONFIG_CMD_NFS
 353 #define CONFIG_CMD_PCI
 354 #define CONFIG_CMD_PING
 355 #define CONFIG_CMD_REGINFO
 356 #define CONFIG_CMD_SDRAM
 357
 358 #ifdef CONFIG_440EPX
 359 #define CONFIG_CMD_USB
 360 #endif
 361
 362 #ifndef CONFIG_RAINIER
 363 #define CFG_POST_FPU_ON         CFG_POST_FPU
 364 #else
 365 #define CFG_POST_FPU_ON         0
 366 #endif
 367
 368 /* POST support */
 369 #define CONFIG_POST             (CFG_POST_MEMORY   | \
 370                                  CFG_POST_CPU      | \
 371                                  CFG_POST_UART     | \
 372                                  CFG_POST_I2C      | \
 373                                  CFG_POST_CACHE    | \
 374                                  CFG_POST_FPU_ON   | \
 375                                  CFG_POST_ETHER    | \
 376                                  CFG_POST_SPR)
 377
 378 #define CFG_POST_WORD_ADDR      (CFG_GBL_DATA_OFFSET - 0x4)
 379 #define CONFIG_LOGBUFFER
 380 #define CFG_POST_CACHE_ADDR     0x10000000 /* free virtual address      */
 381
 382 #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 383
 384 #define CONFIG_SUPPORT_VFAT
 385
 386 /*-----------------------------------------------------------------------
 387  * Miscellaneous configurable options
 388  *----------------------------------------------------------------------*/
 389 #define CFG_LONGHELP                    /* undef to save memory         */
 390 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 391 #if defined(CONFIG_CMD_KGDB)
 392 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 393 #else
 394 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 395 #endif
 396 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 397 #define CFG_MAXARGS             16      /* max number of command args   */
 398 #define CFG_BARGSIZE            CFG_CBSIZE /* Boot Argument Buffer Size */
 399
 400 #define CFG_MEMTEST_START       0x0400000 /* memtest works on           */
 401 #define CFG_MEMTEST_END         0x0C00000 /* 4 ... 12 MB in DRAM        */
 402
 403 #define CFG_LOAD_ADDR           0x100000  /* default load address       */
 404 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 405
 406 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 407
 408 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 409 #define CONFIG_LOOPW            1       /* enable loopw command         */
 410 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 411 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 412 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 413
 414 /*-----------------------------------------------------------------------
 415  * PCI stuff
 416  *----------------------------------------------------------------------*/
 417 /* General PCI */
 418 #define CONFIG_PCI                      /* include pci support          */
 419 #define CONFIG_PCI_PNP                  /* do pci plug-and-play   */
 420 #define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
 421 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 422 #define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
 423
 424 /* Board-specific PCI */
 425 #define CFG_PCI_TARGET_INIT
 426 #define CFG_PCI_MASTER_INIT
 427
 428 #define CFG_PCI_SUBSYS_VENDORID 0x10e8  /* AMCC                         */
 429 #define CFG_PCI_SUBSYS_ID       0xcafe  /* Whatever                     */
 430
 431 /*
 432  * For booting Linux, the board info and command line data
 433  * have to be in the first 8 MB of memory, since this is
 434  * the maximum mapped by the Linux kernel during initialization.
 435  */
 436 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 437
 438 /*-----------------------------------------------------------------------
 439  * External Bus Controller (EBC) Setup
 440  *----------------------------------------------------------------------*/
 441
 442 /*
 443  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
 444  */
 445 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 446 #define CFG_NAND_CS             3               /* NAND chip connected to CSx   */
 447 /* Memory Bank 0 (NOR-FLASH) initialization                                     */
 448 #define CFG_EBC_PB0AP           0x03017200
 449 #define CFG_EBC_PB0CR           (CFG_FLASH_BASE | 0xda000)
 450
 451 /* Memory Bank 3 (NAND-FLASH) initialization                                    */
 452 #define CFG_EBC_PB3AP           0x018003c0
 453 #define CFG_EBC_PB3CR           (CFG_NAND_ADDR | 0x1c000)
 454 #else
 455 #define CFG_NAND_CS             0               /* NAND chip connected to CSx   */
 456 /* Memory Bank 3 (NOR-FLASH) initialization                                     */
 457 #define CFG_EBC_PB3AP           0x03017200
 458 #define CFG_EBC_PB3CR           (CFG_FLASH_BASE | 0xda000)
 459
 460 /* Memory Bank 0 (NAND-FLASH) initialization                                    */
 461 #define CFG_EBC_PB0AP           0x018003c0
 462 #define CFG_EBC_PB0CR           (CFG_NAND_ADDR | 0x1c000)
 463 #endif
 464
 465 /* Memory Bank 2 (CPLD) initialization                                          */
 466 #define CFG_EBC_PB2AP           0x24814580
 467 #define CFG_EBC_PB2CR           (CFG_BCSR_BASE | 0x38000)
 468
 469 #define CFG_BCSR5_PCI66EN       0x80
 470
 471 /*-----------------------------------------------------------------------
 472  * NAND FLASH
 473  *----------------------------------------------------------------------*/
 474 #define CFG_MAX_NAND_DEVICE     1
 475 #define NAND_MAX_CHIPS          1
 476 #define CFG_NAND_BASE           (CFG_NAND_ADDR + CFG_NAND_CS)
 477 #define CFG_NAND_SELECT_DEVICE  1       /* nand driver supports mutipl. chips   */
 478
 479 /*
 480  * Internal Definitions
 481  *
 482  * Boot Flags
 483  */
 484 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 485 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 486
 487 #if defined(CONFIG_CMD_KGDB)
 488 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 489 #define CONFIG_KGDB_SER_INDEX   2           /* which serial port to use */
 490 #endif
 491
 492 /* pass open firmware flat tree */
 493 #define CONFIG_OF_LIBFDT        1
 494 #define CONFIG_OF_BOARD_SETUP   1
 495 #define OF_CPU                  "cpu@0"
 496
 497 #endif  /* __CONFIG_H */