include/configs/sequoia.h

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2006
   6  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   7  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * sequoia.h - configuration for Sequoia & Rainier boards
  27  */
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  */
  34 /* This config file is used for Sequoia (440EPx) and Rainier (440GRx)   */
  35 #ifndef CONFIG_RAINIER
  36 #define CONFIG_440EPX           1       /* Specific PPC440EPx           */
  37 #define CONFIG_HOSTNAME         sequoia
  38 #else
  39 #define CONFIG_440GRX           1       /* Specific PPC440GRx           */
  40 #define CONFIG_HOSTNAME         rainier
  41 #endif
  42 #define CONFIG_440              1       /* ... PPC440 family            */
  43 #define CONFIG_4xx              1       /* ... PPC4xx family            */
  44
  45 #ifndef CONFIG_SYS_TEXT_BASE
  46 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  47 #endif
  48
  49 /*
  50  * Include common defines/options for all AMCC eval boards
  51  */
  52 #include "amcc-common.h"
  53
  54 /* Detect Sequoia PLL input clock automatically via CPLD bit            */
  55 #define CONFIG_SYS_CLK_FREQ    ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
  56                                 33333333 : 33000000)
  57
  58 /*
  59  * Define this if you want support for video console with radeon 9200 pci card
  60  * Also set CONFIG_SYS_TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
  61  */
  62 #undef CONFIG_VIDEO
  63
  64 #ifdef CONFIG_VIDEO
  65 /*
  66  * 44x dcache supported is working now on sequoia, but we don't enable
  67  * it yet since it needs further testing
  68  */
  69 #define CONFIG_4xx_DCACHE               /* enable dcache                */
  70 #endif
  71
  72 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  73 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
  74
  75 /*
  76  * Base addresses -- Note these are effective addresses where the actual
  77  * resources get mapped (not physical addresses).
  78  */
  79 #define CONFIG_SYS_TLB_FOR_BOOT_FLASH   0x0003
  80 #define CONFIG_SYS_BOOT_BASE_ADDR       0xf0000000
  81 #define CONFIG_SYS_FLASH_BASE           0xfc000000      /* start of FLASH       */
  82 #define CONFIG_SYS_NAND_ADDR            0xd0000000      /* NAND Flash           */
  83 #define CONFIG_SYS_OCM_BASE             0xe0010000      /* ocm                  */
  84 #define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_OCM_BASE
  85 #define CONFIG_SYS_PCI_BASE             0xe0000000      /* Internal PCI regs    */
  86 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
  87 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  88 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  89 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  90
  91 #define CONFIG_SYS_USB2D0_BASE          0xe0000100
  92 #define CONFIG_SYS_USB_DEVICE           0xe0000000
  93 #define CONFIG_SYS_USB_HOST             0xe0000400
  94 #define CONFIG_SYS_BCSR_BASE            0xc0000000
  95
  96 /*
  97  * Initial RAM & stack pointer
  98  */
  99 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache     */
 100 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
 101 #define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
 102 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 103 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 104
 105 /*
 106  * Serial Port
 107  */
 108 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 109 #define CONFIG_SYS_EXT_SERIAL_CLOCK     11059200        /* ext. 11.059MHz clk   */
 110
 111 /*
 112  * Environment
 113  */
 114 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 115 #define CONFIG_ENV_IS_IN_NAND           /* use NAND for environ vars    */
 116 #define CONFIG_ENV_IS_EMBEDDED          /* use embedded environment     */
 117 #elif defined(CONFIG_SYS_RAMBOOT)
 118 #define CONFIG_ENV_IS_NOWHERE           /* Store env in memory only     */
 119 #define CONFIG_ENV_SIZE         (8 << 10)
 120 /*
 121  * In RAM-booting version, we have no environment storage. So we need to
 122  * provide at least preliminary MAC addresses for the 4xx EMAC driver to
 123  * register the interfaces. Those two addresses are generated via the
 124  * tools/gen_eth_addr tool and should only be used in a closed laboratory
 125  * environment.
 126  */
 127 #define CONFIG_ETHADDR          4a:56:49:22:3e:43
 128 #define CONFIG_ETH1ADDR         02:93:53:d5:06:98
 129 #else
 130 #define CONFIG_ENV_IS_IN_FLASH          /* use FLASH for environ vars   */
 131 #endif
 132
 133 #if defined(CONFIG_CMD_FLASH)
 134 /*
 135  * FLASH related
 136  */
 137 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 138 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 139
 140 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 141
 142 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks         */
 143 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip  */
 144
 145 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)    */
 146 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)    */
 147
 148 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)   */
 149 #define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection      */
 150
 151 #define CONFIG_SYS_FLASH_EMPTY_INFO           /* print 'E' for empty sector on flinfo */
 152 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash      */
 153
 154 #ifdef CONFIG_ENV_IS_IN_FLASH
 155 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector        */
 156 #define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 157 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector   */
 158
 159 /* Address and size of Redundant Environment Sector     */
 160 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 161 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 162 #endif
 163 #endif /* CONFIG_CMD_FLASH */
 164
 165 /*
 166  * IPL (Initial Program Loader, integrated inside CPU)
 167  * Will load first 4k from NAND (SPL) into cache and execute it from there.
 168  *
 169  * SPL (Secondary Program Loader)
 170  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 171  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 172  * controller and the NAND controller so that the special U-Boot image can be
 173  * loaded from NAND to SDRAM.
 174  *
 175  * NUB (NAND U-Boot)
 176  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 177  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 178  *
 179  * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 180  * set up. While still running from cache, I experienced problems accessing
 181  * the NAND controller. sr - 2006-08-25
 182  */
 183 #define CONFIG_SYS_NAND_BOOT_SPL_SRC    0xfffff000      /* SPL location               */
 184 #define CONFIG_SYS_NAND_BOOT_SPL_SIZE   (4 << 10)       /* SPL size                   */
 185 #define CONFIG_SYS_NAND_BOOT_SPL_DST    (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here  */
 186 #define CONFIG_SYS_NAND_U_BOOT_DST      0x01000000      /* Load NUB to this addr      */
 187 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST      /* Start NUB from     */
 188                                                         /*   this addr        */
 189 #define CONFIG_SYS_NAND_BOOT_SPL_DELTA  (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 190
 191 /*
 192  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 193  */
 194 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (16 << 10)      /* Offset to RAM U-Boot image */
 195 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 << 10)     /* Size of RAM U-Boot image   */
 196
 197 /*
 198  * Now the NAND chip has to be defined (no autodetection used!)
 199  */
 200 #define CONFIG_SYS_NAND_PAGE_SIZE       512             /* NAND chip page size        */
 201 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 << 10)      /* NAND chip block size       */
 202 #define CONFIG_SYS_NAND_PAGE_COUNT      32              /* NAND chip page count       */
 203 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   5             /* Location of bad block marker */
 204 #undef CONFIG_SYS_NAND_4_ADDR_CYCLE                   /* No fourth addr used (<=32MB) */
 205
 206 #define CONFIG_SYS_NAND_ECCSIZE 256
 207 #define CONFIG_SYS_NAND_ECCBYTES        3
 208 #define CONFIG_SYS_NAND_ECCSTEPS        (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
 209 #define CONFIG_SYS_NAND_OOBSIZE 16
 210 #define CONFIG_SYS_NAND_ECCTOTAL        (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
 211 #define CONFIG_SYS_NAND_ECCPOS          {0, 1, 2, 3, 6, 7}
 212
 213 #ifdef CONFIG_ENV_IS_IN_NAND
 214 /*
 215  * For NAND booting the environment is embedded in the U-Boot image. Please take
 216  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
 217  */
 218 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 219 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 220 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 221 #endif
 222
 223 /*
 224  * DDR SDRAM
 225  */
 226 #define CONFIG_SYS_MBYTES_SDRAM        (256)    /* 256MB                        */
 227 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
 228     !defined(CONFIG_SYS_RAMBOOT)
 229 #define CONFIG_DDR_DATA_EYE             /* use DDR2 optimization        */
 230 #endif
 231 #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes     */
 232                                         /* 440EPx errata CHIP 11        */
 233
 234 /*
 235  * I2C
 236  */
 237 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 238
 239 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 240 #define CONFIG_SYS_I2C_EEPROM_ADDR      (0xa8>>1)
 241 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 242 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 243 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 244
 245 /* I2C bootstrap EEPROM */
 246 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x52
 247 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 248 #define CONFIG_4xx_CONFIG_BLOCKSIZE             16
 249
 250 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 251 #define CONFIG_DTT_LM75         1       /* ON Semi's LM75               */
 252 #define CONFIG_DTT_AD7414       1       /* use AD7414                   */
 253 #define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses             */
 254 #define CONFIG_SYS_DTT_MAX_TEMP 70
 255 #define CONFIG_SYS_DTT_LOW_TEMP -30
 256 #define CONFIG_SYS_DTT_HYSTERESIS       3
 257
 258 /*
 259  * Default environment variables
 260  */
 261 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 262         CONFIG_AMCC_DEF_ENV                                             \
 263         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 264         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
 265         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 266         CONFIG_AMCC_DEF_ENV_NAND_UPD                                    \
 267         "kernel_addr=FC000000\0"                                        \
 268         "ramdisk_addr=FC180000\0"                                       \
 269         ""
 270
 271 #define CONFIG_M88E1111_PHY     1
 272 #define CONFIG_IBM_EMAC4_V4     1
 273 #define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 274
 275 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 276 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 277
 278 #define CONFIG_HAS_ETH0
 279 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 280 #define CONFIG_PHY1_ADDR        1
 281
 282 /* USB */
 283 #ifdef CONFIG_440EPX
 284
 285 #undef CONFIG_USB_EHCI  /* OHCI by default */
 286
 287 #ifdef CONFIG_USB_EHCI
 288 #define CONFIG_USB_EHCI_PPC4XX
 289 #define CONFIG_SYS_PPC4XX_USB_ADDR      0xe0000300
 290 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 291 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 292 #define CONFIG_EHCI_DESC_BIG_ENDIAN
 293 #ifdef CONFIG_4xx_DCACHE
 294 #define CONFIG_EHCI_DCACHE
 295 #endif
 296 #else /* CONFIG_USB_EHCI */
 297 #define CONFIG_USB_OHCI_NEW
 298 #define CONFIG_SYS_OHCI_BE_CONTROLLER
 299
 300 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
 301 #define CONFIG_SYS_USB_OHCI_CPU_INIT    1
 302 #define CONFIG_SYS_USB_OHCI_REGS_BASE   CONFIG_SYS_USB_HOST
 303 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ppc440"
 304 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 305 #endif
 306
 307 #define CONFIG_USB_STORAGE
 308 /* Comment this out to enable USB 1.1 device */
 309 #define USB_2_0_DEVICE
 310
 311 #endif /* CONFIG_440EPX */
 312
 313 /* Partitions */
 314 #define CONFIG_MAC_PARTITION
 315 #define CONFIG_DOS_PARTITION
 316 #define CONFIG_ISO_PARTITION
 317
 318 /*
 319  * Commands additional to the ones defined in amcc-common.h
 320  */
 321 #define CONFIG_CMD_CHIP_CONFIG
 322 #define CONFIG_CMD_DTT
 323 #define CONFIG_CMD_FAT
 324 #define CONFIG_CMD_NAND
 325 #define CONFIG_CMD_PCI
 326 #define CONFIG_CMD_SDRAM
 327
 328 #ifdef CONFIG_440EPX
 329 #define CONFIG_CMD_USB
 330 #endif
 331
 332 #ifndef CONFIG_RAINIER
 333 #define CONFIG_SYS_POST_FPU_ON          CONFIG_SYS_POST_FPU
 334 #else
 335 #define CONFIG_SYS_POST_FPU_ON          0
 336 #endif
 337
 338 /*
 339  * Don't run the memory POST on the NAND-booting version. It will
 340  * overwrite part of the U-Boot image which is already loaded from NAND
 341  * to SDRAM.
 342  */
 343 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
 344 #define CONFIG_SYS_POST_MEMORY_ON       0
 345 #else
 346 #define CONFIG_SYS_POST_MEMORY_ON       CONFIG_SYS_POST_MEMORY
 347 #endif
 348
 349 /* POST support */
 350 #define CONFIG_POST             (CONFIG_SYS_POST_CACHE     | \
 351                                  CONFIG_SYS_POST_CPU       | \
 352                                  CONFIG_SYS_POST_ETHER     | \
 353                                  CONFIG_SYS_POST_FPU_ON    | \
 354                                  CONFIG_SYS_POST_I2C       | \
 355                                  CONFIG_SYS_POST_MEMORY_ON | \
 356                                  CONFIG_SYS_POST_SPR       | \
 357                                  CONFIG_SYS_POST_UART)
 358
 359 #define CONFIG_LOGBUFFER
 360 #define CONFIG_SYS_POST_CACHE_ADDR      0x7fff0000      /* free virtual address     */
 361
 362 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* Otherwise it catches logbuffer as output */
 363
 364 #define CONFIG_SUPPORT_VFAT
 365
 366 /*
 367  * PCI stuff
 368  */
 369 /* General PCI */
 370 #define CONFIG_PCI                      /* include pci support          */
 371 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 372 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  0       /* to avoid problems with PNP   */
 373 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 374 #define CONFIG_SYS_PCI_TARGBASE 0x80000000      /* PCIaddr mapped to    */
 375                                                 /*   CONFIG_SYS_PCI_MEMBASE     */
 376 /* Board-specific PCI */
 377 #define CONFIG_SYS_PCI_TARGET_INIT
 378 #define CONFIG_SYS_PCI_MASTER_INIT
 379 #define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
 380
 381 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC                         */
 382 #define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe   /* Whatever                     */
 383
 384 /*
 385  * External Bus Controller (EBC) Setup
 386  */
 387
 388 /*
 389  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
 390  */
 391 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
 392     !defined(CONFIG_SYS_RAMBOOT)
 393 #define CONFIG_SYS_NAND_CS              3       /* NAND chip connected to CSx   */
 394 /* Memory Bank 0 (NOR-FLASH) initialization                             */
 395 #define CONFIG_SYS_EBC_PB0AP            0x03017200
 396 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 397
 398 /* Memory Bank 3 (NAND-FLASH) initialization                            */
 399 #define CONFIG_SYS_EBC_PB3AP            0x018003c0
 400 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 401 #else
 402 #define CONFIG_SYS_NAND_CS              0       /* NAND chip connected to CSx   */
 403 /* Memory Bank 3 (NOR-FLASH) initialization                             */
 404 #define CONFIG_SYS_EBC_PB3AP            0x03017200
 405 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 406
 407 /* Memory Bank 0 (NAND-FLASH) initialization                            */
 408 #define CONFIG_SYS_EBC_PB0AP            0x018003c0
 409 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 410 #endif
 411
 412 /* Memory Bank 2 (CPLD) initialization                                  */
 413 #define CONFIG_SYS_EBC_PB2AP            0x24814580
 414 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_BCSR_BASE | 0x38000)
 415
 416 #define CONFIG_SYS_BCSR5_PCI66EN        0x80
 417
 418 /*
 419  * NAND FLASH
 420  */
 421 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 422 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 423 #define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips */
 424
 425 /*
 426  * PPC440 GPIO Configuration
 427  */
 428 /* test-only: take GPIO init from pcs440ep ???? in config file */
 429 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 430 {                                                                                       \
 431 /* GPIO Core 0 */                                                                       \
 432 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7)     DMA_REQ(2)      */      \
 433 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6)     DMA_ACK(2)      */      \
 434 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5)     DMA_EOT/TC(2)   */      \
 435 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4)     DMA_REQ(3)      */      \
 436 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3)     DMA_ACK(3)      */      \
 437 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2)     DMA_EOT/TC(3)   */      \
 438 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1)                     */      \
 439 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2)                     */      \
 440 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3)                     */      \
 441 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4)                     */      \
 442 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)                    */      \
 443 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR                    */      \
 444 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12                                */      \
 445 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13                                */      \
 446 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14                                */      \
 447 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15                                */      \
 448 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4)                      */      \
 449 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5)                      */      \
 450 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6)                      */      \
 451 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7)                      */      \
 452 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0                     */      \
 453 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1                     */      \
 454 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22                                */      \
 455 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0                          */      \
 456 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2)                      */      \
 457 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3)                      */      \
 458 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26                                */      \
 459 {GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ    USB2D_RXERROR   */      \
 460 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28                USB2D_TXVALID   */      \
 461 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA   USB2D_PAD_SUSPNDM */    \
 462 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK    USB2D_XCVRSELECT*/      \
 463 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/      \
 464 },                                                                                      \
 465 {                                                                                       \
 466 /* GPIO Core 1 */                                                                       \
 467 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0  EBC_DATA(2)     */      \
 468 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1  EBC_DATA(3)     */      \
 469 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
 470 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 471 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N    EBC_DATA(0)     UART3_SIN*/ \
 472 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N    EBC_DATA(1)     UART3_SOUT*/ \
 473 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT    */      \
 474 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN      */      \
 475 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)                     */      \
 476 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)                     */      \
 477 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)                     */      \
 478 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)                     */      \
 479 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)     DMA_ACK(1)      */      \
 480 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)     DMA_EOT/TC(1)   */      \
 481 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)     DMA_REQ(0)      */      \
 482 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)     DMA_ACK(0)      */      \
 483 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)     DMA_EOT/TC(0)   */      \
 484 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 485 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 486 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 487 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 488 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 489 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 490 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 491 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 492 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 493 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 494 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 495 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 496 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 497 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 498 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 499 }                                                                                       \
 500 }
 501
 502 #ifdef CONFIG_VIDEO
 503 #define CONFIG_BIOSEMU                  /* x86 bios emulator for vga bios */
 504 #define CONFIG_ATI_RADEON_FB            /* use radeon framebuffer driver */
 505 #define VIDEO_IO_OFFSET                 0xe8000000
 506 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS          VIDEO_IO_OFFSET
 507 #define CONFIG_VIDEO_SW_CURSOR
 508 #define CONFIG_VIDEO_LOGO
 509 #define CONFIG_CFB_CONSOLE
 510 #define CONFIG_SPLASH_SCREEN
 511 #define CONFIG_VGA_AS_SINGLE_DEVICE
 512 #define CONFIG_CMD_BMP
 513 #endif
 514
 515 #endif /* __CONFIG_H */