include/configs/sequoia.h

   1 /*
   2  * (C) Copyright 2006-2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2006
   6  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   7  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * sequoia.h - configuration for Sequoia & Rainier boards
  27  */
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  */
  34 /* This config file is used for Sequoia (440EPx) and Rainier (440GRx)   */
  35 #ifndef CONFIG_RAINIER
  36 #define CONFIG_440EPX           1       /* Specific PPC440EPx           */
  37 #else
  38 #define CONFIG_440GRX           1       /* Specific PPC440GRx           */
  39 #endif
  40 #define CONFIG_440              1       /* ... PPC440 family            */
  41 #define CONFIG_4xx              1       /* ... PPC4xx family            */
  42 /* Detect Sequoia PLL input clock automatically via CPLD bit            */
  43 #define CONFIG_SYS_CLK_FREQ    ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
  44                                 33333333 : 33000000)
  45
  46 #if 0
  47 /*
  48  * 44x dcache supported is working now on sequoia, but we don't enable
  49  * it yet since it needs further testing
  50  */
  51 #define CONFIG_4xx_DCACHE               /* enable dcache                */
  52 #endif
  53
  54 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  55 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
  56
  57 /*
  58  * Base addresses -- Note these are effective addresses where the actual
  59  * resources get mapped (not physical addresses).
  60  */
  61 #define CFG_MONITOR_LEN         (384 * 1024) /* Reserve 384 kiB for Monitor  */
  62 #define CFG_MALLOC_LEN          (256 * 1024) /* Reserve 256 kiB for malloc() */
  63
  64 #define CFG_TLB_FOR_BOOT_FLASH  0x0003
  65 #define CFG_BOOT_BASE_ADDR      0xf0000000
  66 #define CFG_SDRAM_BASE          0x00000000      /* _must_ be 0          */
  67 #define CFG_FLASH_BASE          0xfc000000      /* start of FLASH       */
  68 #define CFG_MONITOR_BASE        TEXT_BASE
  69 #define CFG_NAND_ADDR           0xd0000000      /* NAND Flash           */
  70 #define CFG_OCM_BASE            0xe0010000      /* ocm                  */
  71 #define CFG_OCM_DATA_ADDR       CFG_OCM_BASE
  72 #define CFG_PCI_BASE            0xe0000000      /* Internal PCI regs    */
  73 #define CFG_PCI_MEMBASE         0x80000000      /* mapped pci memory    */
  74 #define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
  75 #define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
  76 #define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
  77
  78 /* Don't change either of these */
  79 #define CFG_PERIPHERAL_BASE     0xef600000      /* internal peripherals */
  80
  81 #define CFG_USB2D0_BASE         0xe0000100
  82 #define CFG_USB_DEVICE          0xe0000000
  83 #define CFG_USB_HOST            0xe0000400
  84 #define CFG_BCSR_BASE           0xc0000000
  85
  86 /*
  87  * Initial RAM & stack pointer
  88  */
  89 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache     */
  90 #define CFG_INIT_RAM_ADDR       CFG_OCM_BASE    /* OCM                  */
  91 #define CFG_INIT_RAM_END        (4 << 10)
  92 #define CFG_GBL_DATA_SIZE       256     /* num bytes initial data       */
  93 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  94 #define CFG_INIT_SP_OFFSET      CFG_POST_WORD_ADDR
  95
  96 /*
  97  * Serial Port
  98  */
  99 #define CFG_EXT_SERIAL_CLOCK    11059200        /* ext. 11.059MHz clk   */
 100 #define CONFIG_BAUDRATE         115200
 101 #define CONFIG_SERIAL_MULTI     1
 102 /* define this if you want console on UART1 */
 103 #undef CONFIG_UART1_CONSOLE
 104
 105 #define CFG_BAUDRATE_TABLE                                              \
 106         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 107
 108 /*
 109  * Environment
 110  */
 111 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 112 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environ vars   */
 113 #else
 114 #define CFG_ENV_IS_IN_NAND      1       /* use NAND for environ vars    */
 115 #define CFG_ENV_IS_EMBEDDED     1       /* use embedded environment     */
 116 #endif
 117
 118 /*
 119  * FLASH related
 120  */
 121 #define CFG_FLASH_CFI                   /* The flash is CFI compatible  */
 122 #define CFG_FLASH_CFI_DRIVER            /* Use common CFI driver        */
 123
 124 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
 125
 126 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks         */
 127 #define CFG_MAX_FLASH_SECT      512     /* max number of sectors on one chip  */
 128
 129 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)    */
 130 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)    */
 131
 132 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)   */
 133 #define CFG_FLASH_PROTECTION    1       /* use hardware flash protection      */
 134
 135 #define CFG_FLASH_EMPTY_INFO          /* print 'E' for empty sector on flinfo */
 136 #define CFG_FLASH_QUIET_TEST    1       /* don't warn upon unknown flash      */
 137
 138 #ifdef CFG_ENV_IS_IN_FLASH
 139 #define CFG_ENV_SECT_SIZE       0x20000 /* size of one complete sector        */
 140 #define CFG_ENV_ADDR            ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
 141 #define CFG_ENV_SIZE            0x2000  /* Total Size of Environment Sector   */
 142
 143 /* Address and size of Redundant Environment Sector     */
 144 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 145 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 146 #endif
 147
 148 /*
 149  * IPL (Initial Program Loader, integrated inside CPU)
 150  * Will load first 4k from NAND (SPL) into cache and execute it from there.
 151  *
 152  * SPL (Secondary Program Loader)
 153  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 154  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 155  * controller and the NAND controller so that the special U-Boot image can be
 156  * loaded from NAND to SDRAM.
 157  *
 158  * NUB (NAND U-Boot)
 159  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 160  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 161  *
 162  * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 163  * set up. While still running from cache, I experienced problems accessing
 164  * the NAND controller. sr - 2006-08-25
 165  */
 166 #define CFG_NAND_BOOT_SPL_SRC   0xfffff000      /* SPL location               */
 167 #define CFG_NAND_BOOT_SPL_SIZE  (4 << 10)       /* SPL size                   */
 168 #define CFG_NAND_BOOT_SPL_DST   (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here  */
 169 #define CFG_NAND_U_BOOT_DST     0x01000000      /* Load NUB to this addr      */
 170 #define CFG_NAND_U_BOOT_START   CFG_NAND_U_BOOT_DST     /* Start NUB from     */
 171                                                         /*   this addr        */
 172 #define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
 173
 174 /*
 175  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 176  */
 177 #define CFG_NAND_U_BOOT_OFFS    (16 << 10)      /* Offset to RAM U-Boot image */
 178 #define CFG_NAND_U_BOOT_SIZE    (384 << 10)     /* Size of RAM U-Boot image   */
 179
 180 /*
 181  * Now the NAND chip has to be defined (no autodetection used!)
 182  */
 183 #define CFG_NAND_PAGE_SIZE      512             /* NAND chip page size        */
 184 #define CFG_NAND_BLOCK_SIZE     (16 << 10)      /* NAND chip block size       */
 185 #define CFG_NAND_PAGE_COUNT     32              /* NAND chip page count       */
 186 #define CFG_NAND_BAD_BLOCK_POS  5             /* Location of bad block marker */
 187 #undef CFG_NAND_4_ADDR_CYCLE                  /* No fourth addr used (<=32MB) */
 188
 189 #define CFG_NAND_ECCSIZE        256
 190 #define CFG_NAND_ECCBYTES       3
 191 #define CFG_NAND_ECCSTEPS       (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
 192 #define CFG_NAND_OOBSIZE        16
 193 #define CFG_NAND_ECCTOTAL       (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
 194 #define CFG_NAND_ECCPOS         {0, 1, 2, 3, 6, 7}
 195
 196 #ifdef CFG_ENV_IS_IN_NAND
 197 /*
 198  * For NAND booting the environment is embedded in the U-Boot image. Please take
 199  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
 200  */
 201 #define CFG_ENV_SIZE            CFG_NAND_BLOCK_SIZE
 202 #define CFG_ENV_OFFSET          (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
 203 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET + CFG_ENV_SIZE)
 204 #endif
 205
 206 /*
 207  * DDR SDRAM
 208  */
 209 #define CFG_MBYTES_SDRAM        (256)   /* 256MB                        */
 210 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 211 #define CONFIG_DDR_DATA_EYE             /* use DDR2 optimization        */
 212 #endif
 213
 214 /*
 215  * I2C
 216  */
 217 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 218 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 219 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 220 #define CFG_I2C_SLAVE           0x7F
 221
 222 #define CFG_I2C_MULTI_EEPROMS
 223 #define CFG_I2C_EEPROM_ADDR     (0xa8>>1)
 224 #define CFG_I2C_EEPROM_ADDR_LEN 1
 225 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 226 #define CFG_EEPROM_PAGE_WRITE_BITS 3
 227 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
 228
 229 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 230 #define CONFIG_DTT_LM75         1       /* ON Semi's LM75               */
 231 #define CONFIG_DTT_AD7414       1       /* use AD7414                   */
 232 #define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses             */
 233 #define CFG_DTT_MAX_TEMP        70
 234 #define CFG_DTT_LOW_TEMP        -30
 235 #define CFG_DTT_HYSTERESIS      3
 236
 237 #define CONFIG_PREBOOT  "echo;"                                         \
 238         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 239         "echo"
 240
 241 #undef  CONFIG_BOOTARGS
 242
 243 /* Setup some board specific values for the default environment variables */
 244 #ifndef CONFIG_RAINIER
 245 #define CONFIG_HOSTNAME         sequoia
 246 #define CFG_BOOTFILE            "bootfile=/tftpboot/sequoia/uImage\0"
 247 #define CFG_ROOTPATH            "rootpath=/opt/eldk/ppc_4xxFP\0"
 248 #else
 249 #define CONFIG_HOSTNAME         rainier
 250 #define CFG_BOOTFILE            "bootfile=/tftpboot/rainier/uImage\0"
 251 #define CFG_ROOTPATH            "rootpath=/opt/eldk/ppc_4xx\0"
 252 #endif
 253
 254 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 255         CFG_BOOTFILE                                                    \
 256         CFG_ROOTPATH                                                    \
 257         "netdev=eth0\0"                                                 \
 258         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 259                 "nfsroot=${serverip}:${rootpath}\0"                     \
 260         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 261         "addip=setenv bootargs ${bootargs} "                            \
 262                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 263                 ":${hostname}:${netdev}:off panic=1\0"                  \
 264         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 265         "flash_nfs=run nfsargs addip addtty;"                           \
 266                 "bootm ${kernel_addr}\0"                                \
 267         "flash_self=run ramargs addip addtty;"                          \
 268                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 269         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 270                 "bootm\0"                                               \
 271         "kernel_addr=FC000000\0"                                        \
 272         "ramdisk_addr=FC180000\0"                                       \
 273         "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"           \
 274         "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"   \
 275                 "cp.b 200000 FFFA0000 60000\0"                          \
 276         "upd=run load;run update\0"                                     \
 277         ""
 278 #define CONFIG_BOOTCOMMAND      "run flash_self"
 279
 280 #if 0
 281 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
 282 #else
 283 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 284 #endif
 285
 286 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 287 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 288
 289 #define CONFIG_M88E1111_PHY     1
 290 #define CONFIG_IBM_EMAC4_V4     1
 291 #define CONFIG_MII              1       /* MII PHY management           */
 292 #define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 293
 294 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 295 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 296
 297 #define CONFIG_HAS_ETH0
 298 #define CFG_RX_ETH_BUFFER       32      /* Number of ethernet rx        */
 299                                         /*   buffers & descriptors      */
 300 #define CONFIG_NET_MULTI        1
 301 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 302 #define CONFIG_PHY1_ADDR        1
 303
 304 /* USB */
 305 #ifdef CONFIG_440EPX
 306 #define CONFIG_USB_OHCI_NEW
 307 #define CONFIG_USB_STORAGE
 308 #define CFG_OHCI_BE_CONTROLLER
 309
 310 #undef CFG_USB_OHCI_BOARD_INIT
 311 #define CFG_USB_OHCI_CPU_INIT   1
 312 #define CFG_USB_OHCI_REGS_BASE  CFG_USB_HOST
 313 #define CFG_USB_OHCI_SLOT_NAME  "ppc440"
 314 #define CFG_USB_OHCI_MAX_ROOT_PORTS 15
 315
 316 /* Comment this out to enable USB 1.1 device */
 317 #define USB_2_0_DEVICE
 318
 319 #endif /* CONFIG_440EPX */
 320
 321 /* Partitions */
 322 #define CONFIG_MAC_PARTITION
 323 #define CONFIG_DOS_PARTITION
 324 #define CONFIG_ISO_PARTITION
 325
 326 /*
 327  * BOOTP options
 328  */
 329 #define CONFIG_BOOTP_BOOTFILESIZE
 330 #define CONFIG_BOOTP_BOOTPATH
 331 #define CONFIG_BOOTP_GATEWAY
 332 #define CONFIG_BOOTP_HOSTNAME
 333 #define CONFIG_BOOTP_SUBNETMASK
 334
 335 /*
 336  * Command line configuration.
 337  */
 338 #include <config_cmd_default.h>
 339
 340 #define CONFIG_CMD_ASKENV
 341 #define CONFIG_CMD_DHCP
 342 #define CONFIG_CMD_DTT
 343 #define CONFIG_CMD_DIAG
 344 #define CONFIG_CMD_EEPROM
 345 #define CONFIG_CMD_ELF
 346 #define CONFIG_CMD_FAT
 347 #define CONFIG_CMD_I2C
 348 #define CONFIG_CMD_IRQ
 349 #define CONFIG_CMD_MII
 350 #define CONFIG_CMD_NAND
 351 #define CONFIG_CMD_NET
 352 #define CONFIG_CMD_NFS
 353 #define CONFIG_CMD_PCI
 354 #define CONFIG_CMD_PING
 355 #define CONFIG_CMD_REGINFO
 356 #define CONFIG_CMD_SDRAM
 357
 358 #ifdef CONFIG_440EPX
 359 #define CONFIG_CMD_USB
 360 #endif
 361
 362 #ifndef CONFIG_RAINIER
 363 #define CFG_POST_FPU_ON         CFG_POST_FPU
 364 #else
 365 #define CFG_POST_FPU_ON         0
 366 #endif
 367
 368 /* POST support */
 369 #define CONFIG_POST             (CFG_POST_CACHE    | \
 370                                  CFG_POST_CPU      | \
 371                                  CFG_POST_ETHER    | \
 372                                  CFG_POST_FPU_ON   | \
 373                                  CFG_POST_I2C      | \
 374                                  CFG_POST_MEMORY   | \
 375                                  CFG_POST_SPR      | \
 376                                  CFG_POST_UART)
 377
 378 #define CFG_POST_WORD_ADDR      (CFG_GBL_DATA_OFFSET - 0x4)
 379 #define CONFIG_LOGBUFFER
 380 #define CFG_POST_CACHE_ADDR     0x7fff0000      /* free virtual address     */
 381
 382 #define CFG_CONSOLE_IS_IN_ENV   /* Otherwise it catches logbuffer as output */
 383
 384 #define CONFIG_SUPPORT_VFAT
 385
 386 /*
 387  * Miscellaneous configurable options
 388  */
 389 #define CFG_LONGHELP                    /* undef to save memory         */
 390 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 391 #if defined(CONFIG_CMD_KGDB)
 392 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 393 #else
 394 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 395 #endif
 396 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
 397                                         /* Print Buffer Size            */
 398 #define CFG_MAXARGS             16      /* max number of command args   */
 399 #define CFG_BARGSIZE            CFG_CBSIZE /* Boot Argument Buffer Size */
 400
 401 #define CFG_MEMTEST_START       0x0400000 /* memtest works on           */
 402 #define CFG_MEMTEST_END         0x0C00000 /* 4 ... 12 MB in DRAM        */
 403
 404 #define CFG_LOAD_ADDR           0x100000  /* default load address       */
 405 #define CFG_EXTBDINFO           1  /* To use extended board_into (bd_t) */
 406
 407 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 408
 409 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 410 #define CONFIG_LOOPW            1       /* enable loopw command         */
 411 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 412 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 413 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 414
 415 /*
 416  * PCI stuff
 417  */
 418 /* General PCI */
 419 #define CONFIG_PCI                      /* include pci support          */
 420 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 421 #define CFG_PCI_CACHE_LINE_SIZE 0       /* to avoid problems with PNP   */
 422 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 423 #define CFG_PCI_TARGBASE        0x80000000      /* PCIaddr mapped to    */
 424                                                 /*   CFG_PCI_MEMBASE    */
 425 /* Board-specific PCI */
 426 #define CFG_PCI_TARGET_INIT
 427 #define CFG_PCI_MASTER_INIT
 428
 429 #define CFG_PCI_SUBSYS_VENDORID 0x10e8  /* AMCC                         */
 430 #define CFG_PCI_SUBSYS_ID       0xcafe  /* Whatever                     */
 431
 432 /*
 433  * For booting Linux, the board info and command line data have to be in the
 434  * first 8 MB of memory, since this is the maximum mapped by the Linux kernel
 435  * during initialization.
 436  */
 437 #define CFG_BOOTMAPSZ           (8 << 20) /* Initial Memory map for Linux */
 438
 439 /*
 440  * External Bus Controller (EBC) Setup
 441  */
 442
 443 /*
 444  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
 445  */
 446 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 447 #define CFG_NAND_CS             3       /* NAND chip connected to CSx   */
 448 /* Memory Bank 0 (NOR-FLASH) initialization                             */
 449 #define CFG_EBC_PB0AP           0x03017200
 450 #define CFG_EBC_PB0CR           (CFG_FLASH_BASE | 0xda000)
 451
 452 /* Memory Bank 3 (NAND-FLASH) initialization                            */
 453 #define CFG_EBC_PB3AP           0x018003c0
 454 #define CFG_EBC_PB3CR           (CFG_NAND_ADDR | 0x1c000)
 455 #else
 456 #define CFG_NAND_CS             0       /* NAND chip connected to CSx   */
 457 /* Memory Bank 3 (NOR-FLASH) initialization                             */
 458 #define CFG_EBC_PB3AP           0x03017200
 459 #define CFG_EBC_PB3CR           (CFG_FLASH_BASE | 0xda000)
 460
 461 /* Memory Bank 0 (NAND-FLASH) initialization                            */
 462 #define CFG_EBC_PB0AP           0x018003c0
 463 #define CFG_EBC_PB0CR           (CFG_NAND_ADDR | 0x1c000)
 464 #endif
 465
 466 /* Memory Bank 2 (CPLD) initialization                                  */
 467 #define CFG_EBC_PB2AP           0x24814580
 468 #define CFG_EBC_PB2CR           (CFG_BCSR_BASE | 0x38000)
 469
 470 #define CFG_BCSR5_PCI66EN       0x80
 471
 472 /*
 473  * NAND FLASH
 474  */
 475 #define CFG_MAX_NAND_DEVICE     1
 476 #define NAND_MAX_CHIPS          1
 477 #define CFG_NAND_BASE           (CFG_NAND_ADDR + CFG_NAND_CS)
 478 #define CFG_NAND_SELECT_DEVICE  1       /* nand driver supports mutipl. chips */
 479
 480 /*
 481  * PPC440 GPIO Configuration
 482  */
 483 /* test-only: take GPIO init from pcs440ep ???? in config file */
 484 #define CFG_4xx_GPIO_TABLE { /*   Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 485 {                                                                                       \
 486 /* GPIO Core 0 */                                                                       \
 487 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7)     DMA_REQ(2)      */      \
 488 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6)     DMA_ACK(2)      */      \
 489 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5)     DMA_EOT/TC(2)   */      \
 490 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4)     DMA_REQ(3)      */      \
 491 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3)     DMA_ACK(3)      */      \
 492 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2)     DMA_EOT/TC(3)   */      \
 493 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1)                     */      \
 494 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2)                     */      \
 495 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3)                     */      \
 496 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4)                     */      \
 497 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)                    */      \
 498 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR                    */      \
 499 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12                                */      \
 500 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13                                */      \
 501 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14                                */      \
 502 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15                                */      \
 503 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4)                      */      \
 504 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5)                      */      \
 505 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6)                      */      \
 506 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7)                      */      \
 507 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0                     */      \
 508 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1                     */      \
 509 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22                                */      \
 510 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0                          */      \
 511 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2)                      */      \
 512 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3)                      */      \
 513 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26                                */      \
 514 {GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ    USB2D_RXERROR   */      \
 515 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28                USB2D_TXVALID   */      \
 516 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA   USB2D_PAD_SUSPNDM */    \
 517 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK    USB2D_XCVRSELECT*/      \
 518 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/      \
 519 },                                                                                      \
 520 {                                                                                       \
 521 /* GPIO Core 1 */                                                                       \
 522 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0  EBC_DATA(2)     */      \
 523 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1  EBC_DATA(3)     */      \
 524 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 525 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 526 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0)   UART3_SIN*/ \
 527 {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EBC_DATA(1)     UART3_SOUT*/ \
 528 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 529 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 530 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)                     */      \
 531 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)                     */      \
 532 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)                     */      \
 533 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)                     */      \
 534 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)     DMA_ACK(1)      */      \
 535 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)     DMA_EOT/TC(1)   */      \
 536 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)     DMA_REQ(0)      */      \
 537 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)     DMA_ACK(0)      */      \
 538 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)     DMA_EOT/TC(0)   */      \
 539 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 540 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 541 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 542 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 543 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 544 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 545 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 546 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 547 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 548 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 549 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 550 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 551 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 552 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 553 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 554 }                                                                                       \
 555 }
 556
 557 /*
 558  * Internal Definitions
 559  *
 560  * Boot Flags
 561  */
 562 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH     */
 563 #define BOOTFLAG_WARM   0x02    /* Software reboot                      */
 564
 565 #if defined(CONFIG_CMD_KGDB)
 566 #define CONFIG_KGDB_BAUDRATE    230400 /* speed to run kgdb serial port */
 567 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use     */
 568 #endif
 569
 570 /* pass open firmware flat tree */
 571 #define CONFIG_OF_LIBFDT        1
 572 #define CONFIG_OF_BOARD_SETUP   1
 573
 574 #endif /* __CONFIG_H */