include/configs/sequoia.h

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2006
   6  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   7  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * sequoia.h - configuration for Sequoia & Rainier boards
  27  */
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  */
  34 /* This config file is used for Sequoia (440EPx) and Rainier (440GRx)   */
  35 #ifndef CONFIG_RAINIER
  36 #define CONFIG_440EPX           1       /* Specific PPC440EPx           */
  37 #define CONFIG_HOSTNAME         sequoia
  38 #else
  39 #define CONFIG_440GRX           1       /* Specific PPC440GRx           */
  40 #define CONFIG_HOSTNAME         rainier
  41 #endif
  42 #define CONFIG_440              1       /* ... PPC440 family            */
  43 #define CONFIG_4xx              1       /* ... PPC4xx family            */
  44
  45 /*
  46  * Include common defines/options for all AMCC eval boards
  47  */
  48 #include "amcc-common.h"
  49
  50 /* Detect Sequoia PLL input clock automatically via CPLD bit            */
  51 #define CONFIG_SYS_CLK_FREQ    ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
  52                                 33333333 : 33000000)
  53
  54 /*
  55  * Define this if you want support for video console with radeon 9200 pci card
  56  * Also set TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
  57  */
  58 #undef CONFIG_VIDEO
  59
  60 #ifdef CONFIG_VIDEO
  61 /*
  62  * 44x dcache supported is working now on sequoia, but we don't enable
  63  * it yet since it needs further testing
  64  */
  65 #define CONFIG_4xx_DCACHE               /* enable dcache                */
  66 #endif
  67
  68 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  69 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
  70
  71 /*
  72  * Base addresses -- Note these are effective addresses where the actual
  73  * resources get mapped (not physical addresses).
  74  */
  75 #define CONFIG_SYS_TLB_FOR_BOOT_FLASH   0x0003
  76 #define CONFIG_SYS_BOOT_BASE_ADDR       0xf0000000
  77 #define CONFIG_SYS_FLASH_BASE           0xfc000000      /* start of FLASH       */
  78 #define CONFIG_SYS_NAND_ADDR            0xd0000000      /* NAND Flash           */
  79 #define CONFIG_SYS_OCM_BASE             0xe0010000      /* ocm                  */
  80 #define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_OCM_BASE
  81 #define CONFIG_SYS_PCI_BASE             0xe0000000      /* Internal PCI regs    */
  82 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
  83 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  84 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  85 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  86
  87 /* Don't change either of these */
  88 #define CONFIG_SYS_PERIPHERAL_BASE      0xef600000      /* internal peripherals */
  89
  90 #define CONFIG_SYS_USB2D0_BASE          0xe0000100
  91 #define CONFIG_SYS_USB_DEVICE           0xe0000000
  92 #define CONFIG_SYS_USB_HOST             0xe0000400
  93 #define CONFIG_SYS_BCSR_BASE            0xc0000000
  94
  95 /*
  96  * Initial RAM & stack pointer
  97  */
  98 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache     */
  99 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
 100 #define CONFIG_SYS_INIT_RAM_END (4 << 10)
 101 #define CONFIG_SYS_GBL_DATA_SIZE        256     /* num bytes initial data       */
 102 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 103 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_POST_WORD_ADDR
 104
 105 /*
 106  * Serial Port
 107  */
 108 #define CONFIG_SYS_EXT_SERIAL_CLOCK     11059200        /* ext. 11.059MHz clk   */
 109 /* define this if you want console on UART1 */
 110 #undef CONFIG_UART1_CONSOLE
 111
 112 /*
 113  * Environment
 114  */
 115 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 116 #define CONFIG_ENV_IS_IN_NAND           /* use NAND for environ vars    */
 117 #define CONFIG_ENV_IS_EMBEDDED          /* use embedded environment     */
 118 #elif defined(CONFIG_SYS_RAMBOOT)
 119 #define CONFIG_ENV_IS_NOWHERE           /* Store env in memory only     */
 120 #define CONFIG_ENV_SIZE         (8 << 10)
 121 /*
 122  * In RAM-booting version, we have no environment storage. So we need to
 123  * provide at least preliminary MAC addresses for the 4xx EMAC driver to
 124  * register the interfaces. Those two addresses are generated via the
 125  * tools/gen_eth_addr tool and should only be used in a closed laboratory
 126  * environment.
 127  */
 128 #define CONFIG_ETHADDR          4a:56:49:22:3e:43
 129 #define CONFIG_ETH1ADDR         02:93:53:d5:06:98
 130 #else
 131 #define CONFIG_ENV_IS_IN_FLASH          /* use FLASH for environ vars   */
 132 #endif
 133
 134 #if defined(CONFIG_CMD_FLASH)
 135 /*
 136  * FLASH related
 137  */
 138 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 139 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 140
 141 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 142
 143 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks         */
 144 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip  */
 145
 146 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)    */
 147 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)    */
 148
 149 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)   */
 150 #define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection      */
 151
 152 #define CONFIG_SYS_FLASH_EMPTY_INFO           /* print 'E' for empty sector on flinfo */
 153 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash      */
 154
 155 #ifdef CONFIG_ENV_IS_IN_FLASH
 156 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector        */
 157 #define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 158 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector   */
 159
 160 /* Address and size of Redundant Environment Sector     */
 161 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 162 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 163 #endif
 164 #endif /* CONFIG_CMD_FLASH */
 165
 166 /*
 167  * IPL (Initial Program Loader, integrated inside CPU)
 168  * Will load first 4k from NAND (SPL) into cache and execute it from there.
 169  *
 170  * SPL (Secondary Program Loader)
 171  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 172  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 173  * controller and the NAND controller so that the special U-Boot image can be
 174  * loaded from NAND to SDRAM.
 175  *
 176  * NUB (NAND U-Boot)
 177  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 178  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 179  *
 180  * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 181  * set up. While still running from cache, I experienced problems accessing
 182  * the NAND controller. sr - 2006-08-25
 183  */
 184 #define CONFIG_SYS_NAND_BOOT_SPL_SRC    0xfffff000      /* SPL location               */
 185 #define CONFIG_SYS_NAND_BOOT_SPL_SIZE   (4 << 10)       /* SPL size                   */
 186 #define CONFIG_SYS_NAND_BOOT_SPL_DST    (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here  */
 187 #define CONFIG_SYS_NAND_U_BOOT_DST      0x01000000      /* Load NUB to this addr      */
 188 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST      /* Start NUB from     */
 189                                                         /*   this addr        */
 190 #define CONFIG_SYS_NAND_BOOT_SPL_DELTA  (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 191
 192 /*
 193  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 194  */
 195 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (16 << 10)      /* Offset to RAM U-Boot image */
 196 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 << 10)     /* Size of RAM U-Boot image   */
 197
 198 /*
 199  * Now the NAND chip has to be defined (no autodetection used!)
 200  */
 201 #define CONFIG_SYS_NAND_PAGE_SIZE       512             /* NAND chip page size        */
 202 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 << 10)      /* NAND chip block size       */
 203 #define CONFIG_SYS_NAND_PAGE_COUNT      32              /* NAND chip page count       */
 204 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   5             /* Location of bad block marker */
 205 #undef CONFIG_SYS_NAND_4_ADDR_CYCLE                   /* No fourth addr used (<=32MB) */
 206
 207 #define CONFIG_SYS_NAND_ECCSIZE 256
 208 #define CONFIG_SYS_NAND_ECCBYTES        3
 209 #define CONFIG_SYS_NAND_ECCSTEPS        (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
 210 #define CONFIG_SYS_NAND_OOBSIZE 16
 211 #define CONFIG_SYS_NAND_ECCTOTAL        (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
 212 #define CONFIG_SYS_NAND_ECCPOS          {0, 1, 2, 3, 6, 7}
 213
 214 #ifdef CONFIG_ENV_IS_IN_NAND
 215 /*
 216  * For NAND booting the environment is embedded in the U-Boot image. Please take
 217  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
 218  */
 219 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 220 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 221 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 222 #endif
 223
 224 /*
 225  * DDR SDRAM
 226  */
 227 #define CONFIG_SYS_MBYTES_SDRAM        (256)    /* 256MB                        */
 228 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
 229     !defined(CONFIG_SYS_RAMBOOT)
 230 #define CONFIG_DDR_DATA_EYE             /* use DDR2 optimization        */
 231 #endif
 232 #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes     */
 233                                         /* 440EPx errata CHIP 11        */
 234
 235 /*
 236  * I2C
 237  */
 238 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 239
 240 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 241 #define CONFIG_SYS_I2C_EEPROM_ADDR      (0xa8>>1)
 242 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 243 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 244 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 245
 246 /* I2C bootstrap EEPROM */
 247 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x52
 248 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 249 #define CONFIG_4xx_CONFIG_BLOCKSIZE             16
 250
 251 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 252 #define CONFIG_DTT_LM75         1       /* ON Semi's LM75               */
 253 #define CONFIG_DTT_AD7414       1       /* use AD7414                   */
 254 #define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses             */
 255 #define CONFIG_SYS_DTT_MAX_TEMP 70
 256 #define CONFIG_SYS_DTT_LOW_TEMP -30
 257 #define CONFIG_SYS_DTT_HYSTERESIS       3
 258
 259 /*
 260  * Default environment variables
 261  */
 262 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 263         CONFIG_AMCC_DEF_ENV                                             \
 264         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 265         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
 266         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 267         CONFIG_AMCC_DEF_ENV_NAND_UPD                                    \
 268         "kernel_addr=FC000000\0"                                        \
 269         "ramdisk_addr=FC180000\0"                                       \
 270         ""
 271
 272 #define CONFIG_M88E1111_PHY     1
 273 #define CONFIG_IBM_EMAC4_V4     1
 274 #define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 275
 276 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 277 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 278
 279 #define CONFIG_HAS_ETH0
 280 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 281 #define CONFIG_PHY1_ADDR        1
 282
 283 /* USB */
 284 #ifdef CONFIG_440EPX
 285
 286 #undef CONFIG_USB_EHCI  /* OHCI by default */
 287
 288 #ifdef CONFIG_USB_EHCI
 289 #define CONFIG_USB_EHCI_PPC4XX
 290 #define CONFIG_SYS_PPC4XX_USB_ADDR      0xe0000300
 291 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 292 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 293 #define CONFIG_EHCI_DESC_BIG_ENDIAN
 294 #ifdef CONFIG_4xx_DCACHE
 295 #define CONFIG_EHCI_DCACHE
 296 #endif
 297 #else /* CONFIG_USB_EHCI */
 298 #define CONFIG_USB_OHCI_NEW
 299 #define CONFIG_SYS_OHCI_BE_CONTROLLER
 300
 301 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
 302 #define CONFIG_SYS_USB_OHCI_CPU_INIT    1
 303 #define CONFIG_SYS_USB_OHCI_REGS_BASE   CONFIG_SYS_USB_HOST
 304 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ppc440"
 305 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 306 #endif
 307
 308 #define CONFIG_USB_STORAGE
 309 /* Comment this out to enable USB 1.1 device */
 310 #define USB_2_0_DEVICE
 311
 312 #endif /* CONFIG_440EPX */
 313
 314 /* Partitions */
 315 #define CONFIG_MAC_PARTITION
 316 #define CONFIG_DOS_PARTITION
 317 #define CONFIG_ISO_PARTITION
 318
 319 /*
 320  * Commands additional to the ones defined in amcc-common.h
 321  */
 322 #define CONFIG_CMD_CHIP_CONFIG
 323 #define CONFIG_CMD_DTT
 324 #define CONFIG_CMD_FAT
 325 #define CONFIG_CMD_NAND
 326 #define CONFIG_CMD_PCI
 327 #define CONFIG_CMD_SDRAM
 328
 329 #ifdef CONFIG_440EPX
 330 #define CONFIG_CMD_USB
 331 #endif
 332
 333 #ifndef CONFIG_RAINIER
 334 #define CONFIG_SYS_POST_FPU_ON          CONFIG_SYS_POST_FPU
 335 #else
 336 #define CONFIG_SYS_POST_FPU_ON          0
 337 #endif
 338
 339 /*
 340  * Don't run the memory POST on the NAND-booting version. It will
 341  * overwrite part of the U-Boot image which is already loaded from NAND
 342  * to SDRAM.
 343  */
 344 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
 345 #define CONFIG_SYS_POST_MEMORY_ON       0
 346 #else
 347 #define CONFIG_SYS_POST_MEMORY_ON       CONFIG_SYS_POST_MEMORY
 348 #endif
 349
 350 /* POST support */
 351 #define CONFIG_POST             (CONFIG_SYS_POST_CACHE     | \
 352                                  CONFIG_SYS_POST_CPU       | \
 353                                  CONFIG_SYS_POST_ETHER     | \
 354                                  CONFIG_SYS_POST_FPU_ON    | \
 355                                  CONFIG_SYS_POST_I2C       | \
 356                                  CONFIG_SYS_POST_MEMORY_ON | \
 357                                  CONFIG_SYS_POST_SPR       | \
 358                                  CONFIG_SYS_POST_UART)
 359
 360 #define CONFIG_SYS_POST_WORD_ADDR       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 361 #define CONFIG_LOGBUFFER
 362 #define CONFIG_SYS_POST_CACHE_ADDR      0x7fff0000      /* free virtual address     */
 363
 364 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* Otherwise it catches logbuffer as output */
 365
 366 #define CONFIG_SUPPORT_VFAT
 367
 368 /*
 369  * PCI stuff
 370  */
 371 /* General PCI */
 372 #define CONFIG_PCI                      /* include pci support          */
 373 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 374 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  0       /* to avoid problems with PNP   */
 375 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 376 #define CONFIG_SYS_PCI_TARGBASE 0x80000000      /* PCIaddr mapped to    */
 377                                                 /*   CONFIG_SYS_PCI_MEMBASE     */
 378 /* Board-specific PCI */
 379 #define CONFIG_SYS_PCI_TARGET_INIT
 380 #define CONFIG_SYS_PCI_MASTER_INIT
 381 #define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
 382
 383 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC                         */
 384 #define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe   /* Whatever                     */
 385
 386 /*
 387  * External Bus Controller (EBC) Setup
 388  */
 389
 390 /*
 391  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
 392  */
 393 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
 394     !defined(CONFIG_SYS_RAMBOOT)
 395 #define CONFIG_SYS_NAND_CS              3       /* NAND chip connected to CSx   */
 396 /* Memory Bank 0 (NOR-FLASH) initialization                             */
 397 #define CONFIG_SYS_EBC_PB0AP            0x03017200
 398 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 399
 400 /* Memory Bank 3 (NAND-FLASH) initialization                            */
 401 #define CONFIG_SYS_EBC_PB3AP            0x018003c0
 402 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 403 #else
 404 #define CONFIG_SYS_NAND_CS              0       /* NAND chip connected to CSx   */
 405 /* Memory Bank 3 (NOR-FLASH) initialization                             */
 406 #define CONFIG_SYS_EBC_PB3AP            0x03017200
 407 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 408
 409 /* Memory Bank 0 (NAND-FLASH) initialization                            */
 410 #define CONFIG_SYS_EBC_PB0AP            0x018003c0
 411 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 412 #endif
 413
 414 /* Memory Bank 2 (CPLD) initialization                                  */
 415 #define CONFIG_SYS_EBC_PB2AP            0x24814580
 416 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_BCSR_BASE | 0x38000)
 417
 418 #define CONFIG_SYS_BCSR5_PCI66EN        0x80
 419
 420 /*
 421  * NAND FLASH
 422  */
 423 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 424 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 425 #define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips */
 426
 427 /*
 428  * PPC440 GPIO Configuration
 429  */
 430 /* test-only: take GPIO init from pcs440ep ???? in config file */
 431 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 432 {                                                                                       \
 433 /* GPIO Core 0 */                                                                       \
 434 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7)     DMA_REQ(2)      */      \
 435 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6)     DMA_ACK(2)      */      \
 436 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5)     DMA_EOT/TC(2)   */      \
 437 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4)     DMA_REQ(3)      */      \
 438 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3)     DMA_ACK(3)      */      \
 439 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2)     DMA_EOT/TC(3)   */      \
 440 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1)                     */      \
 441 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2)                     */      \
 442 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3)                     */      \
 443 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4)                     */      \
 444 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)                    */      \
 445 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR                    */      \
 446 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12                                */      \
 447 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13                                */      \
 448 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14                                */      \
 449 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15                                */      \
 450 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4)                      */      \
 451 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5)                      */      \
 452 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6)                      */      \
 453 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7)                      */      \
 454 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0                     */      \
 455 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1                     */      \
 456 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22                                */      \
 457 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0                          */      \
 458 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2)                      */      \
 459 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3)                      */      \
 460 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26                                */      \
 461 {GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ    USB2D_RXERROR   */      \
 462 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28                USB2D_TXVALID   */      \
 463 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA   USB2D_PAD_SUSPNDM */    \
 464 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK    USB2D_XCVRSELECT*/      \
 465 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/      \
 466 },                                                                                      \
 467 {                                                                                       \
 468 /* GPIO Core 1 */                                                                       \
 469 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0  EBC_DATA(2)     */      \
 470 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1  EBC_DATA(3)     */      \
 471 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
 472 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 473 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N    EBC_DATA(0)     UART3_SIN*/ \
 474 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N    EBC_DATA(1)     UART3_SOUT*/ \
 475 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT    */      \
 476 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN      */      \
 477 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)                     */      \
 478 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)                     */      \
 479 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)                     */      \
 480 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)                     */      \
 481 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)     DMA_ACK(1)      */      \
 482 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)     DMA_EOT/TC(1)   */      \
 483 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)     DMA_REQ(0)      */      \
 484 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)     DMA_ACK(0)      */      \
 485 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)     DMA_EOT/TC(0)   */      \
 486 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 487 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 488 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 489 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 490 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 491 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 492 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 493 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 494 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 495 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 496 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 497 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 498 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 499 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 500 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 501 }                                                                                       \
 502 }
 503
 504 #ifdef CONFIG_VIDEO
 505 #define CONFIG_BIOSEMU                  /* x86 bios emulator for vga bios */
 506 #define CONFIG_ATI_RADEON_FB            /* use radeon framebuffer driver */
 507 #define VIDEO_IO_OFFSET                 0xe8000000
 508 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS          VIDEO_IO_OFFSET
 509 #define CONFIG_VIDEO_SW_CURSOR
 510 #define CONFIG_VIDEO_LOGO
 511 #define CONFIG_CFB_CONSOLE
 512 #define CONFIG_SPLASH_SCREEN
 513 #define CONFIG_VGA_AS_SINGLE_DEVICE
 514 #define CONFIG_CMD_BMP
 515 #endif
 516
 517 #endif /* __CONFIG_H */