include/configs/sh7785lcr.h

   1 /*
   2  * Configuation settings for the Renesas Technology R0P7785LC0011RL board
   3  *
   4  * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef __SH7785LCR_H
  26 #define __SH7785LCR_H
  27
  28 #undef DEBUG
  29 #define CONFIG_SH               1
  30 #define CONFIG_SH4A             1
  31 #define CONFIG_CPU_SH7785       1
  32 #define CONFIG_SH7785LCR        1
  33
  34 #define CONFIG_CMD_FLASH
  35 #define CONFIG_CMD_MEMORY
  36 #define CONFIG_CMD_PCI
  37 #define CONFIG_CMD_NET
  38 #define CONFIG_CMD_PING
  39 #define CONFIG_CMD_NFS
  40 #define CONFIG_CMD_DFL
  41 #define CONFIG_CMD_SDRAM
  42 #define CONFIG_CMD_RUN
  43 #define CONFIG_CMD_SAVEENV
  44
  45 #define CONFIG_CMD_USB
  46 #define CONFIG_USB_STORAGE
  47 #define CONFIG_CMD_EXT2
  48 #define CONFIG_CMD_FAT
  49 #define CONFIG_DOS_PARTITION
  50 #define CONFIG_MAC_PARTITION
  51
  52 #define CONFIG_BAUDRATE         115200
  53 #define CONFIG_BOOTDELAY        3
  54 #define CONFIG_BOOTARGS         "console=ttySC1,115200 root=/dev/nfs ip=dhcp"
  55
  56 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  57         "bootdevice=0:1\0"                                              \
  58         "usbload=usb reset;usbboot;usb stop;bootm\0"
  59
  60 #define CONFIG_VERSION_VARIABLE
  61 #undef  CONFIG_SHOW_BOOT_PROGRESS
  62
  63 /* MEMORY */
  64 #if defined(CONFIG_SH_32BIT)
  65 #define SH7785LCR_SDRAM_PHYS_BASE       (0x48000000)
  66 #define SH7785LCR_SDRAM_BASE            (0x88000000)
  67 #define SH7785LCR_SDRAM_SIZE            (384 * 1024 * 1024)
  68 #define SH7785LCR_FLASH_BASE_1          (0xa0000000)
  69 #define SH7785LCR_FLASH_BANK_SIZE       (64 * 1024 * 1024)
  70 #define SH7785LCR_USB_BASE              (0xa6000000)
  71 #else
  72 #define SH7785LCR_SDRAM_BASE            (0x08000000)
  73 #define SH7785LCR_SDRAM_SIZE            (128 * 1024 * 1024)
  74 #define SH7785LCR_FLASH_BASE_1          (0xa0000000)
  75 #define SH7785LCR_FLASH_BANK_SIZE       (64 * 1024 * 1024)
  76 #define SH7785LCR_USB_BASE              (0xb4000000)
  77 #endif
  78
  79 #define CONFIG_SYS_LONGHELP
  80 #define CONFIG_SYS_PROMPT               "=> "
  81 #define CONFIG_SYS_CBSIZE               256
  82 #define CONFIG_SYS_PBSIZE               256
  83 #define CONFIG_SYS_MAXARGS              16
  84 #define CONFIG_SYS_BARGSIZE             512
  85 #define CONFIG_SYS_BAUDRATE_TABLE       { 115200 }
  86
  87 /* SCIF */
  88 #define CONFIG_SCIF_CONSOLE     1
  89 #define CONFIG_CONS_SCIF1       1
  90 #define CONFIG_SCIF_EXT_CLOCK   1
  91 #undef  CONFIG_SYS_CONSOLE_INFO_QUIET
  92 #undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
  93 #undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
  94
  95
  96 #define CONFIG_SYS_MEMTEST_START        (SH7785LCR_SDRAM_BASE)
  97 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
  98                                         (SH7785LCR_SDRAM_SIZE) - \
  99                                          4 * 1024 * 1024)
 100 #undef  CONFIG_SYS_ALT_MEMTEST
 101 #undef  CONFIG_SYS_MEMTEST_SCRATCH
 102 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
 103
 104 #define CONFIG_SYS_SDRAM_BASE   (SH7785LCR_SDRAM_BASE)
 105 #define CONFIG_SYS_SDRAM_SIZE   (SH7785LCR_SDRAM_SIZE)
 106 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
 107
 108 #define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1)
 109 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 110 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 111 #define CONFIG_SYS_GBL_DATA_SIZE        (256)
 112 #define CONFIG_SYS_BOOTMAPSZ            (8 * 1024 * 1024)
 113
 114 /* FLASH */
 115 #define CONFIG_FLASH_CFI_DRIVER
 116 #define CONFIG_SYS_FLASH_CFI
 117 #undef  CONFIG_SYS_FLASH_QUIET_TEST
 118 #define CONFIG_SYS_FLASH_EMPTY_INFO
 119 #define CONFIG_SYS_FLASH_BASE           (SH7785LCR_FLASH_BASE_1)
 120 #define CONFIG_SYS_MAX_FLASH_SECT       512
 121
 122 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 123 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE + \
 124                                  (0 * SH7785LCR_FLASH_BANK_SIZE) }
 125
 126 #define CONFIG_SYS_FLASH_ERASE_TOUT     (3 * 1000)
 127 #define CONFIG_SYS_FLASH_WRITE_TOUT     (3 * 1000)
 128 #define CONFIG_SYS_FLASH_LOCK_TOUT      (3 * 1000)
 129 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (3 * 1000)
 130
 131 #undef  CONFIG_SYS_FLASH_PROTECTION
 132 #undef  CONFIG_SYS_DIRECT_FLASH_TFTP
 133
 134 /* R8A66597 */
 135 #define CONFIG_USB_R8A66597_HCD
 136 #define CONFIG_R8A66597_BASE_ADDR       SH7785LCR_USB_BASE
 137 #define CONFIG_R8A66597_XTAL            0x0000  /* 12MHz */
 138 #define CONFIG_R8A66597_LDRV            0x8000  /* 3.3V */
 139 #define CONFIG_R8A66597_ENDIAN          0x0000  /* little */
 140
 141 /* PCI Controller */
 142 #define CONFIG_PCI
 143 #define CONFIG_SH4_PCI
 144 #define CONFIG_SH7780_PCI
 145 #if defined(CONFIG_SH_32BIT)
 146 #define CONFIG_SH7780_PCI_LSR   0x1ff00001
 147 #define CONFIG_SH7780_PCI_LAR   0x5f000000
 148 #define CONFIG_SH7780_PCI_BAR   0x5f000000
 149 #else
 150 #define CONFIG_SH7780_PCI_LSR   0x07f00001
 151 #define CONFIG_SH7780_PCI_LAR   CONFIG_SYS_SDRAM_SIZE
 152 #define CONFIG_SH7780_PCI_BAR   CONFIG_SYS_SDRAM_SIZE
 153 #endif
 154 #define CONFIG_PCI_PNP
 155 #define CONFIG_PCI_SCAN_SHOW    1
 156
 157 #define CONFIG_PCI_MEM_BUS      0xFD000000      /* Memory space base addr */
 158 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
 159 #define CONFIG_PCI_MEM_SIZE     0x01000000      /* Size of Memory window */
 160
 161 #define CONFIG_PCI_IO_BUS       0xFE200000      /* IO space base address */
 162 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
 163 #define CONFIG_PCI_IO_SIZE      0x00200000      /* Size of IO window */
 164
 165 #if defined(CONFIG_SH_32BIT)
 166 #define CONFIG_PCI_SYS_PHYS     SH7785LCR_SDRAM_PHYS_BASE
 167 #else
 168 #define CONFIG_PCI_SYS_PHYS     CONFIG_SYS_SDRAM_BASE
 169 #endif
 170 #define CONFIG_PCI_SYS_BUS      CONFIG_SYS_SDRAM_BASE
 171 #define CONFIG_PCI_SYS_SIZE     CONFIG_SYS_SDRAM_SIZE
 172
 173 /* Network device (RTL8169) support */
 174 #define CONFIG_NET_MULTI
 175 #define CONFIG_RTL8169
 176
 177 /* ENV setting */
 178 #define CONFIG_ENV_IS_IN_FLASH
 179 #define CONFIG_ENV_OVERWRITE    1
 180 #define CONFIG_ENV_SECT_SIZE    (256 * 1024)
 181 #define CONFIG_ENV_SIZE         (CONFIG_ENV_SECT_SIZE)
 182 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 183 #define CONFIG_ENV_OFFSET               (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
 184 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SECT_SIZE)
 185
 186 /* Board Clock */
 187 /* The SCIF used external clock. system clock only used timer. */
 188 #define CONFIG_SYS_CLK_FREQ     50000000
 189 #define CONFIG_SYS_TMU_CLK_DIV          4
 190 #define CONFIG_SYS_HZ           1000
 191
 192 #endif  /* __SH7785LCR_H */