include/configs/shannon.h

   1 /*
   2  * (C) Copyright 2002
   3  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4  * Alex Zuepke <azu@sysgo.de>
   5  *
   6  * Configuation settings for the Shannon/TuxScreen/IS2630 WebPhone Board.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * Since we use the Inferno-Loader to bring us to live,
  32  * we skip the lowlevel init stuff.
  33  * But U-Boot still relocates itself into RAM
  34  */
  35 #define CONFIG_INFERNO                  /* we are using the inferno bootldr */
  36 #define CONFIG_SKIP_LOWLEVEL_INIT       1
  37 #undef  CONFIG_SKIP_RELOCATE_UBOOT
  38
  39 /*
  40  * High Level Configuration Options
  41  * (easy to change)
  42  */
  43 #define CONFIG_SA1100           1       /* This is an SA1100 CPU        */
  44 #define CONFIG_SHANNON          1       /* on an SHANNON/TuxScreen Board      */
  45
  46 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
  47
  48 /*
  49  * Size of malloc() pool
  50  */
  51 #define CFG_MALLOC_LEN          (CFG_ENV_SIZE + 128*1024)
  52 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
  53
  54 /*
  55  * Hardware drivers
  56  */
  57 #define CONFIG_DRIVER_3C589     1
  58
  59 /*
  60  * select serial console configuration
  61  */
  62 #define CONFIG_SERIAL3          1       /* we use SERIAL 3  */
  63
  64 /* allow to overwrite serial and ethaddr */
  65 #define CONFIG_ENV_OVERWRITE
  66
  67 #define CONFIG_BAUDRATE         115200
  68
  69 #if 0 /* XXX - cannot test IDE anyway, so disabled for now - wd */
  70 #define CONFIG_COMMANDS         (CONFIG_CMD_DFL | \
  71                                  CFG_CMD_PCMCIA | \
  72                                  CFG_CMD_IDE)
  73 #endif /* 0 */
  74
  75 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  76 #include <cmd_confdefs.h>
  77
  78 #define CONFIG_BOOTDELAY        3
  79 #define CONFIG_BOOTARGS         "root=ramfs devfs=mount console=ttySA0,115200"
  80 #define CONFIG_NETMASK          255.255.0.0
  81 #define CONFIG_BOOTCOMMAND      "help"
  82
  83 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  84 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
  85 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
  86 #endif
  87
  88 /*
  89  * Miscellaneous configurable options
  90  */
  91 #define CFG_LONGHELP                            /* undef to save memory         */
  92 #define CFG_PROMPT              "TuxScreen # "  /* Monitor Command Prompt       */
  93 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
  94 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  95 #define CFG_MAXARGS             16              /* max number of command args   */
  96 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
  97
  98 #define CFG_MEMTEST_START       0xc0400000      /* memtest works on     */
  99 #define CFG_MEMTEST_END         0xc0800000      /* 4 ... 8 MB in DRAM   */
 100
 101 #undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 102
 103 #define CFG_LOAD_ADDR           0xd0000000      /* default load address */
 104
 105 #define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
 106 #define CFG_CPUSPEED            0x09            /* 190 MHz for Shannon */
 107
 108                                                 /* valid baudrates */
 109 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 110
 111 #define CONFIG_DOS_PARTITION    1               /* DOS partitiion support */
 112
 113 /*-----------------------------------------------------------------------
 114  * Stack sizes
 115  *
 116  * The stack sizes are set up in start.S using the settings below
 117  */
 118 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 119 #ifdef CONFIG_USE_IRQ
 120 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 121 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 122 #endif
 123
 124 /*-----------------------------------------------------------------------
 125  * Physical Memory Map
 126  */
 127 /* BE CAREFUL */
 128 #define CONFIG_NR_DRAM_BANKS    4          /* we have 4 banks of EDORAM */
 129 #define PHYS_SDRAM_1            0xc0000000 /* RAM Bank #1 */
 130 #define PHYS_SDRAM_1_SIZE       0x00400000 /* 4 MB */
 131 #define PHYS_SDRAM_2            0xc8000000 /* RAM Bank #2 */
 132 #define PHYS_SDRAM_2_SIZE       0x00400000 /* 4 MB */
 133 #define PHYS_SDRAM_3            0xd0000000 /* RAM Bank #3 */
 134 #define PHYS_SDRAM_3_SIZE       0x00400000 /* 4 MB */
 135 #define PHYS_SDRAM_4            0xd8000000 /* RAM Bank #4 */
 136 #define PHYS_SDRAM_4_SIZE       0x00400000 /* 4 MB */
 137
 138
 139 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
 140 #define PHYS_FLASH_SIZE         0x00400000 /* 4 MB */
 141
 142 #define CFG_FLASH_BASE          PHYS_FLASH_1
 143
 144 /*-----------------------------------------------------------------------
 145  * FLASH and environment organization
 146  */
 147 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 148 #define CFG_MAX_FLASH_SECT      (31+4)  /* max number of sectors on one chip    */
 149
 150 /* timeout values are in ticks */
 151 #define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase */
 152 #define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write */
 153
 154 #define CFG_ENV_IS_IN_FLASH     1
 155 #ifdef CONFIG_INFERNO
 156 /* we take the last sector, 128 KB in size, but we only use 4 KB of it for stack reasons */
 157 #define CFG_ENV_ADDR            (PHYS_FLASH_1 + 0x003E0000)     /* Addr of Environment Sector   */
 158 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 159 #else
 160 #define CFG_ENV_ADDR            (PHYS_FLASH_1 + 0x1C000)        /* Addr of Environment Sector   */
 161 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 162 #endif
 163
 164 /*-----------------------------------------------------------------------
 165  * PCMCIA stuff
 166  *-----------------------------------------------------------------------
 167  *
 168  */
 169
 170 /* we pick the upper one */
 171
 172 #define CONFIG_PCMCIA_SLOT_A
 173
 174 #define CFG_PCMCIA_IO_ADDR      (0x20000000)
 175 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 176 #define CFG_PCMCIA_DMA_ADDR     (0x24000000)
 177 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 178 #define CFG_PCMCIA_ATTRB_ADDR   (0x2C000000)
 179 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 180 #define CFG_PCMCIA_MEM_ADDR     (0x28000000)
 181 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 182
 183 /* in fact, MEM and ATTRB are swapped - has to be corrected soon in cmd_pcmcia or so */
 184
 185 /*-----------------------------------------------------------------------
 186  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 187  *-----------------------------------------------------------------------
 188  */
 189
 190 #define CONFIG_IDE_PCCARD       1       /* Use IDE with PC Card Adapter */
 191
 192 #undef  CONFIG_IDE_PCMCIA               /* Direct IDE    not supported  */
 193 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 194 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 195
 196 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 197 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 198
 199 #define CFG_ATA_IDE0_OFFSET     0x0000
 200
 201 /* it's simple, all regs are in I/O space */
 202 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_ATTRB_ADDR
 203
 204 /* Offset for data I/O                  */
 205 #define CFG_ATA_DATA_OFFSET     0
 206
 207 /* Offset for normal register accesses  */
 208 #define CFG_ATA_REG_OFFSET      0
 209
 210 /* Offset for alternate registers       */
 211 #define CFG_ATA_ALT_OFFSET      0
 212
 213 /*-----------------------------------------------------------------------
 214  */
 215
 216 #endif  /* __CONFIG_H */