include/configs/smmaco4.h

   1 /*
   2  * (C) Copyright 2003-2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004-2005
   6  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * High Level Configuration Options
  32  * (easy to change)
  33  */
  34
  35 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  36 #define CONFIG_MPC5200          1       /* (more precisely an MPC5200 CPU) */
  37 #define CONFIG_TQM5200          1       /* ... on TQM5200 module */
  38 #undef CONFIG_TQM5200_REV100            /*  define for revision 100 modules */
  39
  40 #define CFG_MPC5XXX_CLKIN       33000000 /* ... running at 33.000000MHz */
  41
  42 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH  */
  43 #define BOOTFLAG_WARM           0x02    /* Software reboot           */
  44
  45 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs */
  46 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  47 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
  48 #endif
  49
  50 /*
  51  * Serial console configuration
  52  */
  53 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  54 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  55 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  56
  57 /* Partitions */
  58 #define CONFIG_MAC_PARTITION
  59 #define CONFIG_DOS_PARTITION
  60 #define CONFIG_ISO_PARTITION
  61
  62 /* POST support */
  63 #define CONFIG_POST             (CFG_POST_MEMORY   | \
  64                                  CFG_POST_CPU      | \
  65                                  CFG_POST_I2C)
  66
  67 #ifdef CONFIG_POST
  68 #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
  69 /* preserve space for the post_word at end of on-chip SRAM */
  70 #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
  71 #else
  72 #define CFG_CMD_POST_DIAG 0
  73 #endif
  74
  75 /*
  76  * Supported commands
  77  */
  78 #define CONFIG_COMMANDS        (CONFIG_CMD_DFL  | \
  79                                 CFG_CMD_ASKENV  | \
  80                                 CFG_CMD_DATE    | \
  81                                 CFG_CMD_DHCP    | \
  82                                 CFG_CMD_ECHO    | \
  83                                 CFG_CMD_EEPROM  | \
  84                                 CFG_CMD_I2C     | \
  85                                 CFG_CMD_JFFS2   | \
  86                                 CFG_CMD_MII     | \
  87                                 CFG_CMD_NFS     | \
  88                                 CFG_CMD_PING    | \
  89                                 CFG_CMD_POST_DIAG | \
  90                                 CFG_CMD_REGINFO | \
  91                                 CFG_CMD_SNTP    )
  92
  93 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  94 #include <cmd_confdefs.h>
  95
  96 #define CONFIG_TIMESTAMP                /* display image timestamps */
  97
  98 #if (TEXT_BASE == 0xFC000000)           /* Boot low */
  99 #   define CFG_LOWBOOT          1
 100 #endif
 101
 102 /*
 103  * Autobooting
 104  */
 105 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 106
 107 #define CONFIG_PREBOOT  "echo;" \
 108         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 109         "echo"
 110
 111 #undef  CONFIG_BOOTARGS
 112
 113 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 114         "netdev=eth0\0"                                                 \
 115         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 116         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 117         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 118                 "nfsroot=${serverip}:${rootpath}\0"                     \
 119         "addip=setenv bootargs ${bootargs} "                            \
 120                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 121                 ":${hostname}:${netdev}:off panic=1\0"                  \
 122         "flash_self=run ramargs addip;"                                 \
 123                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 124         "flash_nfs=run nfsargs addip;"                                  \
 125                 "bootm ${kernel_addr}\0"                                \
 126         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 127         "bootfile=/tftpboot/smmaco4/uImage\0"                           \
 128         "load=tftp 200000 ${u-boot}\0"                                  \
 129         "u-boot=/tftpboot/smmaco4/u-boot.bin\0"                         \
 130         "update=protect off FC000000 FC05FFFF;"                         \
 131                 "erase FC000000 FC05FFFF;"                              \
 132                 "cp.b 200000 FC000000 ${filesize};"                     \
 133                 "protect on FC000000 FC05FFFF\0"                        \
 134         ""
 135
 136 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 137
 138 /*
 139  * IPB Bus clocking configuration.
 140  */
 141 #define CFG_IPBSPEED_133                /* define for 133MHz speed */
 142
 143 #if defined(CFG_IPBSPEED_133)
 144 /*
 145  * PCI Bus clocking configuration
 146  *
 147  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 148  * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
 149  * been tested with a IPB Bus Clock of 66 MHz.
 150  */
 151 #define CFG_PCISPEED_66                 /* define for 66MHz speed */
 152 #endif
 153
 154 /*
 155  * I2C configuration
 156  */
 157 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 158 #ifdef CONFIG_TQM5200_REV100
 159 #define CFG_I2C_MODULE          1       /* Select I2C module #1 for rev. 100 board */
 160 #else
 161 #define CFG_I2C_MODULE          2       /* Select I2C module #2 for all other revs */
 162 #endif
 163
 164 /*
 165  * I2C clock frequency
 166  *
 167  * Please notice, that the resulting clock frequency could differ from the
 168  * configured value. This is because the I2C clock is derived from system
 169  * clock over a frequency divider with only a few divider values. U-boot
 170  * calculates the best approximation for CFG_I2C_SPEED. However the calculated
 171  * approximation allways lies below the configured value, never above.
 172  */
 173 #define CFG_I2C_SPEED           100000 /* 100 kHz */
 174 #define CFG_I2C_SLAVE           0x7F
 175
 176 /*
 177  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
 178  * also). For other EEPROMs configuration should be verified. On Mini-FAP the
 179  * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
 180  * same configuration could be used.
 181  */
 182 #define CFG_I2C_EEPROM_ADDR             0x50    /* 1010000x */
 183 #define CFG_I2C_EEPROM_ADDR_LEN         2
 184 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* =32 Bytes per write */
 185 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  20
 186
 187 /*
 188  * Flash configuration
 189  */
 190 #define CFG_FLASH_BASE          TEXT_BASE /* 0xFC000000 */
 191
 192 /* use CFI flash driver if no module variant is spezified */
 193 #define CFG_FLASH_CFI           1       /* Flash is CFI conformant */
 194 #define CFG_FLASH_CFI_DRIVER    1       /* Use the common driver */
 195 #define CFG_FLASH_BANKS_LIST    { CFG_BOOTCS_START }
 196 #define CFG_FLASH_EMPTY_INFO
 197 #define CFG_FLASH_SIZE          0x04000000 /* 64 MByte */
 198 #define CFG_MAX_FLASH_SECT      512     /* max num of sects on one chip */
 199 #undef CFG_FLASH_USE_BUFFER_WRITE       /* not supported yet for AMD */
 200
 201 #if !defined(CFG_LOWBOOT)
 202 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
 203 #else   /* CFG_LOWBOOT */
 204 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00060000)
 205 #endif  /* CFG_LOWBOOT */
 206 #define CFG_MAX_FLASH_BANKS     1       /* max num of flash banks
 207                                            (= chip selects) */
 208 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 209 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 210
 211 /* Dynamic MTD partition support */
 212 #define CONFIG_JFFS2_CMDLINE
 213 #define MTDIDS_DEFAULT          "nor0=TQM5200-0"
 214 #define MTDPARTS_DEFAULT        "mtdparts=TQM5200-0:640k(firmware),"    \
 215                                                 "1408k(kernel),"        \
 216                                                 "2m(initrd),"           \
 217                                                 "4m(small-fs),"         \
 218                                                 "16m(big-fs),"          \
 219                                                 "8m(misc)"
 220
 221 /*
 222  * Environment settings
 223  */
 224 #define CFG_ENV_IS_IN_FLASH     1
 225 #define CFG_ENV_SIZE            0x10000
 226 #define CFG_ENV_SECT_SIZE       0x20000
 227 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 228 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 229
 230 /*
 231  * Memory map
 232  */
 233 #define CFG_MBAR                0xF0000000
 234 #define CFG_SDRAM_BASE          0x00000000
 235 #define CFG_DEFAULT_MBAR        0x80000000
 236
 237 /* Use ON-Chip SRAM until RAM will be available */
 238 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 239 #ifdef CONFIG_POST
 240 /* preserve space for the post_word at end of on-chip SRAM */
 241 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_POST_SIZE
 242 #else
 243 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_SIZE
 244 #endif
 245
 246
 247 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 248 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 249 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 250
 251 #define CFG_MONITOR_BASE        TEXT_BASE
 252 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 253 #   define CFG_RAMBOOT          1
 254 #endif
 255
 256 #define CFG_MONITOR_LEN         (384 << 10)     /* Reserve 384 kB for Monitor   */
 257 #define CFG_MALLOC_LEN          (256 << 10)     /* Reserve 256 kB for malloc()  */
 258 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 259
 260 /*
 261  * Ethernet configuration
 262  */
 263 #define CONFIG_MPC5xxx_FEC      1
 264 /*
 265  * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 266  */
 267 /* #define CONFIG_FEC_10MBIT 1 */
 268 #define CONFIG_PHY_ADDR         0x00
 269
 270 /*
 271  * GPIO configuration
 272  *
 273  * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
 274  *      Bit 0 (mask: 0x80000000): 1
 275  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 276  *      00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
 277  *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
 278  *            Use for REV200 STK52XX boards. Do not use with REV100 modules
 279  *            (because, there I2C1 is used as I2C bus)
 280  * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 281  * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
 282  *      000 -> All PSC2 pins are GIOPs
 283  *      001 -> CAN1/2 on PSC2 pins
 284  *             Use for REV100 STK52xx boards
 285  * use PSC6:
 286  *   on STK52xx:
 287  *      use as UART. Pins PSC6_0 to PSC6_3 are used.
 288  *      Bits 9:11 (mask: 0x00700000):
 289  *         101 -> PSC6 : Extended POST test is not available
 290  *   on MINI-FAP and TQM5200_IB:
 291  *      use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
 292  *         000 -> PSC6 could not be used as UART, CODEC or IrDA
 293  *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
 294  *   tests.
 295  */
 296 #if defined (CONFIG_MINIFAP)
 297 # define CFG_GPS_PORT_CONFIG    0x91000004
 298 #elif defined (CONFIG_STK52XX)
 299 # if defined (CONFIG_STK52XX_REV100)
 300 #  define CFG_GPS_PORT_CONFIG   0x81500014
 301 # else /* STK52xx REV200 and above */
 302 #  if defined (CONFIG_TQM5200_REV100)
 303 #   error TQM5200 REV100 not supported on STK52XX REV200 or above
 304 #  else/* TQM5200 REV200 and above */
 305 #   define CFG_GPS_PORT_CONFIG  0x91500004
 306 #  endif
 307 # endif
 308 #else  /* TMQ5200 Inbetriebnahme-Board */
 309 # define CFG_GPS_PORT_CONFIG    0x81000004
 310 #endif
 311
 312 /*
 313  * RTC configuration
 314  */
 315 #define CONFIG_RTC_MPC5200      1       /* use internal MPC5200 RTC */
 316
 317 /*
 318  * Miscellaneous configurable options
 319  */
 320 #define CFG_LONGHELP                    /* undef to save memory     */
 321 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt   */
 322 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 323 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size  */
 324 #else
 325 #define CFG_CBSIZE              256     /* Console I/O Buffer Size  */
 326 #endif
 327 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 328 #define CFG_MAXARGS             16      /* max number of command args   */
 329 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 330
 331 /* Enable an alternate, more extensive memory test */
 332 #define CFG_ALT_MEMTEST
 333
 334 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 335 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 336
 337 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 338
 339 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 340
 341 /*
 342  * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
 343  * which is normally part of the default commands (CFV_CMD_DFL)
 344  */
 345 #define CONFIG_LOOPW
 346
 347 /*
 348  * Various low-level settings
 349  */
 350 #if defined(CONFIG_MPC5200)
 351 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 352 #define CFG_HID0_FINAL          HID0_ICE
 353 #else
 354 #define CFG_HID0_INIT           0
 355 #define CFG_HID0_FINAL          0
 356 #endif
 357
 358 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 359 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 360 #ifdef CFG_PCISPEED_66
 361 #define CFG_BOOTCS_CFG          0x0008DF30 /* for pci_clk  = 66 MHz */
 362 #else
 363 #define CFG_BOOTCS_CFG          0x0004DF30 /* for pci_clk = 33 MHz */
 364 #endif
 365 #define CFG_CS0_START           CFG_FLASH_BASE
 366 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 367
 368 #define CFG_CS_BURST            0x00000000
 369 #define CFG_CS_DEADCYCLE        0x33333311      /* 1 dead cycle for flash and SM501 */
 370
 371 #define CFG_RESET_ADDRESS       0xff000000
 372
 373 #endif /* __CONFIG_H */