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ARM: atmel: boards: use default CONFIG_SYS_PBSIZE
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1 /*
2 * Copyright (C) ST-Ericsson SA 2009
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 /*
11 * #define DEBUG 1
12 */
13
14 #define CONFIG_SKIP_LOWLEVEL_INIT
15 #define CONFIG_SNOWBALL
16 #define CONFIG_SYS_ICACHE_OFF
17 #define CONFIG_SYS_DCACHE_OFF
18 #define CONFIG_ARCH_CPU_INIT
19 #define CONFIG_BOARD_LATE_INIT
20
21 /*
22 * High Level Configuration Options
23 * (easy to change)
24 */
25 #define CONFIG_U8500
26
27 #define CONFIG_SYS_MEMTEST_START 0x00000000
28 #define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF
29
30 /*-----------------------------------------------------------------------
31 * Size of environment and malloc() pool
32 */
33 /*
34 * If you use U-Boot as crash kernel, make sure that it does not overwrite
35 * information saved by kexec during panic. Kexec expects the start
36 * address of the executable 32K above "crashkernel" address.
37 */
38 /*
39 * Size of malloc() pool
40 */
41 #define CONFIG_ENV_SIZE (8*1024)
42 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
43
44 #define CONFIG_ENV_IS_IN_MMC
45 #define CONFIG_CMD_ENV
46 #define CONFIG_ENV_OFFSET 0x0118000
47 #define CONFIG_SYS_MMC_ENV_DEV 0 /* SLOT2: eMMC */
48
49 /*
50 * PL011 Configuration
51 */
52 #define CONFIG_PL011_SERIAL
53 #define CONFIG_PL011_SERIAL_RLCR
54 #define CONFIG_PL011_SERIAL_FLUSH_ON_INIT
55
56 /*
57 * U8500 UART registers base for 3 serial devices
58 */
59 #define CFG_UART0_BASE 0x80120000
60 #define CFG_UART1_BASE 0x80121000
61 #define CFG_UART2_BASE 0x80007000
62 #define CFG_SERIAL0 CFG_UART0_BASE
63 #define CFG_SERIAL1 CFG_UART1_BASE
64 #define CFG_SERIAL2 CFG_UART2_BASE
65 #define CONFIG_PL011_CLOCK 38400000
66 #define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \
67 (void *)CFG_SERIAL2 }
68 #define CONFIG_CONS_INDEX 2
69 #define CONFIG_BAUDRATE 115200
70
71 /*
72 * Devices and file systems
73 */
74 #define CONFIG_MMC
75 #define CONFIG_GENERIC_MMC
76 #define CONFIG_DOS_PARTITION
77
78 /*
79 * Commands
80 */
81 #define CONFIG_CMD_MMC
82 #define CONFIG_CMD_FAT
83 #define CONFIG_CMD_EXT2
84
85 #ifndef CONFIG_BOOTDELAY
86 #define CONFIG_BOOTDELAY 1
87 #endif
88 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
89
90 #undef CONFIG_BOOTARGS
91 #define CONFIG_BOOTCOMMAND \
92 "mmc dev 1; " \
93 "if run loadbootscript; " \
94 "then run bootscript; " \
95 "else " \
96 "if run mmcload; " \
97 "then run mmcboot; " \
98 "else " \
99 "mmc dev 0; " \
100 "if run emmcloadbootscript; " \
101 "then run bootscript; " \
102 "else " \
103 "if run emmcload; " \
104 "then run emmcboot; " \
105 "else " \
106 "echo No media to boot from; " \
107 "fi; " \
108 "fi; " \
109 "fi; " \
110 "fi; "
111
112 #define CONFIG_EXTRA_ENV_SETTINGS \
113 "verify=n\0" \
114 "loadaddr=0x00100000\0" \
115 "console=ttyAMA2,115200n8\0" \
116 "loadbootscript=fatload mmc 1:1 ${loadaddr} boot.scr\0" \
117 "emmcloadbootscript=fatload mmc 0:2 ${loadaddr} boot.scr\0" \
118 "bootscript=echo Running bootscript " \
119 "from mmc ...; source ${loadaddr}\0" \
120 "memargs256=mem=96M@0 mem_modem=32M@96M mem=32M@128M " \
121 "hwmem=22M@160M pmem_hwb=42M@182M mem_mali=32@224M\0" \
122 "memargs512=mem=96M@0 mem_modem=32M@96M hwmem=32M@128M " \
123 "mem=64M@160M mem_mali=32M@224M " \
124 "pmem_hwb=128M@256M mem=128M@384M\0" \
125 "memargs1024=mem=128M@0 mali.mali_mem=32M@128M " \
126 "hwmem=168M@M160M mem=48M@328M " \
127 "mem_issw=1M@383M mem=640M@384M\0" \
128 "memargs=setenv bootargs ${bootargs} ${memargs1024}\0" \
129 "emmcload=fatload mmc 0:2 ${loadaddr} uImage\0" \
130 "mmcload=fatload mmc 1:1 ${loadaddr} uImage\0" \
131 "commonargs=setenv bootargs console=${console} " \
132 "vmalloc=300M\0" \
133 "emmcargs=setenv bootargs ${bootargs} " \
134 "root=/dev/mmcblk0p3 " \
135 "rootwait\0" \
136 "addcons=setenv bootargs ${bootargs} " \
137 "console=${console}\0" \
138 "emmcboot=echo Booting from eMMC ...; " \
139 "run commonargs emmcargs memargs; " \
140 "bootm ${loadaddr}\0" \
141 "mmcargs=setenv bootargs ${bootargs} " \
142 "root=/dev/mmcblk1p2 " \
143 "rootwait earlyprintk\0" \
144 "mmcboot=echo Booting from external MMC ...; " \
145 "run commonargs mmcargs memargs; " \
146 "bootm ${loadaddr}\0" \
147 "fdt_high=0x2BC00000\0" \
148 "stdout=serial,usbtty\0" \
149 "stdin=serial,usbtty\0" \
150 "stderr=serial,usbtty\0"
151
152 /*-----------------------------------------------------------------------
153 * Miscellaneous configurable options
154 */
155
156 #define CONFIG_SYS_LONGHELP /* undef to save memory */
157 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
158
159 /* Print Buffer Size */
160 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
161 + sizeof(CONFIG_SYS_PROMPT) + 16)
162 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
163 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
164
165 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
166 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1
167
168 #define CONFIG_SYS_HUSH_PARSER 1
169 #define CONFIG_CMDLINE_EDITING
170
171 #define CONFIG_SETUP_MEMORY_TAGS 2
172 #define CONFIG_INITRD_TAG 1
173 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
174
175 /*
176 * Physical Memory Map
177 */
178 #define CONFIG_NR_DRAM_BANKS 1
179 #define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */
180
181 /*
182 * additions for new relocation code
183 */
184 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
185 #define CONFIG_SYS_MAX_RAM_SIZE 0x40000000
186 #define CONFIG_SYS_INIT_RAM_SIZE 0x100000
187 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
188 CONFIG_SYS_INIT_RAM_SIZE - \
189 GENERATED_GBL_DATA_SIZE)
190 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
191
192 /* landing address before relocation */
193 #ifndef CONFIG_SYS_TEXT_BASE
194 #define CONFIG_SYS_TEXT_BASE 0x0
195 #endif
196
197 /*
198 * MMC related configs
199 */
200 #define CONFIG_ARM_PL180_MMCI
201 #define MMC_BLOCK_SIZE 512
202 #define CFG_EMMC_BASE 0x80114000
203 #define CFG_MMC_BASE 0x80126000
204
205 /*
206 * FLASH and environment organization
207 */
208 #define CONFIG_SYS_NO_FLASH
209
210 /*
211 * base register values for U8500
212 */
213 #define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock */
214
215
216 /*
217 * U8500 GPIO register base for 9 banks
218 */
219 #define CONFIG_DB8500_GPIO
220 #define CFG_GPIO_0_BASE 0x8012E000
221 #define CFG_GPIO_1_BASE 0x8012E080
222 #define CFG_GPIO_2_BASE 0x8000E000
223 #define CFG_GPIO_3_BASE 0x8000E080
224 #define CFG_GPIO_4_BASE 0x8000E100
225 #define CFG_GPIO_5_BASE 0x8000E180
226 #define CFG_GPIO_6_BASE 0x8011E000
227 #define CFG_GPIO_7_BASE 0x8011E080
228 #define CFG_GPIO_8_BASE 0xA03FE000
229
230 #define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */
231
232 #endif /* __CONFIG_H */