include/configs/socfpga_common.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   4  */
   5 #ifndef __CONFIG_SOCFPGA_COMMON_H__
   6 #define __CONFIG_SOCFPGA_COMMON_H__
   7
   8 /*
   9  * High level configuration
  10  */
  11 #define CONFIG_CLOCKS
  12
  13 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  14
  15 /*
  16  * Memory configurations
  17  */
  18 #define PHYS_SDRAM_1                    0x0
  19 #define CONFIG_SYS_MALLOC_LEN           (64 * 1024 * 1024)
  20 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  21 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFFF0000
  22 #define CONFIG_SYS_INIT_RAM_SIZE        SOCFPGA_PHYS_OCRAM_SIZE
  23 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  24 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  25 /* SPL memory allocation configuration, this is for FAT implementation */
  26 #ifndef CONFIG_SYS_SPL_MALLOC_SIZE
  27 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x10000
  28 #endif
  29 #define CONFIG_SYS_INIT_RAM_SIZE        (SOCFPGA_PHYS_OCRAM_SIZE - \
  30                                          CONFIG_SYS_SPL_MALLOC_SIZE)
  31 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_INIT_RAM_ADDR + \
  32                                          CONFIG_SYS_INIT_RAM_SIZE)
  33 #endif
  34
  35 /*
  36  * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
  37  * SRAM as bootcounter storage. Make sure to not put the stack directly
  38  * at this address to not overwrite the bootcounter by checking, if the
  39  * bootcounter address is located in the internal SRAM.
  40  */
  41 #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) &&  \
  42      (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR +   \
  43                                    CONFIG_SYS_INIT_RAM_SIZE)))
  44 #define CONFIG_SPL_STACK                CONFIG_SYS_BOOTCOUNT_ADDR
  45 #else
  46 #define CONFIG_SPL_STACK                        \
  47         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
  48 #endif
  49
  50 /*
  51  * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
  52  * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
  53  * in U-Boot pre-reloc is higher than in SPL.
  54  */
  55 #if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
  56 #define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SPL_STACK_R_ADDR
  57 #else
  58 #define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SPL_STACK
  59 #endif
  60
  61 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  62
  63 /*
  64  * U-Boot general configurations
  65  */
  66 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
  67                                                 /* Print buffer size */
  68 #define CONFIG_SYS_MAXARGS      32              /* Max number of command args */
  69 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  70                                                 /* Boot argument buffer size */
  71
  72 /*
  73  * Cache
  74  */
  75 #define CONFIG_SYS_L2_PL310
  76 #define CONFIG_SYS_PL310_BASE           SOCFPGA_MPUL2_ADDRESS
  77
  78 /*
  79  * Ethernet on SoC (EMAC)
  80  */
  81 #ifdef CONFIG_CMD_NET
  82 #define CONFIG_DW_ALTDESCRIPTOR
  83 #endif
  84
  85 /*
  86  * FPGA Driver
  87  */
  88 #ifdef CONFIG_CMD_FPGA
  89 #define CONFIG_FPGA_COUNT               1
  90 #endif
  91
  92 /*
  93  * L4 OSC1 Timer 0
  94  */
  95 #ifndef CONFIG_TIMER
  96 #define CONFIG_SYS_TIMERBASE            SOCFPGA_OSC1TIMER0_ADDRESS
  97 #define CONFIG_SYS_TIMER_COUNTS_DOWN
  98 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMERBASE + 0x4)
  99 #ifndef CONFIG_SYS_TIMER_RATE
 100 #define CONFIG_SYS_TIMER_RATE           25000000
 101 #endif
 102 #endif
 103
 104 /*
 105  * L4 Watchdog
 106  */
 107 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 108 #define CONFIG_DW_WDT_CLOCK_KHZ         25000
 109
 110 /*
 111  * MMC Driver
 112  */
 113 #ifdef CONFIG_CMD_MMC
 114 /* FIXME */
 115 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 116 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256     /* FIXME -- SPL only? */
 117 #endif
 118
 119 /*
 120  * NAND Support
 121  */
 122 #ifdef CONFIG_NAND_DENALI
 123 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 124 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 125 #define CONFIG_SYS_NAND_ONFI_DETECTION
 126 #define CONFIG_SYS_NAND_REGS_BASE       SOCFPGA_NANDREGS_ADDRESS
 127 #define CONFIG_SYS_NAND_DATA_BASE       SOCFPGA_NANDDATA_ADDRESS
 128 #endif
 129
 130 /*
 131  * QSPI support
 132  */
 133 /* QSPI reference clock */
 134 #ifndef __ASSEMBLY__
 135 unsigned int cm_get_qspi_controller_clk_hz(void);
 136 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
 137 #endif
 138
 139 /*
 140  * USB
 141  */
 142
 143 /*
 144  * USB Gadget (DFU, UMS)
 145  */
 146 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 147 #define CONFIG_SYS_DFU_DATA_BUF_SIZE    (16 * 1024 * 1024)
 148 #define DFU_DEFAULT_POLL_TIMEOUT        300
 149
 150 /* USB IDs */
 151 #define CONFIG_G_DNL_UMS_VENDOR_NUM     0x0525
 152 #define CONFIG_G_DNL_UMS_PRODUCT_NUM    0xA4A5
 153 #endif
 154
 155 /*
 156  * U-Boot environment
 157  */
 158
 159 /* Environment for SDMMC boot */
 160 #if defined(CONFIG_ENV_IS_IN_MMC)
 161 #define CONFIG_SYS_MMC_ENV_DEV          0 /* device 0 */
 162 #endif
 163
 164 /* Environment for QSPI boot */
 165
 166 /*
 167  * SPL
 168  *
 169  * SRAM Memory layout for gen 5:
 170  *
 171  * 0xFFFF_0000 ...... Start of SRAM
 172  * 0xFFFF_xxxx ...... Top of stack (grows down)
 173  * 0xFFFF_yyyy ...... Global Data
 174  * 0xFFFF_zzzz ...... Malloc area
 175  * 0xFFFF_FFFF ...... End of SRAM
 176  *
 177  * SRAM Memory layout for Arria 10:
 178  * 0xFFE0_0000 ...... Start of SRAM (bottom)
 179  * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
 180  * 0xFFEy_yyyy ...... Global Data
 181  * 0xFFEz_zzzz ...... Malloc area (grows up to top)
 182  * 0xFFE3_FFFF ...... End of SRAM (top)
 183  */
 184 #ifndef CONFIG_SPL_TEXT_BASE
 185 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 186 #endif
 187
 188 /* SPL SDMMC boot support */
 189 #ifdef CONFIG_SPL_MMC_SUPPORT
 190 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
 191 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
 192 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 193 #endif
 194 #else
 195 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
 196 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION      1
 197 #endif
 198 #endif
 199
 200 /* SPL QSPI boot support */
 201
 202 /* SPL NAND boot support */
 203 #ifdef CONFIG_SPL_NAND_SUPPORT
 204 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 205 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 206 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 207 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x100000
 208 #endif
 209 #endif
 210
 211 /* Extra Environment */
 212 #ifndef CONFIG_SPL_BUILD
 213
 214 #ifdef CONFIG_CMD_DHCP
 215 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
 216 #else
 217 #define BOOT_TARGET_DEVICES_DHCP(func)
 218 #endif
 219
 220 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
 221 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
 222 #else
 223 #define BOOT_TARGET_DEVICES_PXE(func)
 224 #endif
 225
 226 #ifdef CONFIG_CMD_MMC
 227 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
 228 #else
 229 #define BOOT_TARGET_DEVICES_MMC(func)
 230 #endif
 231
 232 #define BOOT_TARGET_DEVICES(func) \
 233         BOOT_TARGET_DEVICES_MMC(func) \
 234         BOOT_TARGET_DEVICES_PXE(func) \
 235         BOOT_TARGET_DEVICES_DHCP(func)
 236
 237 #include <config_distro_bootcmd.h>
 238
 239 #ifndef CONFIG_EXTRA_ENV_SETTINGS
 240 #define CONFIG_EXTRA_ENV_SETTINGS \
 241         "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 242         "bootm_size=0xa000000\0" \
 243         "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
 244         "fdt_addr_r=0x02000000\0" \
 245         "scriptaddr=0x02100000\0" \
 246         "pxefile_addr_r=0x02200000\0" \
 247         "ramdisk_addr_r=0x02300000\0" \
 248         "socfpga_legacy_reset_compat=1\0" \
 249         BOOTENV
 250
 251 #endif
 252 #endif
 253
 254 #endif  /* __CONFIG_SOCFPGA_COMMON_H__ */