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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/socfpga_common.h
2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef __CONFIG_SOCFPGA_COMMON_H__
7 #define __CONFIG_SOCFPGA_COMMON_H__
9 /* Virtual target or real hardware */
10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
12 #define CONFIG_SYS_THUMB_BUILD
15 * High level configuration
17 #define CONFIG_DISPLAY_BOARDINFO_LATE
18 #define CONFIG_ARCH_MISC_INIT
19 #define CONFIG_SYS_NO_FLASH
22 #define CONFIG_CRC32_VERIFY
24 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
26 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
28 /* add target to build it automatically upon "make" */
29 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp"
32 * Memory configurations
34 #define CONFIG_NR_DRAM_BANKS 1
35 #define PHYS_SDRAM_1 0x0
36 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
37 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
38 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
40 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
41 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
42 #define CONFIG_SYS_INIT_SP_OFFSET \
43 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
44 #define CONFIG_SYS_INIT_SP_ADDR \
45 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
47 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
48 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
49 #define CONFIG_SYS_TEXT_BASE 0x08000040
51 #define CONFIG_SYS_TEXT_BASE 0x01000040
55 * U-Boot general configurations
57 #define CONFIG_SYS_LONGHELP
58 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
59 #define CONFIG_SYS_PBSIZE \
60 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
61 /* Print buffer size */
62 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
63 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
64 /* Boot argument buffer size */
65 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
66 #define CONFIG_CMDLINE_EDITING /* Command history etc */
68 #ifndef CONFIG_SYS_HOSTNAME
69 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD
75 #define CONFIG_SYS_L2_PL310
76 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
81 #define CONFIG_ALTERA_SDRAM
84 * EPCS/EPCQx1 Serial Flash Controller
86 #ifdef CONFIG_ALTERA_SPI
87 #define CONFIG_SF_DEFAULT_SPEED 30000000
89 * The base address is configurable in QSys, each board must specify the
90 * base address based on it's particular FPGA configuration. Please note
91 * that the address here is incremented by 0x400 from the Base address
92 * selected in QSys, since the SPI registers are at offset +0x400.
93 * #define CONFIG_SYS_SPI_BASE 0xff240400
98 * Ethernet on SoC (EMAC)
100 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
101 #define CONFIG_DW_ALTDESCRIPTOR
103 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
104 #define CONFIG_PHY_GIGE
110 #ifdef CONFIG_CMD_FPGA
112 #define CONFIG_FPGA_ALTERA
113 #define CONFIG_FPGA_SOCFPGA
114 #define CONFIG_FPGA_COUNT 1
120 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
121 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
122 #define CONFIG_SYS_TIMER_COUNTS_DOWN
123 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
124 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
125 #define CONFIG_SYS_TIMER_RATE 2400000
127 #define CONFIG_SYS_TIMER_RATE 25000000
133 #ifdef CONFIG_HW_WATCHDOG
134 #define CONFIG_DESIGNWARE_WATCHDOG
135 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
136 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
137 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000
143 #ifdef CONFIG_CMD_MMC
144 #define CONFIG_BOUNCE_BUFFER
145 #define CONFIG_GENERIC_MMC
147 /* using smaller max blk cnt to avoid flooding the limited stack we have */
148 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
154 #ifdef CONFIG_NAND_DENALI
155 #define CONFIG_SYS_MAX_NAND_DEVICE 1
156 #define CONFIG_SYS_NAND_MAX_CHIPS 1
157 #define CONFIG_SYS_NAND_ONFI_DETECTION
158 #define CONFIG_NAND_DENALI_ECC_SIZE 512
159 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
160 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
161 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
167 #define CONFIG_SYS_I2C
168 #define CONFIG_SYS_I2C_BUS_MAX 4
169 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
170 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
171 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
172 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS
173 /* Using standard mode which the speed up to 100Kb/s */
174 #define CONFIG_SYS_I2C_SPEED 100000
175 #define CONFIG_SYS_I2C_SPEED1 100000
176 #define CONFIG_SYS_I2C_SPEED2 100000
177 #define CONFIG_SYS_I2C_SPEED3 100000
178 /* Address of device when used as slave */
179 #define CONFIG_SYS_I2C_SLAVE 0x02
180 #define CONFIG_SYS_I2C_SLAVE1 0x02
181 #define CONFIG_SYS_I2C_SLAVE2 0x02
182 #define CONFIG_SYS_I2C_SLAVE3 0x02
184 /* Clock supplied to I2C controller in unit of MHz */
185 unsigned int cm_get_l4_sp_clk_hz(void);
186 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
192 /* Enable multiple SPI NOR flash manufacturers */
193 #ifndef CONFIG_SPL_BUILD
194 #define CONFIG_SPI_FLASH_MTD
195 #define CONFIG_CMD_MTDPARTS
196 #define CONFIG_MTD_DEVICE
197 #define CONFIG_MTD_PARTITIONS
198 #define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
200 /* QSPI reference clock */
202 unsigned int cm_get_qspi_controller_clk_hz(void);
203 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
205 #define CONFIG_CQSPI_DECODER 0
206 #define CONFIG_BOUNCE_BUFFER
209 * Designware SPI support
215 #define CONFIG_SYS_NS16550_SERIAL
216 #define CONFIG_SYS_NS16550_REG_SIZE -4
217 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
218 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
219 #define CONFIG_SYS_NS16550_CLK 1000000
221 #define CONFIG_SYS_NS16550_CLK 100000000
223 #define CONFIG_CONS_INDEX 1
224 #define CONFIG_BAUDRATE 115200
229 #ifdef CONFIG_CMD_USB
230 #define CONFIG_USB_DWC2
234 * USB Gadget (DFU, UMS)
236 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
237 #define CONFIG_USB_FUNCTION_MASS_STORAGE
239 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024)
240 #define DFU_DEFAULT_POLL_TIMEOUT 300
243 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
244 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
250 #if !defined(CONFIG_ENV_SIZE)
251 #define CONFIG_ENV_SIZE 4096
254 /* Environment for SDMMC boot */
255 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
256 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
257 #define CONFIG_ENV_OFFSET 512 /* just after the MBR */
260 /* Environment for QSPI boot */
261 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
262 #define CONFIG_ENV_OFFSET 0x00100000
263 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
267 * mtd partitioning for serial NOR flash
269 * device nor0 <ff705000.spi.0>, # parts = 6
270 * #: name size offset mask_flags
271 * 0: u-boot 0x00100000 0x00000000 0
272 * 1: env1 0x00040000 0x00100000 0
273 * 2: env2 0x00040000 0x00140000 0
274 * 3: UBI 0x03e80000 0x00180000 0
275 * 4: boot 0x00e80000 0x00180000 0
276 * 5: rootfs 0x01000000 0x01000000 0
279 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
280 #define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\
289 /* UBI and UBIFS support */
290 #if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND)
291 #define CONFIG_CMD_UBIFS
292 #define CONFIG_RBTREE
299 * SRAM Memory layout:
301 * 0xFFFF_0000 ...... Start of SRAM
302 * 0xFFFF_xxxx ...... Top of stack (grows down)
303 * 0xFFFF_yyyy ...... Malloc area
304 * 0xFFFF_zzzz ...... Global Data
305 * 0xFFFF_FF00 ...... End of SRAM
307 #define CONFIG_SPL_FRAMEWORK
308 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
309 #define CONFIG_SPL_MAX_SIZE (64 * 1024)
311 /* SPL SDMMC boot support */
312 #ifdef CONFIG_SPL_MMC_SUPPORT
313 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
314 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2
315 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
317 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
321 /* SPL QSPI boot support */
322 #ifdef CONFIG_SPL_SPI_SUPPORT
323 #define CONFIG_SPL_SPI_LOAD
324 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
327 /* SPL NAND boot support */
328 #ifdef CONFIG_SPL_NAND_SUPPORT
329 #define CONFIG_SYS_NAND_USE_FLASH_BBT
330 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
331 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
337 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
339 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */