include/configs/socfpga_common.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   4  */
   5 #ifndef __CONFIG_SOCFPGA_COMMON_H__
   6 #define __CONFIG_SOCFPGA_COMMON_H__
   7
   8 #include <linux/stringify.h>
   9
  10 /*
  11  * High level configuration
  12  */
  13 #define CONFIG_CLOCKS
  14
  15 /*
  16  * Memory configurations
  17  */
  18 #define PHYS_SDRAM_1                    0x0
  19 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  20 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFFF0000
  21 #define CONFIG_SYS_INIT_RAM_SIZE        SOCFPGA_PHYS_OCRAM_SIZE
  22 #define CONFIG_SPL_PAD_TO               0x10000
  23 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  24 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  25 #define CONFIG_SPL_PAD_TO               0x40000
  26 /* SPL memory allocation configuration, this is for FAT implementation */
  27 #ifndef CONFIG_SYS_SPL_MALLOC_SIZE
  28 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x10000
  29 #endif
  30 #define CONFIG_SYS_INIT_RAM_SIZE        (SOCFPGA_PHYS_OCRAM_SIZE - \
  31                                          CONFIG_SYS_SPL_MALLOC_SIZE)
  32 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_INIT_RAM_ADDR + \
  33                                          CONFIG_SYS_INIT_RAM_SIZE)
  34 #endif
  35
  36 /*
  37  * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
  38  * SRAM as bootcounter storage. Make sure to not put the stack directly
  39  * at this address to not overwrite the bootcounter by checking, if the
  40  * bootcounter address is located in the internal SRAM.
  41  */
  42 #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) &&  \
  43      (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR +   \
  44                                    CONFIG_SYS_INIT_RAM_SIZE)))
  45 #define CONFIG_SPL_STACK                CONFIG_SYS_BOOTCOUNT_ADDR
  46 #else
  47 #define CONFIG_SPL_STACK                        \
  48         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
  49 #endif
  50
  51 /*
  52  * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
  53  * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
  54  * in U-Boot pre-reloc is higher than in SPL.
  55  */
  56 #if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
  57 #define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SPL_STACK_R_ADDR
  58 #else
  59 #define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SPL_STACK
  60 #endif
  61
  62 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  63
  64 /*
  65  * U-Boot general configurations
  66  */
  67 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
  68                                                 /* Print buffer size */
  69 #define CONFIG_SYS_MAXARGS      32              /* Max number of command args */
  70 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  71                                                 /* Boot argument buffer size */
  72
  73 /*
  74  * Cache
  75  */
  76 #define CONFIG_SYS_L2_PL310
  77 #define CONFIG_SYS_PL310_BASE           SOCFPGA_MPUL2_ADDRESS
  78
  79 /*
  80  * Ethernet on SoC (EMAC)
  81  */
  82 #ifdef CONFIG_CMD_NET
  83 #define CONFIG_DW_ALTDESCRIPTOR
  84 #endif
  85
  86 /*
  87  * FPGA Driver
  88  */
  89 #ifdef CONFIG_CMD_FPGA
  90 #define CONFIG_FPGA_COUNT               1
  91 #endif
  92
  93 /*
  94  * L4 OSC1 Timer 0
  95  */
  96 #ifndef CONFIG_TIMER
  97 #define CONFIG_SYS_TIMERBASE            SOCFPGA_OSC1TIMER0_ADDRESS
  98 #define CONFIG_SYS_TIMER_COUNTS_DOWN
  99 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMERBASE + 0x4)
 100 #ifndef CONFIG_SYS_TIMER_RATE
 101 #define CONFIG_SYS_TIMER_RATE           25000000
 102 #endif
 103 #endif
 104
 105 /*
 106  * L4 Watchdog
 107  */
 108 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 109 #define CONFIG_DW_WDT_CLOCK_KHZ         25000
 110
 111 /*
 112  * MMC Driver
 113  */
 114 #ifdef CONFIG_CMD_MMC
 115 /* FIXME */
 116 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 117 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256     /* FIXME -- SPL only? */
 118 #endif
 119
 120 /*
 121  * NAND Support
 122  */
 123 #ifdef CONFIG_NAND_DENALI
 124 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 125 #define CONFIG_SYS_NAND_REGS_BASE       SOCFPGA_NANDREGS_ADDRESS
 126 #define CONFIG_SYS_NAND_DATA_BASE       SOCFPGA_NANDDATA_ADDRESS
 127 #endif
 128
 129 /*
 130  * QSPI support
 131  */
 132 /* QSPI reference clock */
 133 #ifndef __ASSEMBLY__
 134 unsigned int cm_get_qspi_controller_clk_hz(void);
 135 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
 136 #endif
 137
 138 /*
 139  * USB
 140  */
 141
 142 /*
 143  * USB Gadget (DFU, UMS)
 144  */
 145 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 146 #define DFU_DEFAULT_POLL_TIMEOUT        300
 147
 148 /* USB IDs */
 149 #define CONFIG_G_DNL_UMS_VENDOR_NUM     0x0525
 150 #define CONFIG_G_DNL_UMS_PRODUCT_NUM    0xA4A5
 151 #endif
 152
 153 /*
 154  * U-Boot environment
 155  */
 156
 157 /* Environment for SDMMC boot */
 158
 159 /* Environment for QSPI boot */
 160
 161 /*
 162  * SPL
 163  *
 164  * SRAM Memory layout for gen 5:
 165  *
 166  * 0xFFFF_0000 ...... Start of SRAM
 167  * 0xFFFF_xxxx ...... Top of stack (grows down)
 168  * 0xFFFF_yyyy ...... Global Data
 169  * 0xFFFF_zzzz ...... Malloc area
 170  * 0xFFFF_FFFF ...... End of SRAM
 171  *
 172  * SRAM Memory layout for Arria 10:
 173  * 0xFFE0_0000 ...... Start of SRAM (bottom)
 174  * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
 175  * 0xFFEy_yyyy ...... Global Data
 176  * 0xFFEz_zzzz ...... Malloc area (grows up to top)
 177  * 0xFFE3_FFFF ...... End of SRAM (top)
 178  */
 179 #ifndef CONFIG_SPL_TEXT_BASE
 180 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 181 #endif
 182
 183 /* SPL SDMMC boot support */
 184 #ifdef CONFIG_SPL_MMC
 185 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
 186 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
 187 #endif
 188 #endif
 189
 190 /* SPL QSPI boot support */
 191
 192 /* SPL NAND boot support */
 193
 194 /* Extra Environment */
 195 #ifndef CONFIG_SPL_BUILD
 196
 197 #ifdef CONFIG_CMD_DHCP
 198 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
 199 #else
 200 #define BOOT_TARGET_DEVICES_DHCP(func)
 201 #endif
 202
 203 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
 204 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
 205 #else
 206 #define BOOT_TARGET_DEVICES_PXE(func)
 207 #endif
 208
 209 #ifdef CONFIG_CMD_MMC
 210 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
 211 #else
 212 #define BOOT_TARGET_DEVICES_MMC(func)
 213 #endif
 214
 215 #define BOOT_TARGET_DEVICES(func) \
 216         BOOT_TARGET_DEVICES_MMC(func) \
 217         BOOT_TARGET_DEVICES_PXE(func) \
 218         BOOT_TARGET_DEVICES_DHCP(func)
 219
 220 #include <config_distro_bootcmd.h>
 221
 222 #ifndef CONFIG_EXTRA_ENV_SETTINGS
 223 #define CONFIG_EXTRA_ENV_SETTINGS \
 224         "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 225         "bootm_size=0xa000000\0" \
 226         "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
 227         "fdt_addr_r=0x02000000\0" \
 228         "scriptaddr=0x02100000\0" \
 229         "pxefile_addr_r=0x02200000\0" \
 230         "ramdisk_addr_r=0x02300000\0" \
 231         "socfpga_legacy_reset_compat=1\0" \
 232         BOOTENV
 233
 234 #endif
 235 #endif
 236
 237 #endif  /* __CONFIG_SOCFPGA_COMMON_H__ */