include/configs/socfpga_common.h

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
   7 #define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
   8
   9 #define CONFIG_SYS_GENERIC_BOARD
  10
  11 /* Virtual target or real hardware */
  12 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
  13
  14 #define CONFIG_SYS_THUMB_BUILD
  15
  16 /*
  17  * High level configuration
  18  */
  19 #define CONFIG_DISPLAY_CPUINFO
  20 #define CONFIG_DISPLAY_BOARDINFO_LATE
  21 #define CONFIG_ARCH_MISC_INIT
  22 #define CONFIG_ARCH_EARLY_INIT_R
  23 #define CONFIG_SYS_NO_FLASH
  24 #define CONFIG_CLOCKS
  25
  26 #define CONFIG_CRC32_VERIFY
  27
  28 #define CONFIG_FIT
  29 #define CONFIG_OF_LIBFDT
  30 #define CONFIG_SYS_BOOTMAPSZ            (64 * 1024 * 1024)
  31
  32 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  33
  34 /*
  35  * Memory configurations
  36  */
  37 #define CONFIG_NR_DRAM_BANKS            1
  38 #define PHYS_SDRAM_1                    0x0
  39 #define CONFIG_SYS_MALLOC_LEN           (64 * 1024 * 1024)
  40 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
  41 #define CONFIG_SYS_MEMTEST_END          PHYS_SDRAM_1_SIZE
  42
  43 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFFF0000
  44 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  45 #define CONFIG_SYS_INIT_SP_OFFSET               \
  46         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  47 #define CONFIG_SYS_INIT_SP_ADDR                 \
  48         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  49
  50 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  51 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  52 #define CONFIG_SYS_TEXT_BASE            0x08000040
  53 #else
  54 #define CONFIG_SYS_TEXT_BASE            0x01000040
  55 #endif
  56
  57 /*
  58  * U-Boot general configurations
  59  */
  60 #define CONFIG_SYS_LONGHELP
  61 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
  62 #define CONFIG_SYS_PBSIZE       \
  63         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  64                                                 /* Print buffer size */
  65 #define CONFIG_SYS_MAXARGS      32              /* Max number of command args */
  66 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  67                                                 /* Boot argument buffer size */
  68 #define CONFIG_VERSION_VARIABLE                 /* U-BOOT version */
  69 #define CONFIG_AUTO_COMPLETE                    /* Command auto complete */
  70 #define CONFIG_CMDLINE_EDITING                  /* Command history etc */
  71 #define CONFIG_SYS_HUSH_PARSER
  72
  73 /*
  74  * Cache
  75  */
  76 #define CONFIG_SYS_ARM_CACHE_WRITEALLOC
  77 #define CONFIG_SYS_CACHELINE_SIZE 32
  78 #define CONFIG_SYS_L2_PL310
  79 #define CONFIG_SYS_PL310_BASE           SOCFPGA_MPUL2_ADDRESS
  80
  81 /*
  82  * SDRAM controller
  83  */
  84 #define CONFIG_ALTERA_SDRAM
  85
  86 /*
  87  * EPCS/EPCQx1 Serial Flash Controller
  88  */
  89 #ifdef CONFIG_ALTERA_SPI
  90 #define CONFIG_CMD_SPI
  91 #define CONFIG_CMD_SF
  92 #define CONFIG_SF_DEFAULT_SPEED         30000000
  93 #define CONFIG_SPI_FLASH_STMICRO
  94 #define CONFIG_SPI_FLASH_BAR
  95 /*
  96  * The base address is configurable in QSys, each board must specify the
  97  * base address based on it's particular FPGA configuration. Please note
  98  * that the address here is incremented by  0x400  from the Base address
  99  * selected in QSys, since the SPI registers are at offset +0x400.
 100  * #define CONFIG_SYS_SPI_BASE          0xff240400
 101  */
 102 #endif
 103
 104 /*
 105  * Ethernet on SoC (EMAC)
 106  */
 107 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 108 #define CONFIG_DW_ALTDESCRIPTOR
 109 #define CONFIG_MII
 110 #define CONFIG_AUTONEG_TIMEOUT          (15 * CONFIG_SYS_HZ)
 111 #define CONFIG_PHYLIB
 112 #define CONFIG_PHY_GIGE
 113 #endif
 114
 115 /*
 116  * FPGA Driver
 117  */
 118 #ifdef CONFIG_CMD_FPGA
 119 #define CONFIG_FPGA
 120 #define CONFIG_FPGA_ALTERA
 121 #define CONFIG_FPGA_SOCFPGA
 122 #define CONFIG_FPGA_COUNT               1
 123 #endif
 124
 125 /*
 126  * L4 OSC1 Timer 0
 127  */
 128 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
 129 #define CONFIG_SYS_TIMERBASE            SOCFPGA_OSC1TIMER0_ADDRESS
 130 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 131 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMERBASE + 0x4)
 132 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 133 #define CONFIG_SYS_TIMER_RATE           2400000
 134 #else
 135 #define CONFIG_SYS_TIMER_RATE           25000000
 136 #endif
 137
 138 /*
 139  * L4 Watchdog
 140  */
 141 #ifdef CONFIG_HW_WATCHDOG
 142 #define CONFIG_DESIGNWARE_WATCHDOG
 143 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 144 #define CONFIG_DW_WDT_CLOCK_KHZ         25000
 145 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS   30000
 146 #endif
 147
 148 /*
 149  * MMC Driver
 150  */
 151 #ifdef CONFIG_CMD_MMC
 152 #define CONFIG_MMC
 153 #define CONFIG_BOUNCE_BUFFER
 154 #define CONFIG_GENERIC_MMC
 155 #define CONFIG_DWMMC
 156 #define CONFIG_SOCFPGA_DWMMC
 157 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
 158 #define CONFIG_SOCFPGA_DWMMC_DRVSEL     3
 159 #define CONFIG_SOCFPGA_DWMMC_SMPSEL     0
 160 /* FIXME */
 161 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 162 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256     /* FIXME -- SPL only? */
 163 #endif
 164
 165 /*
 166  * I2C support
 167  */
 168 #define CONFIG_SYS_I2C
 169 #define CONFIG_SYS_I2C_DW
 170 #define CONFIG_SYS_I2C_BUS_MAX          4
 171 #define CONFIG_SYS_I2C_BASE             SOCFPGA_I2C0_ADDRESS
 172 #define CONFIG_SYS_I2C_BASE1            SOCFPGA_I2C1_ADDRESS
 173 #define CONFIG_SYS_I2C_BASE2            SOCFPGA_I2C2_ADDRESS
 174 #define CONFIG_SYS_I2C_BASE3            SOCFPGA_I2C3_ADDRESS
 175 /* Using standard mode which the speed up to 100Kb/s */
 176 #define CONFIG_SYS_I2C_SPEED            100000
 177 #define CONFIG_SYS_I2C_SPEED1           100000
 178 #define CONFIG_SYS_I2C_SPEED2           100000
 179 #define CONFIG_SYS_I2C_SPEED3           100000
 180 /* Address of device when used as slave */
 181 #define CONFIG_SYS_I2C_SLAVE            0x02
 182 #define CONFIG_SYS_I2C_SLAVE1           0x02
 183 #define CONFIG_SYS_I2C_SLAVE2           0x02
 184 #define CONFIG_SYS_I2C_SLAVE3           0x02
 185 #ifndef __ASSEMBLY__
 186 /* Clock supplied to I2C controller in unit of MHz */
 187 unsigned int cm_get_l4_sp_clk_hz(void);
 188 #define IC_CLK                          (cm_get_l4_sp_clk_hz() / 1000000)
 189 #endif
 190 #define CONFIG_CMD_I2C
 191
 192 /*
 193  * QSPI support
 194  */
 195 #ifdef CONFIG_OF_CONTROL        /* QSPI is controlled via DT */
 196 #define CONFIG_CADENCE_QSPI
 197 /* Enable multiple SPI NOR flash manufacturers */
 198 #define CONFIG_SPI_FLASH_STMICRO        /* Micron/Numonyx flash */
 199 #define CONFIG_SPI_FLASH_SPANSION       /* Spansion flash */
 200 #ifndef CONFIG_SPL_BUILD
 201 #define CONFIG_SPI_FLASH_MTD
 202 #define CONFIG_CMD_MTDPARTS
 203 #define CONFIG_MTD_DEVICE
 204 #define CONFIG_MTD_PARTITIONS
 205 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi"
 206 #endif
 207 /* QSPI reference clock */
 208 #ifndef __ASSEMBLY__
 209 unsigned int cm_get_qspi_controller_clk_hz(void);
 210 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
 211 #endif
 212 #define CONFIG_CQSPI_DECODER            0
 213 #define CONFIG_CMD_SF
 214 #define CONFIG_SPI_FLASH_BAR
 215 #endif
 216
 217 #if CONFIG_IS_ENABLED(OF_CONTROL)       /* DW SPI is controlled via DT */
 218 #define CONFIG_DESIGNWARE_SPI
 219 #define CONFIG_CMD_SPI
 220 #endif
 221
 222 /*
 223  * Serial Driver
 224  */
 225 #define CONFIG_SYS_NS16550
 226 #define CONFIG_SYS_NS16550_SERIAL
 227 #define CONFIG_SYS_NS16550_REG_SIZE     -4
 228 #define CONFIG_SYS_NS16550_COM1         SOCFPGA_UART0_ADDRESS
 229 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 230 #define CONFIG_SYS_NS16550_CLK          1000000
 231 #else
 232 #define CONFIG_SYS_NS16550_CLK          100000000
 233 #endif
 234 #define CONFIG_CONS_INDEX               1
 235 #define CONFIG_BAUDRATE                 115200
 236
 237 /*
 238  * USB
 239  */
 240 #ifdef CONFIG_CMD_USB
 241 #define CONFIG_USB_DWC2
 242 #define CONFIG_USB_STORAGE
 243 /*
 244  * NOTE: User must define either of the following to select which
 245  *       of the two USB controllers available on SoCFPGA to use.
 246  *       The DWC2 driver doesn't support multiple USB controllers.
 247  * #define CONFIG_USB_DWC2_REG_ADDR     SOCFPGA_USB0_ADDRESS
 248  * #define CONFIG_USB_DWC2_REG_ADDR     SOCFPGA_USB1_ADDRESS
 249  */
 250 #endif
 251
 252 /*
 253  * USB Gadget (DFU, UMS)
 254  */
 255 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 256 #define CONFIG_USB_GADGET
 257 #define CONFIG_USB_GADGET_S3C_UDC_OTG
 258 #define CONFIG_USB_GADGET_DUALSPEED
 259 #define CONFIG_USB_GADGET_VBUS_DRAW     2
 260
 261 /* USB Composite download gadget - g_dnl */
 262 #define CONFIG_USB_GADGET_DOWNLOAD
 263 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 264
 265 #define CONFIG_USB_FUNCTION_DFU
 266 #define CONFIG_DFU_MMC
 267 #define CONFIG_SYS_DFU_DATA_BUF_SIZE    (32 * 1024 * 1024)
 268 #define DFU_DEFAULT_POLL_TIMEOUT        300
 269
 270 /* USB IDs */
 271 #define CONFIG_G_DNL_VENDOR_NUM         0x0525  /* NetChip */
 272 #define CONFIG_G_DNL_PRODUCT_NUM        0xA4A5  /* Linux-USB File-backed Storage Gadget */
 273 #define CONFIG_G_DNL_UMS_VENDOR_NUM     CONFIG_G_DNL_VENDOR_NUM
 274 #define CONFIG_G_DNL_UMS_PRODUCT_NUM    CONFIG_G_DNL_PRODUCT_NUM
 275 #ifndef CONFIG_G_DNL_MANUFACTURER
 276 #define CONFIG_G_DNL_MANUFACTURER       "Altera"
 277 #endif
 278 #endif
 279
 280 /*
 281  * U-Boot environment
 282  */
 283 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 284 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 285 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 286 #define CONFIG_ENV_IS_NOWHERE
 287 #define CONFIG_ENV_SIZE                 4096
 288
 289 /*
 290  * SPL
 291  *
 292  * SRAM Memory layout:
 293  *
 294  * 0xFFFF_0000 ...... Start of SRAM
 295  * 0xFFFF_xxxx ...... Top of stack (grows down)
 296  * 0xFFFF_yyyy ...... Malloc area
 297  * 0xFFFF_zzzz ...... Global Data
 298  * 0xFFFF_FF00 ...... End of SRAM
 299  */
 300 #define CONFIG_SPL_FRAMEWORK
 301 #define CONFIG_SPL_RAM_DEVICE
 302 #define CONFIG_SPL_TEXT_BASE            CONFIG_SYS_INIT_RAM_ADDR
 303 #define CONFIG_SPL_MAX_SIZE             (64 * 1024)
 304 #ifdef CONFIG_SPL_BUILD
 305 #define CONFIG_SYS_MALLOC_SIMPLE
 306 #endif
 307
 308 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 309 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 310 #define CONFIG_SPL_WATCHDOG_SUPPORT
 311 #define CONFIG_SPL_SERIAL_SUPPORT
 312 #define CONFIG_SPL_MMC_SUPPORT
 313 #define CONFIG_SPL_SPI_SUPPORT
 314
 315 /* SPL SDMMC boot support */
 316 #ifdef CONFIG_SPL_MMC_SUPPORT
 317 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
 318 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      2
 319 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot-dtb.img"
 320 #define CONFIG_SPL_LIBDISK_SUPPORT
 321 #else
 322 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      3
 323 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */
 324 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      800 /* 400 KB */
 325 #endif
 326 #endif
 327
 328 /* SPL QSPI boot support */
 329 #ifdef CONFIG_SPL_SPI_SUPPORT
 330 #define CONFIG_DM_SEQ_ALIAS             1
 331 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 332 #define CONFIG_SPL_SPI_LOAD
 333 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x40000
 334 #endif
 335
 336 /*
 337  * Stack setup
 338  */
 339 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 340
 341 #endif  /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */