include/configs/spc1920.h

   1 /*
   2  * (C) Copyright 2006
   3  * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de
   4  *
   5  * Configuation settings for the SPC1920 board.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #ifndef __H
  24 #define __CONFIG_H
  25
  26 #define CONFIG_SPC1920                  1       /* SPC1920 board */
  27 #define CONFIG_MPC885                   1       /* MPC885 CPU */
  28
  29 #define CONFIG_8xx_CONS_SMC1            /* Console is on SMC1 */
  30 #undef  CONFIG_8xx_CONS_SMC2
  31 #undef  CONFIG_8xx_CONS_NONE
  32
  33 #define CONFIG_MII
  34 /* #define MII_DEBUG */
  35 /* #define CONFIG_FEC_ENET */
  36 #undef CONFIG_ETHER_ON_FEC1
  37 #define CONFIG_ETHER_ON_FEC2
  38 #define FEC_ENET
  39 /* #define CONFIG_FEC2_PHY_NORXERR */
  40 /* #define CFG_DISCOVER_PHY */
  41 /* #define CONFIG_PHY_ADDR              0x1 */
  42 #define CONFIG_FEC2_PHY         1
  43
  44 #define CONFIG_BAUDRATE         19200
  45
  46 /* use PLD CLK4 instead of brg */
  47 #define CFG_SPC1920_SMC1_CLK4
  48
  49 #define CONFIG_8xx_OSCLK                10000000 /* 10 MHz oscillator on EXTCLK  */
  50 #define CONFIG_8xx_CPUCLK_DEFAULT       50000000
  51 #define CFG_8xx_CPUCLK_MIN              40000000
  52 #define CFG_8xx_CPUCLK_MAX              133000000
  53
  54 #define CFG_RESET_ADDRESS               0xf8000000
  55
  56 #define CONFIG_BOARD_EARLY_INIT_F
  57
  58
  59 #if 1
  60 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  61 #else
  62 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  63 #endif
  64
  65 #define CONFIG_ENV_OVERWRITE
  66
  67 #define CONFIG_NFSBOOTCOMMAND                                                   \
  68     "dhcp;"                                                                     \
  69     "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath "                       \
  70     "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"              \
  71     "bootm"
  72
  73 #define CONFIG_BOOTCOMMAND                                                      \
  74     "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
  75     "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"              \
  76     "bootm fe080000"
  77
  78 #undef CONFIG_BOOTARGS
  79
  80 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  81 #define CONFIG_BZIP2     /* include support for bzip2 compressed images */
  82
  83 #ifndef CONFIG_COMMANDS
  84 #define CONFIG_COMMANDS (CONFIG_CMD_DFL   \
  85                          | CFG_CMD_ASKENV \
  86                          | CFG_CMD_ECHO   \
  87                          | CFG_CMD_IMMAP  \
  88                          | CFG_CMD_JFFS2 \
  89                          | CFG_CMD_PING \
  90                          | CFG_CMD_DHCP \
  91                          | CFG_CMD_IMMAP \
  92                          | CFG_CMD_I2C \
  93                          | CFG_CMD_MII)
  94                         /* & ~( CFG_CMD_NET)) */
  95
  96
  97 #endif /* !CONFIG_COMMANDS */
  98
  99 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 100 #include <cmd_confdefs.h>
 101
 102 /*
 103  * Miscellaneous configurable options
 104  */
 105 #define CFG_LONGHELP                            /* undef to save memory         */
 106 #define CFG_PROMPT              "=>"            /* Monitor Command Prompt       */
 107 #define CFG_HUSH_PARSER
 108 #define CFG_PROMPT_HUSH_PS2     "> "
 109
 110 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 111 #define CFG_CBSIZE              1024            /* Console I/O Buffer Size      */
 112 #else
 113 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 114 #endif
 115
 116 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size  */
 117 #define CFG_MAXARGS             16              /* max number of command args   */
 118 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 119
 120 #define CFG_LOAD_ADDR           0x00100000
 121
 122 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 123
 124 #define CFG_BAUDRATE_TABLE      { 2400, 4800, 9600, 19200 }
 125
 126 /*
 127  * Low Level Configuration Settings
 128  * (address mappings, register initial values, etc.)
 129  * You should know what you are doing if you make changes here.
 130  */
 131
 132 /*-----------------------------------------------------------------------
 133  * Internal Memory Mapped Register
 134  */
 135 #define CFG_IMMR                0xF0000000
 136
 137 /*-----------------------------------------------------------------------
 138  * Definitions for initial stack pointer and data area (in DPRAM)
 139  */
 140 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 141 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 142 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 143 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 144 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 145
 146 /*-----------------------------------------------------------------------
 147  * Start addresses for the final memory configuration
 148  * (Set up by the startup code)
 149  * Please note that CFG_SDRAM_BASE _must_ start at 0
 150  */
 151 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 152 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 153
 154 /*
 155  * For booting Linux, the board info and command line data
 156  * have to be in the first 8 MB of memory, since this is
 157  * the maximum mapped by the Linux kernel during initialization.
 158  */
 159 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 160
 161 #define CFG_MONITOR_BASE        TEXT_BASE
 162 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 KB for monitor   */
 163
 164 #ifdef CONFIG_BZIP2
 165 #define CFG_MALLOC_LEN          (2500 << 10)    /* Reserve ~2.5 MB for malloc() */
 166 #else
 167 #define CFG_MALLOC_LEN          (384 << 10)     /* Reserve 384 kB for malloc()  */
 168 #endif /* CONFIG_BZIP2 */
 169
 170 #define CFG_ALLOC_DPRAM         1       /* use allocation routines      */
 171
 172 /*
 173  * Flash
 174  */
 175 /*-----------------------------------------------------------------------
 176  * Flash organisation
 177  */
 178 #define CFG_FLASH_BASE          0xFE000000
 179 #define CFG_FLASH_CFI                           /* The flash is CFI compatible  */
 180 #define CFG_FLASH_CFI_DRIVER                    /* Use common CFI driver        */
 181 #define CFG_MAX_FLASH_BANKS     1               /* Max number of flash banks    */
 182 #define CFG_MAX_FLASH_SECT      128             /* Max num of sects on one chip */
 183
 184 /* Environment is in flash */
 185 #define CFG_ENV_IS_IN_FLASH
 186 #define CFG_ENV_SECT_SIZE       0x40000         /* We use one complete sector   */
 187 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 188
 189 #define CONFIG_ENV_OVERWRITE
 190
 191 /*-----------------------------------------------------------------------
 192  * Cache Configuration
 193  */
 194 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 195 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 196
 197 /*-----------------------------------------------------------------------
 198  * I2C configuration
 199  */
 200 #if (CONFIG_COMMANDS & CFG_CMD_I2C)
 201 /* enable I2C and select the hardware/software driver */
 202 #undef CONFIG_HARD_I2C                 /* I2C with hardware support    */
 203 #define CONFIG_SOFT_I2C                1       /* I2C bit-banged               */
 204
 205 #define CFG_I2C_SPEED          93000   /* 93 kHz is supposed to work   */
 206 #define CFG_I2C_SLAVE          0xFE
 207
 208 #ifdef CONFIG_SOFT_I2C
 209 /*
 210  * Software (bit-bang) I2C driver configuration
 211  */
 212 #define PB_SCL         0x00000020      /* PB 26 */
 213 #define PB_SDA         0x00000010      /* PB 27 */
 214
 215 #define I2C_INIT       (immr->im_cpm.cp_pbdir |=  PB_SCL)
 216 #define I2C_ACTIVE     (immr->im_cpm.cp_pbdir |=  PB_SDA)
 217 #define I2C_TRISTATE   (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 218 #define I2C_READ       ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 219 #define I2C_SDA(bit)   if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 220                        else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 221 #define I2C_SCL(bit)   if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 222                        else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 223 #define I2C_DELAY      udelay(2)       /* 1/4 I2C clock duration */
 224 #endif /* CONFIG_SOFT_I2C */
 225 #endif
 226
 227 /*-----------------------------------------------------------------------
 228  * SYPCR - System Protection Control                            11-9
 229  * SYPCR can only be written once after reset!
 230  *-----------------------------------------------------------------------
 231  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 232  */
 233 #if defined(CONFIG_WATCHDOG)
 234 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 235                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 236 #else
 237 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 238 #endif
 239
 240 /*-----------------------------------------------------------------------
 241  * SIUMCR - SIU Module Configuration                            11-6
 242  *-----------------------------------------------------------------------
 243  * PCMCIA config., multi-function pin tri-state
 244  */
 245 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 246
 247 /*-----------------------------------------------------------------------
 248  * TBSCR - Time Base Status and Control                         11-26
 249  *-----------------------------------------------------------------------
 250  * Clear Reference Interrupt Status, Timebase freezing enabled
 251  */
 252 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 253
 254 /*-----------------------------------------------------------------------
 255  * PISCR - Periodic Interrupt Status and Control                11-31
 256  *-----------------------------------------------------------------------
 257  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 258  */
 259 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 260
 261 /*-----------------------------------------------------------------------
 262  * SCCR - System Clock and reset Control Register               15-27
 263  *-----------------------------------------------------------------------
 264  * Set clock output, timebase and RTC source and divider,
 265  * power management and some other internal clocks
 266  */
 267 #define SCCR_MASK       SCCR_EBDF11
 268 /* #define CFG_SCCR     SCCR_TBS */
 269 #define CFG_SCCR        (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 270                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 271                          SCCR_DFALCD00)
 272
 273 /*-----------------------------------------------------------------------
 274  * DER - Debug Enable Register
 275  *-----------------------------------------------------------------------
 276  * Set to zero to prevent the processor from entering debug mode
 277  */
 278 #define CFG_DER          0
 279
 280
 281 /* Because of the way the 860 starts up and assigns CS0 the entire
 282  * address space, we have to set the memory controller differently.
 283  * Normally, you write the option register first, and then enable the
 284  * chip select by writing the base register.  For CS0, you must write
 285  * the base register first, followed by the option register.
 286  */
 287
 288
 289 /*
 290  * Init Memory Controller:
 291  */
 292
 293 /* BR0 and OR0 (FLASH) */
 294 #define FLASH_BASE0_PRELIM      CFG_FLASH_BASE  /* FLASH bank #0 */
 295
 296
 297 /* used to re-map FLASH both when starting from SRAM or FLASH:
 298  * restrict access enough to keep SRAM working (if any)
 299  * but not too much to meddle with FLASH accesses
 300  */
 301 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 302 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 303
 304 /*
 305  * FLASH timing:
 306  */
 307 #define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 308                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 309
 310 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 311 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 312 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 313
 314
 315 /*
 316  * SDRAM CS1 UPMB
 317  */
 318 #define CFG_SDRAM_BASE  0x00000000
 319 #define CFG_SDRAM_BASE_PRELIM CFG_SDRAM_BASE
 320 #define SDRAM_MAX_SIZE  0x4000000 /* max 64 MB */
 321
 322 #define CFG_PRELIM_OR1_AM       0xF0000000
 323 /* #define CFG_OR1_TIMING  OR_CSNT_SAM/\*  | OR_G5LS /\\* *\\/ *\/ */
 324 #define SDRAM_TIMING    OR_SCY_0_CLK    /* SDRAM-Timing */
 325
 326 #define CFG_OR1_PRELIM  (CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING)
 327 #define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V)
 328
 329 /* #define CFG_OR1_FINAL   ((CFG_OR1_AM & OR_AM_MSK) | CFG_OR1_TIMING) */
 330 /* #define CFG_BR1_FINAL   ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */
 331
 332 #define CFG_PTB_PER_CLK ((4096 * 16 * 1000) / (4 * 64))
 333 #define CFG_PTA_PER_CLK 195
 334 #define CFG_MBMR_PTB    195
 335 #define CFG_MPTPR       MPTPR_PTP_DIV16
 336 #define CFG_MAR         0x88
 337
 338 #define CFG_MBMR_8COL  ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
 339                         MBMR_AMB_TYPE_0 | \
 340                         MBMR_G0CLB_A10 | \
 341                         MBMR_DSB_1_CYCL | \
 342                         MBMR_RLFB_1X | \
 343                         MBMR_WLFB_1X | \
 344                         MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
 345
 346 #define CFG_MBMR_9COL  ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
 347                         MBMR_AMB_TYPE_1 | \
 348                         MBMR_G0CLB_A10 | \
 349                         MBMR_DSB_1_CYCL | \
 350                         MBMR_RLFB_1X | \
 351                         MBMR_WLFB_1X | \
 352                         MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
 353
 354
 355 /*
 356  * DSP Host Port Interface CS3
 357  */
 358 #define CFG_SPC1920_HPI_BASE   0x90000000
 359 #define CFG_PRELIM_OR3_AM      0xF0000000
 360
 361 #define CFG_OR3_PRELIM         (CFG_PRELIM_OR3_AM | \
 362                                        OR_G5LS | \
 363                                        OR_SCY_0_CLK | \
 364                                        OR_BI)
 365
 366 #define CFG_BR3_PRELIM ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \
 367                                                BR_MS_UPMA | \
 368                                                BR_PS_16 | \
 369                                                BR_V);
 370
 371 #define CFG_MAMR (MAMR_GPL_A4DIS | \
 372                 MAMR_RLFA_5X | \
 373                 MAMR_WLFA_5X)
 374
 375 #define CONFIG_SPC1920_HPI_TEST
 376
 377 #ifdef CONFIG_SPC1920_HPI_TEST
 378 #define HPI_REG(x)             (*((volatile u16 *) (CFG_SPC1920_HPI_BASE + x)))
 379 #define HPI_HPIC_1             HPI_REG(0)
 380 #define HPI_HPIC_2             HPI_REG(2)
 381 #define HPI_HPIA_1             HPI_REG(0x2000000)
 382 #define HPI_HPIA_2             HPI_REG(0x2000000 + 2)
 383 #define HPI_HPID_INC_1         HPI_REG(0x1000000)
 384 #define HPI_HPID_INC_2         HPI_REG(0x1000000 + 2)
 385 #define HPI_HPID_NOINC_1       HPI_REG(0x3000000)
 386 #define HPI_HPID_NOINC_2       HPI_REG(0x3000000 + 2)
 387 #endif /* CONFIG_SPC1920_HPI_TEST */
 388
 389 /*
 390  * PLD CS5
 391  */
 392 #define CFG_SPC1920_PLD_BASE    0x80000000
 393 #define CFG_PRELIM_OR5_AM       0xfff00000
 394
 395 #define CFG_OR5_PRELIM          (CFG_PRELIM_OR5_AM | \
 396                                         OR_CSNT_SAM | \
 397                                         OR_ACS_DIV1 | \
 398                                         OR_BI | \
 399                                         OR_SCY_0_CLK | \
 400                                         OR_TRLX)
 401
 402 #define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
 403
 404 /*
 405  * Internal Definitions
 406  *
 407  * Boot Flags
 408  */
 409 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 410 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 411
 412 /* Machine type
 413 */
 414 #define _MACH_8xx (_MACH_fads)
 415
 416 #endif  /* __CONFIG_H */