include/configs/spc1920.h

   1 /*
   2  * (C) Copyright 2006
   3  * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de
   4  *
   5  * Configuation settings for the SPC1920 board.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #ifndef __H
  24 #define __CONFIG_H
  25
  26 #define CONFIG_SPC1920                  1       /* SPC1920 board */
  27 #define CONFIG_MPC885                   1       /* MPC885 CPU */
  28
  29 #define CONFIG_8xx_CONS_SMC1            /* Console is on SMC1 */
  30 #undef  CONFIG_8xx_CONS_SMC2
  31 #undef  CONFIG_8xx_CONS_NONE
  32
  33 #define CONFIG_MII
  34 /* #define MII_DEBUG */
  35 /* #define CONFIG_FEC_ENET */
  36 #undef CONFIG_ETHER_ON_FEC1
  37 #define CONFIG_ETHER_ON_FEC2
  38 #define FEC_ENET
  39 /* #define CONFIG_FEC2_PHY_NORXERR */
  40 /* #define CFG_DISCOVER_PHY */
  41 /* #define CONFIG_PHY_ADDR              0x1 */
  42 #define CONFIG_FEC2_PHY         1
  43
  44 #define CONFIG_BAUDRATE         19200
  45
  46 /* use PLD CLK4 instead of brg */
  47 #define CFG_SPC1920_SMC1_CLK4
  48
  49 #define CONFIG_8xx_OSCLK                10000000 /* 10 MHz oscillator on EXTCLK  */
  50 #define CONFIG_8xx_CPUCLK_DEFAULT       50000000
  51 #define CFG_8xx_CPUCLK_MIN              40000000
  52 #define CFG_8xx_CPUCLK_MAX              133000000
  53
  54 #define CFG_RESET_ADDRESS               0xC0000000
  55
  56 #define CONFIG_BOARD_EARLY_INIT_F
  57 #define CONFIG_LAST_STAGE_INIT
  58
  59 #if 0
  60 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  61 #else
  62 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  63 #endif
  64
  65 #define CONFIG_ENV_OVERWRITE
  66
  67 #define CONFIG_NFSBOOTCOMMAND                                                   \
  68     "dhcp;"                                                                     \
  69     "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath "                       \
  70     "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"              \
  71     "bootm"
  72
  73 #define CONFIG_BOOTCOMMAND                                                      \
  74     "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
  75     "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"              \
  76     "bootm fe080000"
  77
  78 #undef CONFIG_BOOTARGS
  79
  80 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  81 #define CONFIG_BZIP2     /* include support for bzip2 compressed images */
  82
  83
  84 /*
  85  * BOOTP options
  86  */
  87 #define CONFIG_BOOTP_BOOTFILESIZE
  88 #define CONFIG_BOOTP_BOOTPATH
  89 #define CONFIG_BOOTP_GATEWAY
  90 #define CONFIG_BOOTP_HOSTNAME
  91
  92
  93 /*
  94  * Command line configuration.
  95  */
  96 #include <config_cmd_default.h>
  97
  98 #define CONFIG_CMD_ASKENV
  99 #define CONFIG_CMD_DATE
 100 #define CONFIG_CMD_ECHO
 101 #define CONFIG_CMD_IMMAP
 102 #define CONFIG_CMD_JFFS2
 103 #define CONFIG_CMD_PING
 104 #define CONFIG_CMD_DHCP
 105 #define CONFIG_CMD_I2C
 106 #define CONFIG_CMD_MII
 107
 108 #undef CONFIG_CMD_NET
 109
 110
 111 /*
 112  * Miscellaneous configurable options
 113  */
 114 #define CFG_LONGHELP                            /* undef to save memory         */
 115 #define CFG_PROMPT              "=>"            /* Monitor Command Prompt       */
 116 #define CFG_HUSH_PARSER
 117 #define CFG_PROMPT_HUSH_PS2     "> "
 118
 119 #if defined(CONFIG_CMD_KGDB)
 120 #define CFG_CBSIZE              1024            /* Console I/O Buffer Size      */
 121 #else
 122 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 123 #endif
 124
 125 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size  */
 126 #define CFG_MAXARGS             16              /* max number of command args   */
 127 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 128
 129 #define CFG_LOAD_ADDR           0x00100000
 130
 131 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 132
 133 #define CFG_BAUDRATE_TABLE      { 2400, 4800, 9600, 19200 }
 134
 135 /*
 136  * Low Level Configuration Settings
 137  * (address mappings, register initial values, etc.)
 138  * You should know what you are doing if you make changes here.
 139  */
 140
 141 /*-----------------------------------------------------------------------
 142  * Internal Memory Mapped Register
 143  */
 144 #define CFG_IMMR                0xF0000000
 145
 146 /*-----------------------------------------------------------------------
 147  * Definitions for initial stack pointer and data area (in DPRAM)
 148  */
 149 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 150 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 151 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 152 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 153 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 154
 155 /*-----------------------------------------------------------------------
 156  * Start addresses for the final memory configuration
 157  * (Set up by the startup code)
 158  * Please note that CFG_SDRAM_BASE _must_ start at 0
 159  */
 160 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 161 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 162
 163 /*
 164  * For booting Linux, the board info and command line data
 165  * have to be in the first 8 MB of memory, since this is
 166  * the maximum mapped by the Linux kernel during initialization.
 167  */
 168 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 169
 170 #define CFG_MONITOR_BASE        TEXT_BASE
 171 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 KB for monitor   */
 172
 173 #ifdef CONFIG_BZIP2
 174 #define CFG_MALLOC_LEN          (2500 << 10)    /* Reserve ~2.5 MB for malloc() */
 175 #else
 176 #define CFG_MALLOC_LEN          (384 << 10)     /* Reserve 384 kB for malloc()  */
 177 #endif /* CONFIG_BZIP2 */
 178
 179 #define CFG_ALLOC_DPRAM         1       /* use allocation routines      */
 180
 181 /*
 182  * Flash
 183  */
 184 /*-----------------------------------------------------------------------
 185  * Flash organisation
 186  */
 187 #define CFG_FLASH_BASE          0xFE000000
 188 #define CFG_FLASH_CFI                           /* The flash is CFI compatible  */
 189 #define CFG_FLASH_CFI_DRIVER                    /* Use common CFI driver        */
 190 #define CFG_MAX_FLASH_BANKS     1               /* Max number of flash banks    */
 191 #define CFG_MAX_FLASH_SECT      128             /* Max num of sects on one chip */
 192
 193 /* Environment is in flash */
 194 #define CFG_ENV_IS_IN_FLASH
 195 #define CFG_ENV_SECT_SIZE       0x40000         /* We use one complete sector   */
 196 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 197
 198 #define CONFIG_ENV_OVERWRITE
 199
 200 /*-----------------------------------------------------------------------
 201  * Cache Configuration
 202  */
 203 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 204 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 205
 206 #ifdef CONFIG_CMD_DATE
 207 # define CONFIG_RTC_DS3231
 208 # define CFG_I2C_RTC_ADDR      0x68
 209 #endif
 210
 211 /*-----------------------------------------------------------------------
 212  * I2C configuration
 213  */
 214 #if defined(CONFIG_CMD_I2C)
 215 /* enable I2C and select the hardware/software driver */
 216 #undef CONFIG_HARD_I2C                 /* I2C with hardware support    */
 217 #define CONFIG_SOFT_I2C                1       /* I2C bit-banged               */
 218
 219 #define CFG_I2C_SPEED          93000   /* 93 kHz is supposed to work   */
 220 #define CFG_I2C_SLAVE          0xFE
 221
 222 #ifdef CONFIG_SOFT_I2C
 223 /*
 224  * Software (bit-bang) I2C driver configuration
 225  */
 226 #define PB_SCL         0x00000020      /* PB 26 */
 227 #define PB_SDA         0x00000010      /* PB 27 */
 228
 229 #define I2C_INIT       (immr->im_cpm.cp_pbdir |=  PB_SCL)
 230 #define I2C_ACTIVE     (immr->im_cpm.cp_pbdir |=  PB_SDA)
 231 #define I2C_TRISTATE   (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 232 #define I2C_READ       ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 233 #define I2C_SDA(bit)   if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 234                        else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 235 #define I2C_SCL(bit)   if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 236                        else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 237 #define I2C_DELAY      udelay(2)       /* 1/4 I2C clock duration */
 238 #endif /* CONFIG_SOFT_I2C */
 239 #endif
 240
 241 /*-----------------------------------------------------------------------
 242  * SYPCR - System Protection Control                            11-9
 243  * SYPCR can only be written once after reset!
 244  *-----------------------------------------------------------------------
 245  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 246  */
 247 #if defined(CONFIG_WATCHDOG)
 248 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 249                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 250 #else
 251 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 252 #endif
 253
 254 /*-----------------------------------------------------------------------
 255  * SIUMCR - SIU Module Configuration                            11-6
 256  *-----------------------------------------------------------------------
 257  * PCMCIA config., multi-function pin tri-state
 258  */
 259 #define CFG_SIUMCR      (SIUMCR_FRC)
 260
 261 /*-----------------------------------------------------------------------
 262  * TBSCR - Time Base Status and Control                         11-26
 263  *-----------------------------------------------------------------------
 264  * Clear Reference Interrupt Status, Timebase freezing enabled
 265  */
 266 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 267
 268 /*-----------------------------------------------------------------------
 269  * PISCR - Periodic Interrupt Status and Control                11-31
 270  *-----------------------------------------------------------------------
 271  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 272  */
 273 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 274
 275 /*-----------------------------------------------------------------------
 276  * SCCR - System Clock and reset Control Register               15-27
 277  *-----------------------------------------------------------------------
 278  * Set clock output, timebase and RTC source and divider,
 279  * power management and some other internal clocks
 280  */
 281 #define SCCR_MASK       SCCR_EBDF11
 282 /* #define CFG_SCCR     SCCR_TBS */
 283 #define CFG_SCCR        (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 284                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 285                          SCCR_DFALCD00)
 286
 287 /*-----------------------------------------------------------------------
 288  * DER - Debug Enable Register
 289  *-----------------------------------------------------------------------
 290  * Set to zero to prevent the processor from entering debug mode
 291  */
 292 #define CFG_DER          0
 293
 294
 295 /* Because of the way the 860 starts up and assigns CS0 the entire
 296  * address space, we have to set the memory controller differently.
 297  * Normally, you write the option register first, and then enable the
 298  * chip select by writing the base register.  For CS0, you must write
 299  * the base register first, followed by the option register.
 300  */
 301
 302
 303 /*
 304  * Init Memory Controller:
 305  */
 306
 307 /* BR0 and OR0 (FLASH) */
 308 #define FLASH_BASE0_PRELIM      CFG_FLASH_BASE  /* FLASH bank #0 */
 309
 310
 311 /* used to re-map FLASH both when starting from SRAM or FLASH:
 312  * restrict access enough to keep SRAM working (if any)
 313  * but not too much to meddle with FLASH accesses
 314  */
 315 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 316 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 317
 318 /*
 319  * FLASH timing:
 320  */
 321 #define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 322                                  OR_SCY_6_CLK | OR_EHTR | OR_BI)
 323
 324 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 325 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 326 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 327
 328
 329 /*
 330  * SDRAM CS1 UPMB
 331  */
 332 #define CFG_SDRAM_BASE  0x00000000
 333 #define CFG_SDRAM_BASE_PRELIM CFG_SDRAM_BASE
 334 #define SDRAM_MAX_SIZE  0x4000000 /* max 64 MB */
 335
 336 #define CFG_PRELIM_OR1_AM       0xF0000000
 337 /* #define CFG_OR1_TIMING  OR_CSNT_SAM/\*  | OR_G5LS /\\* *\\/ *\/ */
 338 #define SDRAM_TIMING    OR_SCY_0_CLK    /* SDRAM-Timing */
 339
 340 #define CFG_OR1_PRELIM  (CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING)
 341 #define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V)
 342
 343 /* #define CFG_OR1_FINAL   ((CFG_OR1_AM & OR_AM_MSK) | CFG_OR1_TIMING) */
 344 /* #define CFG_BR1_FINAL   ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */
 345
 346 #define CFG_PTB_PER_CLK ((4096 * 16 * 1000) / (4 * 64))
 347 #define CFG_PTA_PER_CLK 195
 348 #define CFG_MBMR_PTB    195
 349 #define CFG_MPTPR       MPTPR_PTP_DIV16
 350 #define CFG_MAR         0x88
 351
 352 #define CFG_MBMR_8COL  ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
 353                         MBMR_AMB_TYPE_0 | \
 354                         MBMR_G0CLB_A10 | \
 355                         MBMR_DSB_1_CYCL | \
 356                         MBMR_RLFB_1X | \
 357                         MBMR_WLFB_1X | \
 358                         MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
 359
 360 #define CFG_MBMR_9COL  ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
 361                         MBMR_AMB_TYPE_1 | \
 362                         MBMR_G0CLB_A10 | \
 363                         MBMR_DSB_1_CYCL | \
 364                         MBMR_RLFB_1X | \
 365                         MBMR_WLFB_1X | \
 366                         MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
 367
 368
 369 /*
 370  * DSP Host Port Interface CS3
 371  */
 372 #define CFG_SPC1920_HPI_BASE   0x90000000
 373 #define CFG_PRELIM_OR3_AM      0xF8000000
 374
 375 #define CFG_OR3         (CFG_PRELIM_OR3_AM | \
 376                                        OR_G5LS | \
 377                                        OR_SCY_0_CLK | \
 378                                        OR_BI)
 379
 380 #define CFG_BR3 ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \
 381                                                BR_MS_UPMA | \
 382                                                BR_PS_16 | \
 383                                                BR_V);
 384
 385 #define CFG_MAMR (MAMR_GPL_A4DIS | \
 386                 MAMR_RLFA_5X | \
 387                 MAMR_WLFA_5X)
 388
 389 #define CONFIG_SPC1920_HPI_TEST
 390
 391 #ifdef CONFIG_SPC1920_HPI_TEST
 392 #define HPI_REG(x)             (*((volatile u16 *) (CFG_SPC1920_HPI_BASE + x)))
 393 #define HPI_HPIC_1             HPI_REG(0)
 394 #define HPI_HPIC_2             HPI_REG(2)
 395 #define HPI_HPIA_1             HPI_REG(0x2000008)
 396 #define HPI_HPIA_2             HPI_REG(0x2000008 + 2)
 397 #define HPI_HPID_INC_1         HPI_REG(0x1000004)
 398 #define HPI_HPID_INC_2         HPI_REG(0x1000004 + 2)
 399 #define HPI_HPID_NOINC_1       HPI_REG(0x300000c)
 400 #define HPI_HPID_NOINC_2       HPI_REG(0x300000c + 2)
 401 #endif /* CONFIG_SPC1920_HPI_TEST */
 402
 403 /*
 404  * Ramtron FM18L08 FRAM 32KB on CS4
 405  */
 406 #define CFG_SPC1920_FRAM_BASE   0x80100000
 407 #define CFG_PRELIM_OR4_AM       0xffff8000
 408 #define CFG_OR4         (CFG_PRELIM_OR4_AM | \
 409                                         OR_ACS_DIV2 | \
 410                                         OR_BI | \
 411                                         OR_SCY_4_CLK | \
 412                                         OR_TRLX)
 413
 414 #define CFG_BR4 ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
 415
 416 /*
 417  * PLD CS5
 418  */
 419 #define CFG_SPC1920_PLD_BASE    0x80000000
 420 #define CFG_PRELIM_OR5_AM       0xffff8000
 421
 422 #define CFG_OR5_PRELIM          (CFG_PRELIM_OR5_AM | \
 423                                         OR_CSNT_SAM | \
 424                                         OR_ACS_DIV1 | \
 425                                         OR_BI | \
 426                                         OR_SCY_0_CLK | \
 427                                         OR_TRLX)
 428
 429 #define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
 430
 431 /*
 432  * Internal Definitions
 433  *
 434  * Boot Flags
 435  */
 436 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 437 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 438
 439 /* Machine type
 440 */
 441 #define _MACH_8xx (_MACH_fads)
 442
 443 #endif  /* __CONFIG_H */