include/configs/spieval.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004-2005
   6  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * High Level Configuration Options
  32  * (easy to change)
  33  */
  34
  35 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  36 #define CONFIG_MPC5200          1       /* (more precisely an MPC5200 CPU) */
  37 #define CONFIG_TQM5200          1       /* ... on TQM5200 module */
  38 #undef CONFIG_TQM5200_REV100            /*  define for revision 100 modules */
  39 #define CONFIG_STK52XX          1       /* ... on a STK52XX base board */
  40 #define CONFIG_STK52XX_REV100   1       /*  define for revision 100 baseboards */
  41
  42 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz */
  43
  44 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  45
  46 /*
  47  * Serial console configuration
  48  */
  49 #define CONFIG_PSC_CONSOLE      6       /* console is on PSC6 */
  50 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  51 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  52
  53 #ifdef CONFIG_STK52XX
  54 #undef CONFIG_PS2KBD                    /* AT-PS/2 Keyboard             */
  55 #define CONFIG_PS2MULT                  /* .. on PS/2 Multiplexer       */
  56 #define CONFIG_PS2SERIAL        6       /* .. on PSC6                   */
  57 #define CONFIG_PS2MULT_DELAY    (CONFIG_SYS_HZ/2)       /* Initial delay        */
  58 #define CONFIG_BOARD_EARLY_INIT_R
  59 #endif /* CONFIG_STK52XX */
  60
  61 /*
  62  * PCI Mapping:
  63  * 0x40000000 - 0x4fffffff - PCI Memory
  64  * 0x50000000 - 0x50ffffff - PCI IO Space
  65  */
  66 #ifdef CONFIG_STK52XX
  67 #define CONFIG_PCI              1
  68 #define CONFIG_PCI_PNP          1
  69 /* #define CONFIG_PCI_SCAN_SHOW 1 */
  70
  71 #define CONFIG_PCI_MEM_BUS      0x40000000
  72 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  73 #define CONFIG_PCI_MEM_SIZE     0x10000000
  74
  75 #define CONFIG_PCI_IO_BUS       0x50000000
  76 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  77 #define CONFIG_PCI_IO_SIZE      0x01000000
  78
  79 #define CONFIG_EEPRO100         1
  80 #define CONFIG_SYS_RX_ETH_BUFFER        8  /* use 8 rx buffer on eepro100  */
  81 #define CONFIG_NS8382X          1
  82 #endif  /* CONFIG_STK52XX */
  83
  84 /*
  85  * Video console
  86  */
  87 #if 1
  88 #define CONFIG_VIDEO
  89 #define CONFIG_VIDEO_SM501
  90 #define CONFIG_VIDEO_SM501_32BPP
  91 #define CONFIG_CFB_CONSOLE
  92 #define CONFIG_VIDEO_LOGO
  93 #define CONFIG_VGA_AS_SINGLE_DEVICE
  94 #define CONFIG_CONSOLE_EXTRA_INFO
  95 #define CONFIG_VIDEO_SW_CURSOR
  96 #define CONFIG_SPLASH_SCREEN
  97 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
  98 #endif
  99
 100 /* Partitions */
 101 #define CONFIG_MAC_PARTITION
 102 #define CONFIG_DOS_PARTITION
 103 #define CONFIG_ISO_PARTITION
 104
 105 /* USB */
 106 #ifdef CONFIG_STK52XX
 107 #define CONFIG_USB_OHCI
 108 #define CONFIG_USB_STORAGE
 109 #endif
 110
 111 /* POST support */
 112 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY   | \
 113                                  CONFIG_SYS_POST_CPU       | \
 114                                  CONFIG_SYS_POST_I2C)
 115
 116 #ifdef CONFIG_POST
 117 /* preserve space for the post_word at end of on-chip SRAM */
 118 #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
 119 #endif
 120
 121
 122 /*
 123  * BOOTP options
 124  */
 125 #define CONFIG_BOOTP_BOOTFILESIZE
 126 #define CONFIG_BOOTP_BOOTPATH
 127 #define CONFIG_BOOTP_GATEWAY
 128 #define CONFIG_BOOTP_HOSTNAME
 129
 130
 131 /*
 132  * Command line configuration.
 133  */
 134 #include <config_cmd_default.h>
 135
 136 #define CONFIG_CMD_ASKENV
 137 #define CONFIG_CMD_DATE
 138 #define CONFIG_CMD_DHCP
 139 #define CONFIG_CMD_ECHO
 140 #define CONFIG_CMD_EEPROM
 141 #define CONFIG_CMD_I2C
 142 #define CONFIG_CMD_MII
 143 #define CONFIG_CMD_NFS
 144 #define CONFIG_CMD_PING
 145 #define CONFIG_CMD_REGINFO
 146 #define CONFIG_CMD_SNTP
 147
 148 #if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
 149     #define CONFIG_CMD_IDE
 150     #define CONFIG_CMD_FAT
 151     #define CONFIG_CMD_EXT2
 152 #endif
 153
 154 #ifdef CONFIG_STK52XX
 155     #define CONFIG_CMD_USB
 156     #define CONFIG_CMD_FAT
 157 #endif
 158
 159 #ifdef CONFIG_VIDEO
 160     #define CONFIG_CMD_BMP
 161 #endif
 162
 163 #ifdef CONFIG_PCI
 164     #define CONFIG_CMD_PCI
 165     #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE     1
 166 #endif
 167
 168 #ifdef CONFIG_POST
 169 #define CONFIG_CMD_DIAG
 170 #endif
 171
 172
 173 #define CONFIG_TIMESTAMP                /* display image timestamps */
 174
 175 #if (CONFIG_SYS_TEXT_BASE == 0xFC000000)                /* Boot low */
 176 #   define CONFIG_SYS_LOWBOOT           1
 177 #endif
 178
 179 /*
 180  * Autobooting
 181  */
 182 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 183
 184 #define CONFIG_PREBOOT  "echo;" \
 185         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 186         "echo"
 187
 188 #undef  CONFIG_BOOTARGS
 189
 190 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 191         "netdev=eth0\0"                                                 \
 192         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 193         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 194         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 195                 "nfsroot=${serverip}:${rootpath}\0"                     \
 196         "addip=setenv bootargs ${bootargs} "                            \
 197                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 198                 ":${hostname}:${netdev}:off panic=1\0"                  \
 199         "flash_self=run ramargs addip;"                                 \
 200                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 201         "flash_nfs=run nfsargs addip;"                                  \
 202                 "bootm ${kernel_addr}\0"                                \
 203         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 204         "bootfile=/tftpboot/tqm5200/uImage\0"                           \
 205         "load=tftp 200000 ${u-boot}\0"                                  \
 206         "u-boot=/tftpboot/tqm5200/u-boot.bin\0"                         \
 207         "update=protect off FC000000 FC05FFFF;"                         \
 208                 "erase FC000000 FC05FFFF;"                              \
 209                 "cp.b 200000 FC000000 ${filesize};"                     \
 210                 "protect on FC000000 FC05FFFF\0"                        \
 211         ""
 212
 213 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 214
 215 /*
 216  * IPB Bus clocking configuration.
 217  */
 218 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 219
 220 #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
 221 /*
 222  * PCI Bus clocking configuration
 223  *
 224  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 225  * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 226  * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 227  */
 228 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2    /* define for 66MHz speed */
 229 #endif
 230
 231 /*
 232  * I2C configuration
 233  */
 234 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 235 #ifdef CONFIG_TQM5200_REV100
 236 #define CONFIG_SYS_I2C_MODULE           1       /* Select I2C module #1 for rev. 100 board */
 237 #else
 238 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #2 for all other revs */
 239 #endif
 240
 241 /*
 242  * I2C clock frequency
 243  *
 244  * Please notice, that the resulting clock frequency could differ from the
 245  * configured value. This is because the I2C clock is derived from system
 246  * clock over a frequency divider with only a few divider values. U-boot
 247  * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
 248  * approximation allways lies below the configured value, never above.
 249  */
 250 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 251 #define CONFIG_SYS_I2C_SLAVE            0x7F
 252
 253 /*
 254  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
 255  * also). For other EEPROMs configuration should be verified. On Mini-FAP the
 256  * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
 257  * same configuration could be used.
 258  */
 259 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 260 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 261 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* =32 Bytes per write */
 262 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   20
 263
 264 /*
 265  * HW-Monitor configuration on Mini-FAP
 266  */
 267 #if defined (CONFIG_MINIFAP)
 268 #define CONFIG_SYS_I2C_HWMON_ADDR               0x2C
 269 #endif
 270
 271 /* List of I2C addresses to be verified by POST */
 272 #if defined (CONFIG_MINIFAP)
 273 #undef CONFIG_SYS_POST_I2C_ADDRS
 274 #define CONFIG_SYS_POST_I2C_ADDRS       {CONFIG_SYS_I2C_EEPROM_ADDR,    \
 275                                          CONFIG_SYS_I2C_HWMON_ADDR,     \
 276                                          CONFIG_SYS_I2C_SLAVE}
 277 #endif
 278
 279 /*
 280  * Flash configuration
 281  */
 282 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
 283
 284 /* use CFI flash driver if no module variant is spezified */
 285 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 286 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 287 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_BOOTCS_START }
 288 #define CONFIG_SYS_FLASH_EMPTY_INFO
 289 #define CONFIG_SYS_FLASH_SIZE           0x04000000 /* 64 MByte */
 290 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sects on one chip */
 291 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE        /* not supported yet for AMD */
 292
 293 #if !defined(CONFIG_SYS_LOWBOOT)
 294 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
 295 #else   /* CONFIG_SYS_LOWBOOT */
 296 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00060000)
 297 #endif  /* CONFIG_SYS_LOWBOOT */
 298 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks
 299                                            (= chip selects) */
 300 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 301 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 302
 303
 304 /*
 305  * Environment settings
 306  */
 307 #define CONFIG_ENV_IS_IN_FLASH  1
 308 #define CONFIG_ENV_SIZE         0x10000
 309 #define CONFIG_ENV_SECT_SIZE    0x20000
 310 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 311 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 312
 313 /*
 314  * Memory map
 315  */
 316 #define CONFIG_SYS_MBAR         0xF0000000
 317 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 318 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 319
 320 /* Use ON-Chip SRAM until RAM will be available */
 321 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 322 #ifdef CONFIG_POST
 323 /* preserve space for the post_word at end of on-chip SRAM */
 324 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_POST_SIZE
 325 #else
 326 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
 327 #endif
 328
 329
 330 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 331 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 332
 333 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 334 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 335 #   define CONFIG_SYS_RAMBOOT           1
 336 #endif
 337
 338 #define CONFIG_SYS_MONITOR_LEN          (384 << 10)     /* Reserve 384 kB for Monitor   */
 339 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 340 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 341
 342 /*
 343  * Ethernet configuration
 344  */
 345 #define CONFIG_MPC5xxx_FEC      1
 346 /*
 347  * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 348  */
 349 /* #define CONFIG_FEC_10MBIT 1 */
 350 #define CONFIG_PHY_ADDR         0x00
 351
 352 /*
 353  * GPIO configuration
 354  *
 355  * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
 356  *      Bit 0 (mask: 0x80000000): 1
 357  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 358  *      00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
 359  *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
 360  *            Use for REV200 STK52XX boards. Do not use with REV100 modules
 361  *            (because, there I2C1 is used as I2C bus)
 362  * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 363  * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
 364  *      000 -> All PSC2 pins are GIOPs
 365  *      001 -> CAN1/2 on PSC2 pins
 366  *             Use for REV100 STK52xx boards
 367  * use PSC6:
 368  *   on STK52xx:
 369  *      use as UART. Pins PSC6_0 to PSC6_3 are used.
 370  *      Bits 9:11 (mask: 0x00700000):
 371  *         101 -> PSC6 : Extended POST test is not available
 372  *   on MINI-FAP and TQM5200_IB:
 373  *      use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
 374  *         000 -> PSC6 could not be used as UART, CODEC or IrDA
 375  *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
 376  *   tests.
 377  */
 378 #if defined (CONFIG_MINIFAP)
 379 # define CONFIG_SYS_GPS_PORT_CONFIG     0x91000004
 380 #elif defined (CONFIG_STK52XX)
 381 # if defined (CONFIG_STK52XX_REV100)
 382 #  define CONFIG_SYS_GPS_PORT_CONFIG    0x81500014
 383 # else /* STK52xx REV200 and above */
 384 #  if defined (CONFIG_TQM5200_REV100)
 385 #   error TQM5200 REV100 not supported on STK52XX REV200 or above
 386 #  else/* TQM5200 REV200 and above */
 387 #   define CONFIG_SYS_GPS_PORT_CONFIG   0x91500004
 388 #  endif
 389 # endif
 390 #else  /* TMQ5200 Inbetriebnahme-Board */
 391 # define CONFIG_SYS_GPS_PORT_CONFIG     0x81000004
 392 #endif
 393
 394 /*
 395  * RTC configuration
 396  */
 397 #define CONFIG_RTC_MPC5200      1       /* use internal MPC5200 RTC */
 398
 399 /*
 400  * Miscellaneous configurable options
 401  */
 402 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 403 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 404 #if defined(CONFIG_CMD_KGDB)
 405 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 406 #else
 407 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 408 #endif
 409 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 410 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 411 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 412
 413 /* Enable an alternate, more extensive memory test */
 414 #define CONFIG_SYS_ALT_MEMTEST
 415
 416 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 417 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 418
 419 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 420
 421 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 422
 423 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 424 #if defined(CONFIG_CMD_KGDB)
 425 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 426 #endif
 427
 428 /*
 429  * Enable loopw command.
 430  */
 431 #define CONFIG_LOOPW
 432
 433 /*
 434  * Various low-level settings
 435  */
 436 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 437 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 438
 439 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 440 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 441 #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
 442 #define CONFIG_SYS_BOOTCS_CFG           0x0008DF30 /* for pci_clk  = 66 MHz */
 443 #else
 444 #define CONFIG_SYS_BOOTCS_CFG           0x0004DF30 /* for pci_clk = 33 MHz */
 445 #endif
 446 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 447 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 448
 449 #define CONFIG_LAST_STAGE_INIT
 450
 451 /*
 452  * SRAM - Do not map below 2 GB in address space, because this area is used
 453  * for SDRAM autosizing.
 454  */
 455 #define CONFIG_SYS_CS2_START            0xE5000000
 456 #define CONFIG_SYS_CS2_SIZE             0x100000        /* 1 MByte */
 457 #define CONFIG_SYS_CS2_CFG              0x0004D930
 458
 459 /*
 460  * Grafic controller - Do not map below 2 GB in address space, because this
 461  * area is used for SDRAM autosizing.
 462  */
 463 #define SM501_FB_BASE           0xE0000000
 464 #define CONFIG_SYS_CS1_START            (SM501_FB_BASE)
 465 #define CONFIG_SYS_CS1_SIZE             0x4000000       /* 64 MByte */
 466 #define CONFIG_SYS_CS1_CFG              0x8F48FF70
 467 #define SM501_MMIO_BASE         CONFIG_SYS_CS1_START + 0x03E00000
 468
 469 #define CONFIG_SYS_CS_BURST             0x00000000
 470 #define CONFIG_SYS_CS_DEADCYCLE 0x33333311      /* 1 dead cycle for flash and SM501 */
 471
 472 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 473
 474 /*-----------------------------------------------------------------------
 475  * USB stuff
 476  *-----------------------------------------------------------------------
 477  */
 478 #define CONFIG_USB_CLOCK        0x0001BBBB
 479 #define CONFIG_USB_CONFIG       0x00001000
 480
 481 /*-----------------------------------------------------------------------
 482  * IDE/ATA stuff Supports IDE harddisk
 483  *-----------------------------------------------------------------------
 484  */
 485
 486 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 487
 488 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 489 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 490
 491 #define CONFIG_IDE_RESET                /* reset for ide supported      */
 492 #define CONFIG_IDE_PREINIT
 493
 494 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 495 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 2 drives per IDE bus    */
 496
 497 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 498
 499 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 500
 501 /* Offset for data I/O                  */
 502 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 503
 504 /* Offset for normal register accesses  */
 505 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 506
 507 /* Offset for alternate registers       */
 508 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 509
 510 /* Interval between registers                                                */
 511 #define CONFIG_SYS_ATA_STRIDE           4
 512
 513 #endif /* __CONFIG_H */