include/configs/stxgp3.h

   1 /*
   2  * (C) Copyright 2003 Embedded Edge, LLC
   3  * Dan Malek <dan@embeddededge.com>
   4  * Copied from ADS85xx.
   5  * Updates for Silicon Tx GP3 8560 board.
   6  *
   7  * (C) Copyright 2002,2003 Motorola,Inc.
   8  * Xianghua Xiao <X.Xiao@motorola.com>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 /* mpc8560ads board configuration file */
  14 /* please refer to doc/README.mpc85xx for more info */
  15 /* make sure you change the MAC address and other network params first,
  16  * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
  17  */
  18
  19 #ifndef __CONFIG_H
  20 #define __CONFIG_H
  21
  22 /* High Level Configuration Options */
  23 #define CONFIG_BOOKE            1       /* BOOKE                */
  24 #define CONFIG_E500             1       /* BOOKE e500 family    */
  25 #define CONFIG_CPM2             1       /* has CPM2 */
  26 #define CONFIG_STXGP3           1       /* Silicon Tx GPPP board specific*/
  27 #define CONFIG_MPC8560          1
  28
  29 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  30
  31 #undef  CONFIG_PCI                      /* pci ethernet support */
  32 #define CONFIG_TSEC_ENET                /* tsec ethernet support*/
  33 #undef  CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
  34 #define CONFIG_ENV_OVERWRITE
  35
  36 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  37
  38 /* sysclk for MPC85xx
  39  */
  40
  41 #define CONFIG_SYS_CLK_FREQ     33333333 /* most pci cards are 33Mhz */
  42
  43 /* Blinkin' LEDs for Robert :-)
  44 */
  45 #define CONFIG_SHOW_ACTIVITY 1
  46
  47 /*
  48  * These can be toggled for performance analysis, otherwise use default.
  49  */
  50 #define CONFIG_L2_CACHE                     /* toggle L2 cache         */
  51 #define  CONFIG_BTB                          /* toggle branch predition */
  52
  53 #define CONFIG_BOARD_EARLY_INIT_F   1        /* Call board_pre_init      */
  54 #define CONFIG_RESET_PHY_R      1       /* Call reset_phy()             */
  55
  56 #undef  CONFIG_SYS_DRAM_TEST                       /* memory test, takes time  */
  57 #define CONFIG_SYS_MEMTEST_START       0x00200000  /* memtest region */
  58 #define CONFIG_SYS_MEMTEST_END         0x00400000
  59
  60
  61 /* Localbus SDRAM is an option, not all boards have it.
  62  * This address, however, is used to configure a 256M local bus
  63  * window that includes the Config latch below.
  64  */
  65 #define CONFIG_SYS_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
  66 #define CONFIG_SYS_LBC_SDRAM_SIZE       256             /* LBC SDRAM is 64MB    */
  67
  68 #define CONFIG_SYS_FLASH_BASE        0xff000000      /* start of FLASH 16M    */
  69 #define CONFIG_SYS_BR0_PRELIM        0xff001801      /* port size 32bit      */
  70
  71 #define CONFIG_SYS_OR0_PRELIM          0xff000ff7      /* 16 MB Flash           */
  72 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks      */
  73 #define CONFIG_SYS_MAX_FLASH_SECT       136             /* sectors per device   */
  74 #undef  CONFIG_SYS_FLASH_CHECKSUM
  75 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Timeout for Flash Erase (in ms)      */
  76 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
  77
  78 /* The configuration latch is Chip Select 1.
  79  * It's an 8-bit latch in the lower 8 bits of the word.
  80  */
  81 #define CONFIG_SYS_BR1_PRELIM           0xfc001801      /* 32-bit port */
  82 #define CONFIG_SYS_OR1_PRELIM           0xffff0ff7      /* 64K is enough */
  83 #define CONFIG_SYS_LBC_LCLDEVS_BASE     0xfc000000      /* Base of localbus devices */
  84
  85 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor     */
  86
  87 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  88 #define CONFIG_SYS_RAMBOOT
  89 #else
  90 #undef  CONFIG_SYS_RAMBOOT
  91 #endif
  92
  93 #ifdef CONFIG_SYS_RAMBOOT
  94 #define CONFIG_SYS_CCSRBAR_DEFAULT      0x40000000      /* CCSRBAR by BDI cfg   */
  95 #endif
  96 #define CONFIG_SYS_CCSRBAR              0xfdf00000
  97 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  98
  99 /* DDR Setup */
 100 #define CONFIG_SYS_FSL_DDR1
 101 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
 102 #define CONFIG_DDR_SPD
 103 #undef CONFIG_FSL_DDR_INTERACTIVE
 104
 105 #undef  CONFIG_DDR_ECC                  /* only for ECC DDR module */
 106 #define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN     /* possible DLL fix needed */
 107 #define CONFIG_DDR_2T_TIMING            /* Sets the 2T timing bit */
 108
 109 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 110
 111 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 112 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 113
 114 #define CONFIG_NUM_DDR_CONTROLLERS      1
 115 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 116 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 117
 118 /* I2C addresses of SPD EEPROMs */
 119 #define SPD_EEPROM_ADDRESS      0x54    /* CTLR 0 DIMM 0 */
 120
 121 #undef CONFIG_CLOCKS_IN_MHZ
 122
 123 /* local bus definitions */
 124 #define CONFIG_SYS_BR2_PRELIM           0xf8001861      /* 64MB localbus SDRAM  */
 125 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 126 #define CONFIG_SYS_LBC_LCRR             0x00030004      /* local bus freq       */
 127 #define CONFIG_SYS_LBC_LBCR             0x00000000
 128 #define CONFIG_SYS_LBC_LSRT             0x20000000
 129 #define CONFIG_SYS_LBC_MRTPR            0x20000000
 130 #define CONFIG_SYS_LBC_LSDMR_1          0x2861b723
 131 #define CONFIG_SYS_LBC_LSDMR_2          0x0861b723
 132 #define CONFIG_SYS_LBC_LSDMR_3          0x0861b723
 133 #define CONFIG_SYS_LBC_LSDMR_4          0x1861b723
 134 #define CONFIG_SYS_LBC_LSDMR_5          0x4061b723
 135
 136 #define CONFIG_SYS_INIT_RAM_LOCK        1
 137 #define CONFIG_SYS_INIT_RAM_ADDR       0x60000000      /* Initial RAM address  */
 138 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 139
 140 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 141 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 142
 143 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 144 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 145
 146 /* Serial Port */
 147 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
 148 #undef  CONFIG_CONS_NONE                /* define if console on something else */
 149 #define CONFIG_CONS_INDEX       2       /* which serial channel for console */
 150
 151 #define CONFIG_BAUDRATE         38400
 152
 153 #define CONFIG_SYS_BAUDRATE_TABLE  \
 154         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 155
 156 /* Use the HUSH parser */
 157 #define CONFIG_SYS_HUSH_PARSER
 158 #ifdef  CONFIG_SYS_HUSH_PARSER
 159 #endif
 160
 161 /*
 162  * I2C
 163  */
 164 #define CONFIG_SYS_I2C
 165 #define CONFIG_SYS_I2C_FSL
 166 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 167 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 168 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 169
 170 #if 0
 171 #define CONFIG_SYS_I2C_NOPROBES        {0x00}  /* Don't probe these addrs */
 172 #else
 173 /* I did the 'if 0' so we could keep the syntax above if ever needed. */
 174 #undef CONFIG_SYS_I2C_NOPROBES
 175 #endif
 176
 177 /* RapdIO Map configuration, mapped 1:1.
 178 */
 179 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000
 180 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
 181 #define CONFIG_SYS_RIO_MEM_SIZE 0x200000000     /* 512 M */
 182
 183 /* Standard 8560 PCI addressing, mapped 1:1.
 184 */
 185 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 186 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 187 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 188 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
 189 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
 190 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000      /* 16 M */
 191
 192 #if defined(CONFIG_PCI)                 /* PCI Ethernet card */
 193
 194 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 195
 196 #undef CONFIG_EEPRO100
 197 #undef CONFIG_TULIP
 198
 199 #if !defined(CONFIG_PCI_PNP)
 200   #define PCI_ENET0_IOADDR      0xe0000000
 201   #define PCI_ENET0_MEMADDR     0xe0000000
 202   #define PCI_IDSEL_NUMBER      0x0c    /* slot0->3(IDSEL)=12->15 */
 203 #endif
 204
 205 #undef CONFIG_PCI_SCAN_SHOW
 206 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 207
 208 #endif /* CONFIG_PCI */
 209
 210 #if defined(CONFIG_TSEC_ENET)
 211
 212 #define CONFIG_MII              1       /* MII PHY management           */
 213
 214 #define CONFIG_TSEC1    1
 215 #define CONFIG_TSEC1_NAME       "TSEC0"
 216 #define CONFIG_TSEC2    1
 217 #define CONFIG_TSEC2_NAME       "TSEC1"
 218
 219 #define TSEC1_PHY_ADDR          2
 220 #define TSEC2_PHY_ADDR          4
 221 #define TSEC1_PHYIDX            0
 222 #define TSEC2_PHYIDX            0
 223 #define TSEC1_FLAGS             TSEC_GIGABIT
 224 #define TSEC2_FLAGS             TSEC_GIGABIT
 225 #define CONFIG_ETHPRIME         "TSEC0"
 226
 227 #elif defined(CONFIG_ETHER_ON_FCC)      /* CPM FCC Ethernet */
 228
 229 #define CONFIG_ETHER_ON_FCC2             /* define if ether on FCC   */
 230 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 231 #define CONFIG_ETHER_INDEX      2       /* which channel for ether  */
 232
 233 #if (CONFIG_ETHER_INDEX == 2)
 234   /*
 235    * - Rx-CLK is CLK13
 236    * - Tx-CLK is CLK14
 237    * - Select bus for bd/buffers
 238    * - Full duplex
 239    */
 240   #define CONFIG_SYS_CMXFCR_MASK2      (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 241   #define CONFIG_SYS_CMXFCR_VALUE2     (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 242   #define CONFIG_SYS_CPMFCR_RAMTYPE    0
 243 #if 0
 244   #define CONFIG_SYS_FCC_PSMR          (FCC_PSMR_FDE)
 245 #else
 246   #define CONFIG_SYS_FCC_PSMR          0
 247 #endif
 248   #define FETH2_RST             0x01
 249 #elif (CONFIG_ETHER_INDEX == 3)
 250   /* need more definitions here for FE3 */
 251   #define FETH3_RST             0x80
 252 #endif  /* CONFIG_ETHER_INDEX */
 253
 254 /* MDIO is done through the TSEC0 control.
 255 */
 256 #define CONFIG_MII                      /* MII PHY management */
 257 #undef CONFIG_BITBANGMII                /* bit-bang MII PHY management  */
 258
 259 #endif
 260
 261 /* Environment */
 262 /* We use the top boot sector flash, so we have some 16K sectors for env
 263  */
 264 #ifndef CONFIG_SYS_RAMBOOT
 265   #define CONFIG_ENV_IS_IN_FLASH        1
 266   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE + 0x60000)
 267   #define CONFIG_ENV_SECT_SIZE  0x4000  /* 16K (one top sector) for env */
 268   #define CONFIG_ENV_SIZE               0x2000
 269 #else
 270   #define CONFIG_SYS_NO_FLASH           1       /* Flash is not usable now      */
 271   #define CONFIG_ENV_IS_NOWHERE 1       /* Store ENV in memory only     */
 272   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 273   #define CONFIG_ENV_SIZE               0x2000
 274 #endif
 275
 276 #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400"
 277 #define CONFIG_BOOTCOMMAND      "bootm 0xff000000 0xff100000"
 278 #define CONFIG_BOOTDELAY        3       /* -1 disable autoboot */
 279
 280 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 281 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 282
 283 /*
 284  * BOOTP options
 285  */
 286 #define CONFIG_BOOTP_BOOTFILESIZE
 287 #define CONFIG_BOOTP_BOOTPATH
 288 #define CONFIG_BOOTP_GATEWAY
 289 #define CONFIG_BOOTP_HOSTNAME
 290
 291
 292 /*
 293  * Command line configuration.
 294  */
 295 #include <config_cmd_default.h>
 296
 297 #define CONFIG_CMD_PING
 298 #define CONFIG_CMD_I2C
 299 #define CONFIG_CMD_REGINFO
 300
 301 #if defined(CONFIG_SYS_RAMBOOT)
 302     #undef CONFIG_CMD_SAVEENV
 303     #undef CONFIG_CMD_LOADS
 304 #else
 305     #define CONFIG_CMD_ELF
 306 #endif
 307
 308 #if defined(CONFIG_PCI)
 309     #define CONFIG_CMD_PCI
 310 #endif
 311
 312 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 313     #define CONFIG_CMD_MII
 314 #endif
 315
 316
 317 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 318
 319 /*
 320  * Miscellaneous configurable options
 321  */
 322 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 323 #define CONFIG_SYS_PROMPT       "GPPP=> "       /* Monitor Command Prompt       */
 324 #if defined(CONFIG_CMD_KGDB)
 325 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 326 #else
 327 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 328 #endif
 329 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 330 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 331 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 332 #define CONFIG_SYS_LOAD_ADDR    0x1000000       /* default load address */
 333
 334 /*
 335  * For booting Linux, the board info and command line data
 336  * have to be in the first 8 MB of memory, since this is
 337  * the maximum mapped by the Linux kernel during initialization.
 338  */
 339 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 340
 341 #if defined(CONFIG_CMD_KGDB)
 342 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 343 #endif
 344
 345 /*Note: change below for your network setting!!! */
 346 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 347 #define CONFIG_HAS_ETH0
 348 #define CONFIG_ETHADDR           00:e0:0c:07:9b:8a
 349 #define CONFIG_HAS_ETH1
 350 #define CONFIG_ETH1ADDR          00:e0:0c:07:9b:8b
 351 #define CONFIG_HAS_ETH2
 352 #define CONFIG_ETH2ADDR          00:e0:0c:07:9b:8c
 353 #endif
 354
 355 #define CONFIG_SERVERIP         192.168.85.1
 356 #define CONFIG_IPADDR           192.168.85.60
 357 #define CONFIG_GATEWAYIP        192.168.85.1
 358 #define CONFIG_NETMASK          255.255.255.0
 359 #define CONFIG_HOSTNAME         STX_GP3
 360 #define CONFIG_ROOTPATH         "/gppproot"
 361 #define CONFIG_BOOTFILE         "uImage"
 362 #define CONFIG_LOADADDR         0x1000000
 363
 364 #endif  /* __CONFIG_H */