include/configs/stxssa.h

   1 /*
   2  * (C) Copyright 2005 Embedded Alley Solutions, Inc.
   3  * Dan Malek <dan@embeddedalley.com>
   4  * Copied from STx GP3.
   5  * Updates for Silicon Tx GP3 SSA board.
   6  *
   7  * (C) Copyright 2002,2003 Motorola,Inc.
   8  * Xianghua Xiao <X.Xiao@motorola.com>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 /* mpc8560ads board configuration file */
  30 /* please refer to doc/README.mpc85xx for more info */
  31 /* make sure you change the MAC address and other network params first,
  32  * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
  33  */
  34
  35 #ifndef __CONFIG_H
  36 #define __CONFIG_H
  37
  38 /* High Level Configuration Options */
  39 #define CONFIG_BOOKE            1       /* BOOKE                */
  40 #define CONFIG_E500             1       /* BOOKE e500 family    */
  41 #define CONFIG_MPC85xx          1       /* MPC8540/MPC8560      */
  42 #define CONFIG_CPM2             1       /* has CPM2 */
  43 #define CONFIG_STXSSA           1       /* Silicon Tx GPPP SSA board specific*/
  44 #define CONFIG_MPC8560          1
  45
  46 #define CONFIG_PCI                      /* PCI ethernet support */
  47 #define CONFIG_TSEC_ENET                /* tsec ethernet support*/
  48 #undef CONFIG_ETHER_ON_FCC              /* cpm FCC ethernet support */
  49 #define CONFIG_ENV_OVERWRITE
  50 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  51 #undef  CONFIG_DDR_ECC                  /* only for ECC DDR module */
  52 #undef CONFIG_DDR_DLL                   /* possible DLL fix needed */
  53 #define CONFIG_DDR_2T_TIMING            /* Sets the 2T timing bit */
  54
  55 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  56
  57 /* sysclk for MPC85xx
  58  */
  59
  60 #define CONFIG_SYS_CLK_FREQ     33000000 /* most pci cards are 33Mhz */
  61
  62 /* Blinkin' LEDs for Robert :-)
  63 */
  64 #define CONFIG_SHOW_ACTIVITY 1
  65
  66 /*
  67  * These can be toggled for performance analysis, otherwise use default.
  68  */
  69 #define CONFIG_L2_CACHE                         /* toggle L2 cache             */
  70 #define  CONFIG_BTB                             /* toggle branch predition */
  71 #define  CONFIG_ADDR_STREAMING                  /* toggle addr streaming        */
  72
  73 #define CONFIG_BOARD_EARLY_INIT_F   1           /* Call board_pre_init   */
  74
  75 #undef  CFG_DRAM_TEST                           /* memory test, takes time      */
  76 #define CFG_MEMTEST_START       0x00200000      /* memtest region */
  77 #define CFG_MEMTEST_END         0x00400000
  78
  79
  80 /* Localbus connector.  There are many options that can be
  81  * connected here, including sdram or lots of flash.
  82  * This address, however, is used to configure a 256M local bus
  83  * window that includes the Config latch below.
  84  */
  85 #define CFG_LBC_OPTION_BASE     0xF0000000      /* Localbus Extension */
  86 #define CFG_LBC_OPTION_SIZE     256             /* 256MB */
  87
  88 /* There are various flash options used, we configure for the largest,
  89  * which is 64Mbytes.  The CFI works fine and will discover the proper
  90  * sizes.
  91  */
  92 #ifdef CONFIG_STXSSA_4M
  93 #define CFG_FLASH_BASE          0xFFC00000      /* start of  4 MiB flash */
  94 #else
  95 #define CFG_FLASH_BASE          0xFC000000      /* start of 64 MiB flash */
  96 #endif
  97 #define CFG_BR0_PRELIM  (CFG_FLASH_BASE | 0x1801) /* port size 32bit     */
  98 #define CFG_OR0_PRELIM  (CFG_FLASH_BASE | 0x0FF7)
  99
 100 #define CFG_FLASH_CFI           1
 101 #define CFG_FLASH_CFI_DRIVER    1
 102 #undef CFG_FLASH_USE_BUFFER_WRITE       /* use buffered writes (20x faster) */
 103 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip */
 104 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks   */
 105
 106 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
 107
 108 #define CFG_FLASH_PROTECTION
 109
 110 /* The configuration latch is Chip Select 1.
 111  * It's an 8-bit latch in the lower 8 bits of the word.
 112  */
 113 #define CFG_LBC_CFGLATCH_BASE   0xFB000000      /* Base of config latch */
 114 #define CFG_BR1_PRELIM          0xFB001801      /* 32-bit port */
 115 #define CFG_OR1_PRELIM          0xFFFF0FF7      /* 64K is enough */
 116
 117 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor     */
 118
 119 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 120 #define CFG_RAMBOOT
 121 #else
 122 #undef  CFG_RAMBOOT
 123 #endif
 124
 125 #ifdef CFG_RAMBOOT
 126 #define CFG_CCSRBAR_DEFAULT     0x40000000      /* CCSRBAR by BDI cfg   */
 127 #else
 128 #define CFG_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default      */
 129 #endif
 130 #define CFG_CCSRBAR             0xe0000000      /* relocated CCSRBAR    */
 131 #define CFG_CCSRBAR_PHYS        CFG_CCSRBAR     /* physical addr of CCSRBAR */
 132 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR   */
 133
 134
 135 /*
 136  * DDR Setup
 137  */
 138
 139 /*
 140  * Base addresses -- Note these are effective addresses where the
 141  * actual resources get mapped (not physical addresses)
 142  */
 143 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory  */
 144 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
 145
 146 #define SPD_EEPROM_ADDRESS      0x54            /*  DDR DIMM */
 147
 148 #undef CONFIG_CLOCKS_IN_MHZ
 149
 150 /* local bus definitions */
 151 #define CFG_BR2_PRELIM          0xf8001861      /* 64MB localbus SDRAM  */
 152 #define CFG_OR2_PRELIM          0xfc006901
 153 #define CFG_LBC_LCRR            0x00030004      /* local bus freq       */
 154 #define CFG_LBC_LBCR            0x00000000
 155 #define CFG_LBC_LSRT            0x20000000
 156 #define CFG_LBC_MRTPR           0x20000000
 157 #define CFG_LBC_LSDMR_1         0x2861b723
 158 #define CFG_LBC_LSDMR_2         0x0861b723
 159 #define CFG_LBC_LSDMR_3         0x0861b723
 160 #define CFG_LBC_LSDMR_4         0x1861b723
 161 #define CFG_LBC_LSDMR_5         0x4061b723
 162
 163 #define CONFIG_L1_INIT_RAM
 164 #define CFG_INIT_RAM_LOCK       1
 165 #define CFG_INIT_RAM_ADDR       0x60000000      /* Initial RAM address  */
 166 #define CFG_INIT_RAM_END        0x4000          /* End of used area in RAM */
 167
 168 #define CFG_GBL_DATA_SIZE       128             /* num bytes initial data */
 169 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 170 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 171
 172 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Mon */
 173 #define CFG_MALLOC_LEN          (512 * 1024)    /* Reserved for malloc */
 174
 175 /* Serial Port */
 176 #define CONFIG_CONS_INDEX     2
 177 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 178 #define CFG_NS16550
 179 #define CFG_NS16550_SERIAL
 180 #define CFG_NS16550_REG_SIZE    1
 181 #define CFG_NS16550_CLK         get_bus_freq(0)
 182
 183 #define CFG_BAUDRATE_TABLE  \
 184         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 185
 186 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 187 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 188
 189 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 190 #define CFG_HUSH_PARSER         1       /* Use the HUSH parser          */
 191 #ifdef  CFG_HUSH_PARSER
 192 #define CFG_PROMPT_HUSH_PS2 "> "
 193 #endif
 194
 195 /*
 196  * I2C
 197  */
 198 #define CONFIG_FSL_I2C                  /* Use FSL common I2C driver */
 199 #define  CONFIG_HARD_I2C                /* I2C with hardware support*/
 200 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 201 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 202 #define CFG_I2C_SLAVE           0x7F
 203 #undef CFG_I2C_NOPROBES
 204 #define CFG_I2C_OFFSET          0x3000
 205
 206 /* I2C RTC */
 207 #define CONFIG_RTC_DS1337               /* This is really a DS1339 RTC  */
 208 #define CFG_I2C_RTC_ADDR        0x68    /* at address 0x68              */
 209
 210 /* I2C EEPROM.  AT24C32, we keep our environment in here.
 211 */
 212 #define CFG_I2C_EEPROM_ADDR             0x51    /* 1010001x             */
 213 #define CFG_I2C_EEPROM_ADDR_LEN         2
 214 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* =32 Bytes per write  */
 215 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 216 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  20
 217
 218 /*
 219  * Standard 8555 PCI mapping.
 220  * Addresses are mapped 1-1.
 221  */
 222 #define CFG_PCI1_MEM_BASE       0x80000000
 223 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 224 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
 225 #define CFG_PCI1_IO_BASE        0x00000000
 226 #define CFG_PCI1_IO_PHYS        0xe2000000
 227 #define CFG_PCI1_IO_SIZE        0x01000000      /* 16M */
 228
 229 #define CFG_PCI2_MEM_BASE       0xa0000000
 230 #define CFG_PCI2_MEM_PHYS       CFG_PCI2_MEM_BASE
 231 #define CFG_PCI2_MEM_SIZE       0x20000000      /* 512M */
 232 #define CFG_PCI2_IO_BASE        0x00000000
 233 #define CFG_PCI2_IO_PHYS        0xe3000000
 234 #define CFG_PCI2_IO_SIZE        0x01000000      /* 16M */
 235
 236 #if defined(CONFIG_PCI)                 /* PCI Ethernet card */
 237 #define CONFIG_MPC85XX_PCI2     1
 238 #define CONFIG_NET_MULTI
 239 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 240
 241 #define CONFIG_EEPRO100
 242 #define CONFIG_TULIP
 243
 244 #if !defined(CONFIG_PCI_PNP)
 245   #define PCI_ENET0_IOADDR      0xe0000000
 246   #define PCI_ENET0_MEMADDR     0xe0000000
 247   #define PCI_IDSEL_NUMBER      0x0c    /* slot0->3(IDSEL)=12->15 */
 248 #endif
 249
 250 #define CONFIG_PCI_SCAN_SHOW
 251 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 252
 253 #endif /* CONFIG_PCI */
 254
 255 #if defined(CONFIG_TSEC_ENET)
 256
 257 #ifndef CONFIG_NET_MULTI
 258 #define CONFIG_NET_MULTI        1
 259 #endif
 260
 261 #define CONFIG_MII              1       /* MII PHY management           */
 262
 263 #define CONFIG_TSEC1    1
 264 #define CONFIG_TSEC1_NAME       "TSEC0"
 265 #define CONFIG_TSEC2    1
 266 #define CONFIG_TSEC2_NAME       "TSEC1"
 267
 268 #define TSEC1_PHY_ADDR          2
 269 #define TSEC2_PHY_ADDR          4
 270 #define TSEC1_PHYIDX            0
 271 #define TSEC2_PHYIDX            0
 272 #define TSEC1_FLAGS             TSEC_GIGABIT
 273 #define TSEC2_FLAGS             TSEC_GIGABIT
 274 #define CONFIG_ETHPRIME         "TSEC0"
 275
 276 #elif defined(CONFIG_ETHER_ON_FCC)      /* CPM FCC Ethernet */
 277
 278 #define CONFIG_ETHER_ON_FCC2            /* define if ether on FCC   */
 279 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 280 #define CONFIG_ETHER_INDEX      2       /* which channel for ether  */
 281
 282 #if (CONFIG_ETHER_INDEX == 2)
 283   /*
 284    * - Rx-CLK is CLK13
 285    * - Tx-CLK is CLK14
 286    * - Select bus for bd/buffers
 287    * - Full duplex
 288    */
 289   #define CFG_CMXFCR_MASK       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 290   #define CFG_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 291   #define CFG_CPMFCR_RAMTYPE    0
 292 #if 0
 293   #define CFG_FCC_PSMR          (FCC_PSMR_FDE)
 294 #else
 295   #define CFG_FCC_PSMR          0
 296 #endif
 297   #define FETH2_RST             0x01
 298 #elif (CONFIG_ETHER_INDEX == 3)
 299   /* need more definitions here for FE3 */
 300   #define FETH3_RST             0x80
 301 #endif                                  /* CONFIG_ETHER_INDEX */
 302
 303 /* MDIO is done through the TSEC0 control.
 304 */
 305 #define CONFIG_MII                      /* MII PHY management */
 306 #undef CONFIG_BITBANGMII                /* bit-bang MII PHY management  */
 307
 308 #endif
 309
 310 /* Environment - default config is in flash, see below */
 311 #if 0   /* in EEPROM */
 312 # define CFG_ENV_IS_IN_EEPROM   1
 313 # define CFG_ENV_OFFSET         0
 314 # define CFG_ENV_SIZE           2048
 315 #else   /* in flash */
 316 # define CFG_ENV_IS_IN_FLASH    1
 317 # ifdef CONFIG_STXSSA_4M
 318 #  define CFG_ENV_SECT_SIZE     0x20000
 319 # else  /* default configuration - 64 MiB flash */
 320 #  define CFG_ENV_SECT_SIZE     0x40000
 321 # endif
 322 # define CFG_ENV_ADDR           (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
 323 # define CFG_ENV_SIZE           0x4000
 324 # define CFG_ENV_ADDR_REDUND    (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
 325 # define CFG_ENV_SIZE_REDUND    (CFG_ENV_SIZE)
 326 #endif
 327
 328 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 329 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 330
 331 #define CONFIG_TIMESTAMP                /* Print image info with ts     */
 332
 333
 334 /*
 335  * BOOTP options
 336  */
 337 #define CONFIG_BOOTP_BOOTFILESIZE
 338 #define CONFIG_BOOTP_BOOTPATH
 339 #define CONFIG_BOOTP_GATEWAY
 340 #define CONFIG_BOOTP_HOSTNAME
 341
 342
 343 /*
 344  * Command line configuration.
 345  */
 346 #include <config_cmd_default.h>
 347
 348 #define CONFIG_CMD_DATE
 349 #define CONFIG_CMD_DHCP
 350 #define CONFIG_CMD_EEPROM
 351 #define CONFIG_CMD_I2C
 352 #define CONFIG_CMD_NFS
 353 #define CONFIG_CMD_PING
 354 #define CONFIG_CMD_SNTP
 355
 356 #if defined(CONFIG_PCI)
 357     #define CONFIG_CMD_PCI
 358 #endif
 359
 360 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 361     #define CONFIG_CMD_MII
 362 #endif
 363
 364 #if defined(CFG_RAMBOOT)
 365     #undef CONFIG_CMD_ENV
 366     #undef CONFIG_CMD_LOADS
 367 #else
 368     #define CONFIG_CMD_ELF
 369 #endif
 370
 371
 372 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 373
 374 /*
 375  * Miscellaneous configurable options
 376  */
 377 #define CFG_LONGHELP                    /* undef to save memory         */
 378 #define CFG_PROMPT      "SSA=> "        /* Monitor Command Prompt       */
 379 #if defined(CONFIG_CMD_KGDB)
 380 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 381 #else
 382 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 383 #endif
 384 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 385 #define CFG_MAXARGS     16              /* max number of command args   */
 386 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 387 #define CFG_LOAD_ADDR   0x1000000       /* default load address */
 388 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 389
 390 /*
 391  * For booting Linux, the board info and command line data
 392  * have to be in the first 8 MB of memory, since this is
 393  * the maximum mapped by the Linux kernel during initialization.
 394  */
 395 #define CFG_BOOTMAPSZ           (8 << 20) /* Initial Memory map for Linux */
 396
 397 /*
 398  * Internal Definitions
 399  *
 400  * Boot Flags
 401  */
 402 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 403 #define BOOTFLAG_WARM   0x02            /* Software reboot              */
 404
 405 #if defined(CONFIG_CMD_KGDB)
 406 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 407 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 408 #endif
 409
 410 /*Note: change below for your network setting!!! */
 411 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 412 #define CONFIG_HAS_ETH0
 413 #define CONFIG_ETHADDR   00:e0:0c:07:9b:8a
 414 #define CONFIG_HAS_ETH1
 415 #define CONFIG_ETH1ADDR  00:e0:0c:07:9b:8b
 416 #define CONFIG_HAS_ETH2
 417 #define CONFIG_ETH2ADDR  00:e0:0c:07:9b:8c
 418 #endif
 419
 420 /*
 421  * Environment in EEPROM is compatible with different flash sector sizes,
 422  * but only little space is available, so we use a very simple setup.
 423  * With environment in flash, we use a more powerful default configuration.
 424  */
 425 #ifdef CFG_ENV_IS_IN_EEPROM             /* use restricted "standard" environment */
 426
 427 #define CONFIG_BAUDRATE         38400
 428
 429 #define CONFIG_BOOTDELAY        3       /* -1 disable autoboot */
 430 #define CONFIG_BOOTCOMMAND      "bootm 0xffc00000 0xffd00000"
 431 #define CONFIG_BOOTARGS         "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
 432 #define CONFIG_SERVERIP         192.168.85.1
 433 #define CONFIG_IPADDR           192.168.85.60
 434 #define CONFIG_GATEWAYIP        192.168.85.1
 435 #define CONFIG_NETMASK          255.255.255.0
 436 #define CONFIG_HOSTNAME         STX_SSA
 437 #define CONFIG_ROOTPATH         /gppproot
 438 #define CONFIG_BOOTFILE         uImage
 439 #define CONFIG_LOADADDR         0x1000000
 440
 441 #else /* ENV IS IN FLASH                -- use a full-blown envionment */
 442
 443 #define CONFIG_BAUDRATE         115200
 444
 445 #define CONFIG_BOOTDELAY        5       /* -1 disable autoboot */
 446
 447 #define CONFIG_PREBOOT  "echo;" \
 448         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 449         "echo"
 450
 451 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs   */
 452
 453 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 454         "hostname=gp3ssa\0"                                             \
 455         "bootfile=/tftpboot/gp3ssa/uImage\0"                            \
 456         "loadaddr=400000\0"                                             \
 457         "netdev=eth0\0"                                                 \
 458         "consdev=ttyS1\0"                                               \
 459         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 460                 "nfsroot=$serverip:$rootpath\0"                         \
 461         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 462         "addip=setenv bootargs $bootargs "                              \
 463                 "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
 464                 ":$hostname:$netdev:off panic=1\0"                      \
 465         "addcons=setenv bootargs $bootargs "                            \
 466                 "console=$consdev,$baudrate\0"                          \
 467         "flash_nfs=run nfsargs addip addcons;"                          \
 468                 "bootm $kernel_addr\0"                                  \
 469         "flash_self=run ramargs addip addcons;"                         \
 470                 "bootm $kernel_addr $ramdisk_addr\0"                    \
 471         "net_nfs=tftp $loadaddr $bootfile;"                             \
 472                 "run nfsargs addip addcons;bootm\0"                     \
 473         "rootpath=/opt/eldk/ppc_85xx\0"                                 \
 474         "kernel_addr=FC000000\0"                                        \
 475         "ramdisk_addr=FC200000\0"                                       \
 476         ""
 477 #define CONFIG_BOOTCOMMAND      "run flash_self"
 478
 479 #endif  /* CFG_ENV_IS_IN_EEPROM */
 480
 481 #endif  /* __CONFIG_H */