include/configs/stxxtc.h

   1 /*
   2  * (C) Copyright 2000-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
  26  * U-Boot port on STx XTc 8xx board
  27  * Mostly copied from Panto's NETTA2 board.
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37
  38 #define CONFIG_MPC875           1       /* This is a MPC875 CPU         */
  39 #define CONFIG_STXXTC           1       /* ...on a STx XTc  board       */
  40
  41 #define CONFIG_SYS_TEXT_BASE    0x40F00000
  42
  43 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  44 #undef  CONFIG_8xx_CONS_SMC2
  45 #undef  CONFIG_8xx_CONS_NONE
  46
  47 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115.2kbps */
  48
  49 #define CONFIG_XIN              10000000        /* 10 MHz input xtal */
  50
  51 /* Select one of few clock rates defined later in this file.
  52 */
  53 /* #define MPC8XX_HZ            50000000 */
  54 #define MPC8XX_HZ               66666666
  55
  56 #define CONFIG_8xx_GCLK_FREQ    MPC8XX_HZ
  57
  58 #if 0
  59 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  60 #else
  61 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  62 #endif
  63
  64 #undef  CONFIG_CLOCKS_IN_MHZ    /* clocks NOT passsed to Linux in MHz */
  65
  66 #undef  CONFIG_BOOTARGS
  67 #define CONFIG_BOOTCOMMAND                                                      \
  68         "tftpboot; "                                                            \
  69         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  70         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
  71         "bootm"
  72
  73 #define CONFIG_SOURCE
  74 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
  75 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  76
  77 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  78
  79 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  80 #define CONFIG_BOARD_SPECIFIC_LED       /* version has board specific leds */
  81
  82 /*
  83  * BOOTP options
  84  */
  85 #define CONFIG_BOOTP_SUBNETMASK
  86 #define CONFIG_BOOTP_GATEWAY
  87 #define CONFIG_BOOTP_HOSTNAME
  88 #define CONFIG_BOOTP_BOOTPATH
  89 #define CONFIG_BOOTP_BOOTFILESIZE
  90 #define CONFIG_BOOTP_NISDOMAIN
  91
  92
  93 #undef CONFIG_MAC_PARTITION
  94 #undef CONFIG_DOS_PARTITION
  95
  96 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  97
  98 #define FEC_ENET                1       /* eth.c needs it that way... */
  99 #undef CONFIG_SYS_DISCOVER_PHY
 100 #define CONFIG_MII              1
 101 #define CONFIG_MII_INIT         1
 102 #undef CONFIG_RMII
 103
 104 #define CONFIG_ETHER_ON_FEC1    1
 105 #define CONFIG_FEC1_PHY         1       /* phy address of FEC */
 106 #undef CONFIG_FEC1_PHY_NORXERR
 107
 108 #define CONFIG_ETHER_ON_FEC2    1
 109 #define CONFIG_FEC2_PHY         3
 110 #undef CONFIG_FEC2_PHY_NORXERR
 111
 112 #define CONFIG_ENV_OVERWRITE    1       /* allow modification of vendor params */
 113
 114
 115 /*
 116  * Command line configuration.
 117  */
 118 #include <config_cmd_default.h>
 119
 120 #define CONFIG_CMD_DHCP
 121 #define CONFIG_CMD_MII
 122 #define CONFIG_CMD_NFS
 123 #define CONFIG_CMD_PING
 124
 125
 126 #define CONFIG_BOARD_EARLY_INIT_F       1
 127 #define CONFIG_MISC_INIT_R
 128
 129 /*
 130  * Miscellaneous configurable options
 131  */
 132 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 133 #define CONFIG_SYS_PROMPT       "xtc> "         /* Monitor Command Prompt       */
 134
 135 #define CONFIG_SYS_HUSH_PARSER  1
 136 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 137
 138 #if defined(CONFIG_CMD_KGDB)
 139 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 140 #else
 141 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 142 #endif
 143 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 144 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 145 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 146
 147 #define CONFIG_SYS_MEMTEST_START        0x0300000       /* memtest works on     */
 148 #define CONFIG_SYS_MEMTEST_END          0x0700000       /* 3 ... 7 MB in DRAM   */
 149
 150 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 151
 152 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 153
 154 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 155
 156 /*
 157  * Low Level Configuration Settings
 158  * (address mappings, register initial values, etc.)
 159  * You should know what you are doing if you make changes here.
 160  */
 161 /*-----------------------------------------------------------------------
 162  * Internal Memory Mapped Register
 163  */
 164 #define CONFIG_SYS_IMMR         0xFF000000
 165
 166 /*-----------------------------------------------------------------------
 167  * Definitions for initial stack pointer and data area (in DPRAM)
 168  */
 169 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 170 #define CONFIG_SYS_INIT_RAM_SIZE        0x3000  /* Size of used area in DPRAM   */
 171 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 172 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 173
 174 /*-----------------------------------------------------------------------
 175  * Start addresses for the final memory configuration
 176  * (Set up by the startup code)
 177  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 178  */
 179 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 180 #define CONFIG_SYS_FLASH_BASE           0x40000000
 181 #if defined(DEBUG)
 182 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 183 #else
 184 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 185 #endif
 186
 187 /* yes this is weird, I know :) */
 188 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE | 0x00F00000)
 189 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 190
 191 #define CONFIG_SYS_RESET_ADDRESS        0x80000000
 192
 193 /*
 194  * For booting Linux, the board info and command line data
 195  * have to be in the first 8 MB of memory, since this is
 196  * the maximum mapped by the Linux kernel during initialization.
 197  */
 198 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 199
 200 /*-----------------------------------------------------------------------
 201  * FLASH organization
 202  */
 203 #define CONFIG_ENV_IS_IN_FLASH  1
 204 #define CONFIG_ENV_SECT_SIZE    0x10000
 205
 206 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00000000)
 207 #define CONFIG_ENV_OFFSET               0
 208 #define CONFIG_ENV_SIZE         0x4000
 209
 210 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_SYS_FLASH_BASE + 0x00010000)
 211 #define CONFIG_ENV_OFFSET_REDUND        0
 212 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 213
 214 #define CONFIG_SYS_FLASH_CFI            1
 215 #define CONFIG_FLASH_CFI_DRIVER 1
 216 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE        /* use buffered writes (20x faster) */
 217 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max number of sectors on one chip */
 218 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks   */
 219
 220 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x2000000 }
 221
 222 #define CONFIG_SYS_FLASH_PROTECTION
 223
 224 /*-----------------------------------------------------------------------
 225  * Cache Configuration
 226  */
 227 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs */
 228 #if defined(CONFIG_CMD_KGDB)
 229 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value */
 230 #endif
 231
 232 /*-----------------------------------------------------------------------
 233  * SYPCR - System Protection Control                            11-9
 234  * SYPCR can only be written once after reset!
 235  *-----------------------------------------------------------------------
 236  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 237  */
 238 #if defined(CONFIG_WATCHDOG)
 239 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 240                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 241 #else
 242 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 243 #endif
 244
 245 /*-----------------------------------------------------------------------
 246  * SIUMCR - SIU Module Configuration                            11-6
 247  *-----------------------------------------------------------------------
 248  * PCMCIA config., multi-function pin tri-state
 249  */
 250 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E)
 251
 252 /*-----------------------------------------------------------------------
 253  * TBSCR - Time Base Status and Control                         11-26
 254  *-----------------------------------------------------------------------
 255  * Clear Reference Interrupt Status, Timebase freezing enabled
 256  */
 257 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 258
 259 /*-----------------------------------------------------------------------
 260  * RTCSC - Real-Time Clock Status and Control Register          11-27
 261  *-----------------------------------------------------------------------
 262  */
 263 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 264
 265 /*-----------------------------------------------------------------------
 266  * PISCR - Periodic Interrupt Status and Control                11-31
 267  *-----------------------------------------------------------------------
 268  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 269  */
 270 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 271
 272 /*-----------------------------------------------------------------------
 273  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 274  *-----------------------------------------------------------------------
 275  * Reset PLL lock status sticky bit, timer expired status bit and timer
 276  * interrupt status bit
 277  *
 278  */
 279
 280 #if CONFIG_XIN == 10000000
 281
 282 #if MPC8XX_HZ == 50000000
 283 #define CONFIG_SYS_PLPRCR       ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 284                          (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 285                          PLPRCR_TEXPS)
 286 #elif MPC8XX_HZ == 66666666
 287 #define CONFIG_SYS_PLPRCR       ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
 288                          (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 289                          PLPRCR_TEXPS)
 290 #else
 291 #error unsupported CPU freq for XIN = 10MHz
 292 #endif
 293 #else
 294 #error unsupported freq for XIN (must be 10MHz)
 295 #endif
 296
 297
 298 /*
 299  *-----------------------------------------------------------------------
 300  * SCCR - System Clock and reset Control Register               15-27
 301  *-----------------------------------------------------------------------
 302  * Set clock output, timebase and RTC source and divider,
 303  * power management and some other internal clocks
 304  *
 305  * Note: When TBS == 0 the timebase is independent of current cpu clock.
 306  */
 307
 308 #define SCCR_MASK       SCCR_EBDF11
 309 #if MPC8XX_HZ > 66666666
 310 #define CONFIG_SYS_SCCR (/* SCCR_TBS     | */ SCCR_CRQEN | \
 311                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 312                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 313                          SCCR_DFALCD00 | SCCR_EBDF01)
 314 #else
 315 #define CONFIG_SYS_SCCR (/* SCCR_TBS     | */ SCCR_CRQEN | \
 316                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 317                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 318                          SCCR_DFALCD00)
 319 #endif
 320
 321 /*-----------------------------------------------------------------------
 322  *
 323  *-----------------------------------------------------------------------
 324  *
 325  */
 326 /*#define       CONFIG_SYS_DER  0x2002000F*/
 327 #define CONFIG_SYS_DER  0
 328
 329 /*
 330  * Init Memory Controller:
 331  *
 332  * BR0/1 and OR0/1 (FLASH)
 333  */
 334
 335 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 336 #define FLASH_BASE1_PRELIM      0x42000000      /* FLASH bank #1        */
 337
 338 /* used to re-map FLASH both when starting from SRAM or FLASH:
 339  * restrict access enough to keep SRAM working (if any)
 340  * but not too much to meddle with FLASH accesses
 341  */
 342
 343 #define FLASH_BANK_MAX_SIZE     0x01000000      /* max size per chip */
 344
 345 #define CONFIG_SYS_REMAP_OR_AM          0x80000000
 346 #define CONFIG_SYS_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1))
 347
 348 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1        */
 349 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
 350
 351 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 352 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 353 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 354
 355 #define CONFIG_SYS_OR1_PRELIM   ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_FLASH)
 356 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 357
 358 /*
 359  * BR4 and OR4 (SDRAM)
 360  *
 361  */
 362 #define SDRAM_BASE1_PRELIM      0x00000000      /* SDRAM bank #0        */
 363 #define SDRAM_MAX_SIZE          (256 << 20)     /* max 256MB per bank   */
 364
 365 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 366 #define CONFIG_SYS_OR_TIMING_SDRAM      (OR_CSNT_SAM | OR_G5LS)
 367
 368 #define CONFIG_SYS_OR4_PRELIM   ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
 369 #define CONFIG_SYS_BR4_PRELIM   ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
 370
 371 /*
 372  * Memory Periodic Timer Prescaler
 373  */
 374
 375 /*
 376  * Memory Periodic Timer Prescaler
 377  *
 378  * The Divider for PTA (refresh timer) configuration is based on an
 379  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 380  * the number of chip selects (NCS) and the actually needed refresh
 381  * rate is done by setting MPTPR.
 382  *
 383  * PTA is calculated from
 384  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 385  *
 386  *      gclk      CPU clock (not bus clock!)
 387  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 388  *
 389  * 4096  Rows from SDRAM example configuration
 390  * 1000  factor s -> ms
 391  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 392  *    4  Number of refresh cycles per period
 393  *   64  Refresh cycle in ms per number of rows
 394  * --------------------------------------------
 395  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 396  *
 397  * 50 MHz => 50.000.000 / Divider =  98
 398  * 66 Mhz => 66.000.000 / Divider = 129
 399  * 80 Mhz => 80.000.000 / Divider = 156
 400  */
 401
 402 #define CONFIG_SYS_MAMR_PTA              234
 403
 404 /*
 405  * For 16 MBit, refresh rates could be 31.3 us
 406  * (= 64 ms / 2K = 125 / quad bursts).
 407  * For a simpler initialization, 15.6 us is used instead.
 408  *
 409  * #define CONFIG_SYS_MPTPR_2BK_2K      MPTPR_PTP_DIV32         for 2 banks
 410  * #define CONFIG_SYS_MPTPR_1BK_2K      MPTPR_PTP_DIV64         for 1 bank
 411  */
 412 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 413 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 414
 415 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 416 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 417 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 418
 419 /*
 420  * MAMR settings for SDRAM
 421  */
 422
 423 /* 8 column SDRAM */
 424 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 425                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 426                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 427
 428 /* 9 column SDRAM */
 429 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 430                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 431                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 432
 433 #define CONFIG_LAST_STAGE_INIT          /* needed to reset the damn phys */
 434
 435 /****************************************************************/
 436
 437 #define NAND_SIZE       0x00010000      /* 64K */
 438 #define NAND_BASE       0xF1000000
 439
 440 /*****************************************************************************/
 441
 442 #define CONFIG_SYS_DIRECT_FLASH_TFTP
 443
 444 /*****************************************************************************/
 445
 446 /* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB,
 447  * CxOE and CxRESET.  We use the CxOE.
 448  */
 449 #define STATUS_LED_BIT          0x00000080              /* bit 24 */
 450
 451 #define STATUS_LED_PERIOD       (CONFIG_SYS_HZ / 2)
 452 #define STATUS_LED_STATE        STATUS_LED_BLINKING
 453
 454 #define STATUS_LED_ACTIVE       0               /* LED on for bit == 0  */
 455 #define STATUS_LED_BOOT         0               /* LED 0 used for boot status */
 456
 457 #ifndef __ASSEMBLY__
 458
 459 /* LEDs */
 460
 461 /* led_id_t is unsigned int mask */
 462 typedef unsigned int led_id_t;
 463
 464 #define __led_toggle(_msk) \
 465         do { \
 466                 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \
 467         } while(0)
 468
 469 #define __led_set(_msk, _st) \
 470         do { \
 471                 if ((_st)) \
 472                         ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \
 473                 else \
 474                         ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \
 475         } while(0)
 476
 477 #define __led_init(msk, st) __led_set(msk, st)
 478
 479 #endif
 480
 481 /******************************************************************************/
 482
 483 #define CONFIG_SYS_CONSOLE_IS_IN_ENV            1
 484 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE    1
 485 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE        1
 486
 487 /******************************************************************************/
 488
 489 /* use board specific hardware */
 490 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 491 #define CONFIG_HW_WATCHDOG
 492
 493 /*****************************************************************************/
 494
 495 #define CONFIG_AUTO_COMPLETE    1
 496 #define CONFIG_CRC32_VERIFY     1
 497 #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE       1
 498
 499 /*****************************************************************************/
 500
 501 /* pass open firmware flattened device tree */
 502 #define CONFIG_OF_LIBFDT        1
 503
 504 #define OF_TBCLK                (MPC8XX_HZ / 16)
 505
 506 #endif  /* __CONFIG_H */