include/configs/svm_sc8xx.h

   1 /*
   2  * (C) Copyright 2000, 2001, 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific,
  26  *                  for SinoVee Microsystems SC8xx series SBC
  27  *                  http://www.fel.com.cn (Chinese)
  28  *                  http://www.sinovee.com (English)
  29  */
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 #define CONFIG_SYS_TEXT_BASE    0x40000000
  35
  36 /* Custom configuration */
  37 /* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */
  38 /* SC85T,SC860T, FEL8xx-AT(855T/860T) */
  39 /*#define CONFIG_FEL8xx_AT */
  40 /*#define CONFIG_LCD */
  41 /* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */
  42 /* #define CONFIG_50MHz */
  43 /* #define CONFIG_66MHz */
  44 /* #define CONFIG_75MHz */
  45 #define CONFIG_80MHz
  46 /*#define CONFIG_100MHz */
  47 /* #define CONFIG_BUS_DIV2      1 */
  48 /* for BOOT device port size */
  49 /* #define CONFIG_BOOT_8B */
  50 #define CONFIG_BOOT_16B
  51 /* #define CONFIG_BOOT_32B */
  52 /* #define CONFIG_CAN_DRIVER */
  53 /* #define DEBUG */
  54 #define CONFIG_FEC_ENET
  55
  56 /* #define CONFIG_SDRAM_16M */
  57 #define CONFIG_SDRAM_32M
  58 /* #define CONFIG_SDRAM_64M */
  59 #define CONFIG_SYS_RESET_ADDRESS 0xffffffff
  60 /*
  61  * High Level Configuration Options
  62  * (easy to change)
  63  */
  64
  65 /* #define CONFIG_MPC823                1 */
  66 /* #define CONFIG_MPC850                1 */
  67 #define CONFIG_MPC855           1
  68 /* #define CONFIG_MPC860                1 */
  69 /* #define CONFIG_MPC860T               1 */
  70
  71 #undef  CONFIG_WATCHDOG                 /* watchdog */
  72
  73 #define CONFIG_SVM_SC8xx                1       /* ...on SVM SC8xx series       */
  74
  75 #ifdef  CONFIG_LCD                      /* with LCD controller ?        */
  76 /* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display       */
  77 #endif
  78
  79 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  80 #undef  CONFIG_8xx_CONS_SMC2
  81 #undef  CONFIG_8xx_CONS_NONE
  82 #define CONFIG_BAUDRATE         19200   /* console baudrate = 115kbps   */
  83 #if 0
  84 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  85 #else
  86 #define CONFIG_BOOTDELAY        1       /* autoboot after 5 seconds     */
  87 #endif
  88
  89 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  90
  91 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  92
  93 #define CONFIG_PREBOOT  "echo;echo Welcome to U-Boot SVM port;echo;echo Type \"? or help\" to get on-line help;echo"
  94
  95 #undef  CONFIG_BOOTARGS
  96 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  97         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  98          "nfsroot=${serverip}:${rootpath}\0"                     \
  99         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 100         "addip=setenv bootargs ${bootargs} "                            \
 101                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 102                 ":${hostname}:${netdev}:off panic=1\0"                  \
 103                 "flash_nfs=run nfsargs addip;"                                  \
 104              "bootm ${kernel_addr}\0"                                \
 105         "flash_self=run ramargs addip;"                                 \
 106                "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 107         "net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0"     \
 108         "rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0"                                  \
 109         "bootfile=pImage-sc855t\0"                           \
 110         "kernel_addr=48000000\0"                                        \
 111         "ramdisk_addr=48100000\0"                                       \
 112         ""
 113 #define CONFIG_BOOTCOMMAND                                                      \
 114         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
 115         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
 116         "tftpboot 0x210000 pImage-sc855t;bootm 0x210000"
 117
 118 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 119 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 120
 121
 122 #ifdef CONFIG_LCD
 123 # undef  CONFIG_STATUS_LED              /* disturbs display             */
 124 #else
 125 # define CONFIG_STATUS_LED      1       /* Status LED enabled           */
 126 #endif  /* CONFIG_LCD */
 127
 128 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
 129
 130 /*
 131  * BOOTP options
 132  */
 133 #define CONFIG_BOOTP_SUBNETMASK
 134 #define CONFIG_BOOTP_GATEWAY
 135 #define CONFIG_BOOTP_HOSTNAME
 136 #define CONFIG_BOOTP_BOOTPATH
 137 #define CONFIG_BOOTP_BOOTFILESIZE
 138
 139 #define CONFIG_MAC_PARTITION
 140 #define CONFIG_DOS_PARTITION
 141
 142 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
 143
 144
 145 /*
 146  * Command line configuration.
 147  */
 148 #include <config_cmd_default.h>
 149
 150 #define CONFIG_CMD_ASKENV
 151 #define CONFIG_CMD_DHCP
 152 #define CONFIG_CMD_DATE
 153
 154 /*
 155  * Miscellaneous configurable options
 156  */
 157 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 158 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 159
 160 #ifdef  CONFIG_SYS_HUSH_PARSER
 161 #endif
 162
 163 #if defined(CONFIG_CMD_KGDB)
 164 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 165 #else
 166 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 167 #endif
 168 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 169 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 170 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 171
 172 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 173 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 174
 175 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 176
 177 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 178
 179 /*
 180  * Low Level Configuration Settings
 181  * (address mappings, register initial values, etc.)
 182  * You should know what you are doing if you make changes here.
 183  */
 184 /*-----------------------------------------------------------------------
 185  * Internal Memory Mapped Register
 186  */
 187 #define CONFIG_SYS_IMMR         0xFF000000
 188
 189 /*-----------------------------------------------------------------------
 190  * Definitions for initial stack pointer and data area (in DPRAM)
 191  */
 192 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 193 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 194 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 195 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 196
 197 /*-----------------------------------------------------------------------
 198  * Start addresses for the final memory configuration
 199  * (Set up by the startup code)
 200  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 201  */
 202 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 203 #define CONFIG_SYS_FLASH_BASE           0x40000000
 204 #define CONFIG_SYS_MONITOR_LEN          (384 << 10)     /* Reserve 192 kB for Monitor   */
 205 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 206 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 207
 208 /*
 209  * For booting Linux, the board info and command line data
 210  * have to be in the first 8 MB of memory, since this is
 211  * the maximum mapped by the Linux kernel during initialization.
 212  */
 213 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 214
 215 /*-----------------------------------------------------------------------
 216  * FLASH organization
 217  */
 218 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 219 #define CONFIG_SYS_MAX_FLASH_SECT       67      /* max number of sectors on one chip    */
 220
 221 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 222 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 223
 224 #define CONFIG_ENV_IS_IN_FLASH  1
 225
 226 #ifdef CONFIG_BOOT_8B
 227 #define CONFIG_ENV_OFFSET               0x10000 /*   Offset   of Environment Sector     */
 228 #define CONFIG_ENV_SIZE         0x10000 /* Total Size of Environment Sector     */
 229 #elif defined (CONFIG_BOOT_16B)
 230 #define CONFIG_ENV_OFFSET               0x10000 /*   Offset   of Environment Sector     */
 231 #define CONFIG_ENV_SIZE         0x10000 /* Total Size of Environment Sector     */
 232 #elif defined (CONFIG_BOOT_32B)
 233 #define CONFIG_ENV_OFFSET               0x8000  /*   Offset   of Environment Sector     */
 234 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 235 #endif
 236
 237 /* Address and size of Redundant Environment Sector     */
 238 #define CONFIG_ENV_OFFSET_REDUND   (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
 239 #define CONFIG_ENV_SIZE_REDUND     (CONFIG_ENV_SIZE)
 240
 241
 242 /*-----------------------------------------------------------------------
 243  * Hardware Information Block
 244  */
 245 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 246 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 247 #define CONFIG_SYS_HWINFO_MAGIC 0x46454C38      /* 'SVM8' */
 248
 249 /*-----------------------------------------------------------------------
 250  * Cache Configuration
 251  */
 252 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 253 #if defined(CONFIG_CMD_KGDB)
 254 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 255 #endif
 256
 257 /*-----------------------------------------------------------------------
 258  * SYPCR - System Protection Control                            11-9
 259  * SYPCR can only be written once after reset!
 260  *-----------------------------------------------------------------------
 261  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 262  */
 263 #if defined(CONFIG_WATCHDOG)
 264 /*#define CONFIG_SYS_SYPCR      (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 265                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 266 */
 267 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \
 268                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 269 #else
 270 #define CONFIG_SYS_SYPCR 0xffffff88
 271 #endif
 272
 273 /*-----------------------------------------------------------------------
 274  * SIUMCR - SIU Module Configuration                            11-6
 275  *-----------------------------------------------------------------------
 276  * PCMCIA config., multi-function pin tri-state
 277  */
 278 #ifndef CONFIG_CAN_DRIVER
 279 /*#define CONFIG_SYS_SIUMCR 0x00610c00  */
 280 #define CONFIG_SYS_SIUMCR 0x00000000
 281 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 282 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 283 #endif  /* CONFIG_CAN_DRIVER */
 284
 285 /*-----------------------------------------------------------------------
 286  * TBSCR - Time Base Status and Control                         11-26
 287  *-----------------------------------------------------------------------
 288  * Clear Reference Interrupt Status, Timebase freezing enabled
 289  */
 290 #define CONFIG_SYS_TBSCR        0x0001
 291
 292 /*-----------------------------------------------------------------------
 293  * RTCSC - Real-Time Clock Status and Control Register          11-27
 294  *-----------------------------------------------------------------------
 295  */
 296 #define CONFIG_SYS_RTCSC        0x00c3
 297
 298 /*-----------------------------------------------------------------------
 299  * PISCR - Periodic Interrupt Status and Control                11-31
 300  *-----------------------------------------------------------------------
 301  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 302  */
 303 #define CONFIG_SYS_PISCR        0x0000
 304
 305 /*-----------------------------------------------------------------------
 306  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 307  *-----------------------------------------------------------------------
 308  * Reset PLL lock status sticky bit, timer expired status bit and timer
 309  * interrupt status bit
 310  */
 311 #if defined (CONFIG_100MHz)
 312 #define CONFIG_SYS_PLPRCR 0x06301000
 313 #define CONFIG_8xx_GCLK_FREQ 100000000
 314 #elif defined (CONFIG_80MHz)
 315 #define CONFIG_SYS_PLPRCR 0x04f01000
 316 #define CONFIG_8xx_GCLK_FREQ 80000000
 317 #elif defined(CONFIG_75MHz)
 318 #define CONFIG_SYS_PLPRCR 0x04a00100
 319 #define CONFIG_8xx_GCLK_FREQ 75000000
 320 #elif defined(CONFIG_66MHz)
 321 #define CONFIG_SYS_PLPRCR 0x04101000
 322 #define CONFIG_8xx_GCLK_FREQ 66000000
 323 #elif defined(CONFIG_50MHz)
 324 #define CONFIG_SYS_PLPRCR 0x03101000
 325 #define CONFIG_8xx_GCLK_FREQ 50000000
 326 #endif
 327
 328 /*-----------------------------------------------------------------------
 329  * SCCR - System Clock and reset Control Register               15-27
 330  *-----------------------------------------------------------------------
 331  * Set clock output, timebase and RTC source and divider,
 332  * power management and some other internal clocks
 333  */
 334 #define SCCR_MASK       SCCR_EBDF11
 335 #ifdef  CONFIG_BUS_DIV2
 336 #define CONFIG_SYS_SCCR 0x02020000 | SCCR_RTSEL
 337 #else                   /* up to 50 MHz we use a 1:1 clock */
 338 #define CONFIG_SYS_SCCR    0x02000000 | SCCR_RTSEL
 339 #endif
 340
 341 /*-----------------------------------------------------------------------
 342  * PCMCIA stuff
 343  *-----------------------------------------------------------------------
 344  *
 345  */
 346 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 347 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 348 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 349 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 350 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 351 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 352 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 353 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 354
 355 /*-----------------------------------------------------------------------
 356  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 357  *-----------------------------------------------------------------------
 358  */
 359
 360 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 361
 362 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 363 #define CONFIG_IDE_INIT_POSTRESET       1       /* Use postreset IDE hook */
 364 #define CONFIG_IDE_8xx_DIRECT   1       /* Direct IDE    not supported  */
 365 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 366 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 367
 368 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 369 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 370
 371 #define CONFIG_SYS_ATA_BASE_ADDR       0xFE100010
 372 #define CONFIG_SYS_ATA_IDE0_OFFSET     0x0000
 373 /*#define CONFIG_SYS_ATA_IDE1_OFFSET     0x0C00 */
 374 #define CONFIG_SYS_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O
 375                                            */
 376 #define CONFIG_SYS_ATA_REG_OFFSET      0x0200  /* Offset for normal register accesses
 377                                            */
 378 #define CONFIG_SYS_ATA_ALT_OFFSET      0x0210  /* Offset for alternate registers
 379                                            */
 380 #define CONFIG_ATAPI
 381 #define CONFIG_SYS_PIO_MODE 0
 382
 383 /*-----------------------------------------------------------------------
 384  *
 385  *-----------------------------------------------------------------------
 386  *
 387  */
 388 /*#define       CONFIG_SYS_DER  0x2002000F*/
 389 #define CONFIG_SYS_DER  0x0
 390
 391 /*
 392  * Init Memory Controller:
 393  *
 394  * BR0/1 and OR0/1 (FLASH)
 395  */
 396
 397 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 398 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 399
 400 /* used to re-map FLASH both when starting from SRAM or FLASH:
 401  * restrict access enough to keep SRAM working (if any)
 402  * but not too much to meddle with FLASH accesses
 403  */
 404 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 405 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 406
 407 /*
 408  * FLASH timing:
 409  */
 410 #if defined(CONFIG_100MHz)
 411 #define CONFIG_SYS_OR_TIMING_FLASH 0x000002f4
 412 #define CONFIG_SYS_OR_TIMING_DOC   0x000002f4
 413 #define CONFIG_SYS_MxMR_PTx 0x61000000
 414 #define CONFIG_SYS_MPTPR 0x400
 415
 416 #elif  defined(CONFIG_80MHz)
 417 #define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4
 418 #define CONFIG_SYS_OR_TIMING_DOC   0x000001f4
 419 #define CONFIG_SYS_MxMR_PTx 0x4e000000
 420 #define CONFIG_SYS_MPTPR 0x400
 421
 422 #elif defined(CONFIG_75MHz)
 423 #define CONFIG_SYS_OR_TIMING_FLASH 0x000008f4
 424 #define CONFIG_SYS_OR_TIMING_DOC   0x000002f4
 425 #define CONFIG_SYS_MxMR_PTx 0x49000000
 426 #define CONFIG_SYS_MPTPR 0x400
 427
 428 #elif defined(CONFIG_66MHz)
 429 #define CONFIG_SYS_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 430         OR_SCY_3_CLK | OR_EHTR | OR_BI)
 431 /*#define CONFIG_SYS_OR_TIMING_FLASH 0x000001f4 */
 432 #define CONFIG_SYS_OR_TIMING_DOC   0x000003f4
 433 #define CONFIG_SYS_MxMR_PTx  0x40000000
 434 #define CONFIG_SYS_MPTPR 0x400
 435
 436 #else           /*   50 MHz */
 437 #define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4
 438 #define CONFIG_SYS_OR_TIMING_DOC   0x000001f4
 439 #define CONFIG_SYS_MxMR_PTx  0x30000000
 440 #define CONFIG_SYS_MPTPR 0x400
 441 #endif  /*CONFIG_??MHz */
 442
 443
 444 #if  defined (CONFIG_BOOT_8B)   /* 512K X 8 ,29F040 , 2MB space */
 445 #define CONFIG_SYS_OR0_PRELIM   (0xffe00000 | CONFIG_SYS_OR_TIMING_FLASH)
 446 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8)
 447 #elif  defined (CONFIG_BOOT_16B)   /* 29lv160 X 16 , 4MB space */
 448 #define CONFIG_SYS_OR0_PRELIM   (0xffc00000 | CONFIG_SYS_OR_TIMING_FLASH)
 449 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
 450 #elif defined( CONFIG_BOOT_32B )  /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */
 451 #define CONFIG_SYS_OR0_PRELIM   (0xfc000000 | CONFIG_SYS_OR_TIMING_FLASH)
 452 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 453 #else
 454 #error Boot device port size missing.
 455 #endif
 456
 457 /*
 458  * Disk-On-Chip configuration
 459  */
 460
 461 #define CONFIG_SYS_DOC_SHORT_TIMEOUT
 462 #define CONFIG_SYS_MAX_DOC_DEVICE      1       /* Max number of DOC devices    */
 463
 464 #define CONFIG_SYS_DOC_SUPPORT_2000
 465 #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
 466 #define CONFIG_SYS_DOC_BASE 0x80000000
 467
 468 #endif  /* __CONFIG_H */