include/configs/taihu.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2005-2007
   6  * Beijing UD Technology Co., Ltd., taihusupport@amcc.com
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14
  15 #define CONFIG_405EP            1       /* this is a PPC405 CPU */
  16 #define CONFIG_TAIHU            1       /*  on a taihu board */
  17
  18 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  19
  20 /*
  21  * Include common defines/options for all AMCC eval boards
  22  */
  23 #define CONFIG_HOSTNAME         taihu
  24 #include "amcc-common.h"
  25
  26 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f */
  27
  28 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  29
  30 #define CONFIG_NO_SERIAL_EEPROM
  31
  32 /*----------------------------------------------------------------------------*/
  33 #ifdef CONFIG_NO_SERIAL_EEPROM
  34
  35 /*
  36 !-------------------------------------------------------------------------------
  37 ! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI,
  38 ! assuming a 33MHz input clock to the 405EP from the C9531.
  39 !-------------------------------------------------------------------------------
  40 */
  41 #define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |  \
  42                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
  43                               PLL_MALDIV_1 | PLL_PCIDIV_3)
  44 #define PLLMR1_333_111_55_37 (PLL_FBKDIV_10  |  \
  45                               PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
  46                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
  47 #define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |  \
  48                                PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
  49                                PLL_MALDIV_1 | PLL_PCIDIV_1)
  50 #define PLLMR1_333_111_55_111 (PLL_FBKDIV_10  |  \
  51                                PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
  52                                PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
  53
  54 #define PLLMR0_DEFAULT          PLLMR0_333_111_55_37
  55 #define PLLMR1_DEFAULT          PLLMR1_333_111_55_37
  56 #define PLLMR0_DEFAULT_PCI66    PLLMR0_333_111_55_111
  57 #define PLLMR1_DEFAULT_PCI66    PLLMR1_333_111_55_111
  58
  59 #endif
  60 /*----------------------------------------------------------------------------*/
  61
  62 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars */
  63
  64 /*
  65  * Default environment variables
  66  */
  67 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  68         CONFIG_AMCC_DEF_ENV                                             \
  69         CONFIG_AMCC_DEF_ENV_PPC                                         \
  70         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
  71         "kernel_addr=FC000000\0"                                        \
  72         "ramdisk_addr=FC180000\0"                                       \
  73         ""
  74
  75 #define CONFIG_PHY_ADDR         0x14    /* PHY address                  */
  76 #define CONFIG_HAS_ETH0
  77 #define CONFIG_HAS_ETH1
  78 #define CONFIG_PHY1_ADDR        0x10    /* EMAC1 PHY address            */
  79 #define CONFIG_PHY_RESET        1
  80
  81 /*
  82  * Commands additional to the ones defined in amcc-common.h
  83  */
  84 #define CONFIG_CMD_CACHE
  85 #define CONFIG_CMD_PCI
  86 #define CONFIG_CMD_SDRAM
  87 #define CONFIG_CMD_SPI
  88
  89 #undef CONFIG_SPD_EEPROM                /* use SPD EEPROM for setup */
  90 #define CONFIG_SYS_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
  91 #define CONFIG_SYS_SDRAM_BANKS          2
  92
  93 /*
  94  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  95  */
  96 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
  97 #define CONFIG_SDRAM_BANK1      1       /* init onboard SDRAM bank 1 */
  98
  99 /* SDRAM timings used in datasheet */
 100 #define CONFIG_SYS_SDRAM_CL            3        /* CAS latency */
 101 #define CONFIG_SYS_SDRAM_tRP           20       /* PRECHARGE command period */
 102 #define CONFIG_SYS_SDRAM_tRC           66       /* ACTIVE-to-ACTIVE command period */
 103 #define CONFIG_SYS_SDRAM_tRCD          20       /* ACTIVE-to-READ delay */
 104 #define CONFIG_SYS_SDRAM_tRFC           66      /* Auto refresh period */
 105
 106 /*
 107  * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
 108  * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
 109  * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
 110  * The Linux BASE_BAUD define should match this configuration.
 111  *    baseBaud = cpuClock/(uartDivisor*16)
 112  * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
 113  * set Linux BASE_BAUD to 403200.
 114  */
 115 #define CONFIG_CONS_INDEX       2       /* Use UART1                    */
 116 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
 117 #undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
 118 #define CONFIG_SYS_BASE_BAUD            691200
 119
 120 /*-----------------------------------------------------------------------
 121  * I2C stuff
 122  *-----------------------------------------------------------------------
 123  */
 124 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 125
 126 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* avoid i2c probe hangup (?) */
 127 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   6 /* 24C02 requires 5ms delay */
 128
 129 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* I2C boot EEPROM (24C02W)     */
 130 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1       /* Bytes of address             */
 131
 132 #define CONFIG_SOFT_SPI
 133 #define SPI_SCL  spi_scl
 134 #define SPI_SDA  spi_sda
 135 #define SPI_READ spi_read()
 136 #define SPI_DELAY udelay(2)
 137 #ifndef __ASSEMBLY__
 138 void spi_scl(int);
 139 void spi_sda(int);
 140 unsigned char spi_read(void);
 141 #endif
 142
 143 /* standard dtt sensor configuration */
 144 #define CONFIG_DTT_DS1775       1
 145 #define CONFIG_DTT_SENSORS      { 0 }
 146 #define CONFIG_SYS_I2C_DTT_ADDR 0x49
 147
 148 /*-----------------------------------------------------------------------
 149  * PCI stuff
 150  *-----------------------------------------------------------------------
 151  */
 152 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter    */
 153 #define PCI_HOST_FORCE   1              /* configure as pci host       */
 154 #define PCI_HOST_AUTO    2              /* detected via arbiter enable */
 155
 156 #define CONFIG_PCI                      /* include pci support         */
 157 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 158 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function    */
 159 #define CONFIG_PCI_PNP                  /* do pci plug-and-play        */
 160                                         /* resource configuration      */
 161 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 162
 163 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC */
 164 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever */
 165 #define CONFIG_SYS_PCI_CLASSCODE       0x0600  /* PCI Class Code: bridge/host */
 166 #define CONFIG_SYS_PCI_PTM1LA       0x00000000  /* point to sdram              */
 167 #define CONFIG_SYS_PCI_PTM1MS      0x80000001   /* 2GB, enable hard-wired to 1 */
 168 #define CONFIG_SYS_PCI_PTM1PCI     0x00000000   /* Host: use this pci address  */
 169 #define CONFIG_SYS_PCI_PTM2LA      0x00000000   /* disabled                    */
 170 #define CONFIG_SYS_PCI_PTM2MS       0x00000000  /* disabled                    */
 171 #define CONFIG_SYS_PCI_PTM2PCI     0x04000000   /* Host: use this pci address  */
 172 #define CONFIG_EEPRO100         1
 173
 174 /*-----------------------------------------------------------------------
 175  * Start addresses for the final memory configuration
 176  * (Set up by the startup code)
 177  */
 178 #define CONFIG_SYS_FLASH_BASE           0xFFE00000
 179
 180 /*-----------------------------------------------------------------------
 181  * FLASH organization
 182  */
 183 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 184 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 185
 186 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 187 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 188
 189 #define CONFIG_SYS_FLASH_ADDR0         0x555
 190 #define CONFIG_SYS_FLASH_ADDR1         0x2aa
 191 #define CONFIG_SYS_FLASH_WORD_SIZE     unsigned short
 192
 193 #ifdef CONFIG_ENV_IS_IN_FLASH
 194 #define CONFIG_ENV_SECT_SIZE    0x10000 /* size of one complete sector  */
 195 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 196 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 197
 198 /* Address and size of Redundant Environment Sector     */
 199 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 200 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 201 #endif /* CONFIG_ENV_IS_IN_FLASH */
 202
 203 /*-----------------------------------------------------------------------
 204  * NVRAM organization
 205  */
 206 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xf0000000      /* NVRAM base address */
 207 #define CONFIG_SYS_NVRAM_SIZE           0x1ff8          /* NVRAM size */
 208
 209 #ifdef CONFIG_ENV_IS_IN_NVRAM
 210 #define CONFIG_ENV_SIZE         0x0ff8          /* Size of Environment vars */
 211 #define CONFIG_ENV_ADDR         \
 212         (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)      /* Env*/
 213 #endif
 214
 215 /*-----------------------------------------------------------------------
 216  * PPC405 GPIO Configuration
 217  */
 218 #define CONFIG_SYS_4xx_GPIO_TABLE { /*                          GPIO    Alternate1              */      \
 219 {                                                                                               \
 220 /* GPIO Core 0 */                                                                               \
 221 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast    SPI CS      */      \
 222 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1   TS1E                    */      \
 223 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2   TS2E                    */      \
 224 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3   TS1O                    */      \
 225 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4   TS2O                    */      \
 226 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5   TS3                     */      \
 227 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6   TS4                     */      \
 228 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7   TS5                     */      \
 229 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8   TS6                     */      \
 230 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9   TrcClk                  */      \
 231 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1                  */      \
 232 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2                  */      \
 233 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3                  */      \
 234 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4                  */      \
 235 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03   SPI SCLK    */      \
 236 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04   SPI DI      */      \
 237 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05   SPI DO      */      \
 238 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0        PCI INTA    */      \
 239 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1        PCI INTB    */      \
 240 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2        PCI INTC    */      \
 241 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3        PCI INTD    */      \
 242 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4        USB         */      \
 243 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5        EBC         */      \
 244 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6        unused      */      \
 245 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD   UART1       */      \
 246 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR               */      \
 247 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI                */      \
 248 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR               */      \
 249 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx    UART0       */      \
 250 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx                */      \
 251 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0  User LED1   */      \
 252 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1  User LED2   */      \
 253 }                                                                                               \
 254 }
 255
 256 /*
 257  * Init Memory Controller:
 258  *
 259  * BR0/1 and OR0/1 (FLASH)
 260  */
 261
 262 #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
 263 #define FLASH_BASE1_PRELIM  0xFC000000  /* FLASH bank #1 */
 264
 265 /*-----------------------------------------------------------------------
 266  * Definitions for initial stack pointer and data area (in data cache)
 267  */
 268 /* use on chip memory (OCM) for temperary stack until sdram is tested */
 269 #define CONFIG_SYS_TEMP_STACK_OCM        1
 270
 271 /* On Chip Memory location */
 272 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 273 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 274 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 275 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 276
 277 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 278 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 279
 280 /*-----------------------------------------------------------------------
 281  * External Bus Controller (EBC) Setup
 282  */
 283
 284 /* Memory Bank 0 (Flash/SRAM) initialization */
 285 #define CONFIG_SYS_EBC_PB0AP           0x03815600
 286 #define CONFIG_SYS_EBC_PB0CR           0xFFE3A000  /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */
 287
 288 /* Memory Bank 1 (NVRAM/RTC) initialization */
 289 #define CONFIG_SYS_EBC_PB1AP           0x05815600
 290 #define CONFIG_SYS_EBC_PB1CR           0xFC0BA000  /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */
 291
 292 /* Memory Bank 2 (USB device) initialization */
 293 #define CONFIG_SYS_EBC_PB2AP           0x03016600
 294 #define CONFIG_SYS_EBC_PB2CR           0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */
 295
 296 /* Memory Bank 3 (LCM and D-flip-flop) initialization */
 297 #define CONFIG_SYS_EBC_PB3AP           0x158FF600
 298 #define CONFIG_SYS_EBC_PB3CR           0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */
 299
 300 /* Memory Bank 4 (not install) initialization */
 301 #define CONFIG_SYS_EBC_PB4AP           0x158FF600
 302 #define CONFIG_SYS_EBC_PB4CR           0x5021A000
 303
 304 #define CPLD_REG0_ADDR  0x50100000
 305 #define CPLD_REG1_ADDR  0x50100001
 306
 307 #endif  /* __CONFIG_H */