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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/tao3530.h
515a28410abe6e6bb20ff3674443c95014989482
2 * Configuration settings for the TechNexion TAO-3530 SOM
3 * equipped on Thunder baseboard.
5 * Edward Lin <linuxfae@technexion.com>
6 * Tapani Utriainen <linuxfae@technexion.com>
8 * Copyright (C) 2013 Stefan Roese <sr@denx.de>
10 * SPDX-License-Identifier: GPL-2.0+
17 * High Level Configuration Options
19 #define CONFIG_OMAP /* in a TI OMAP core */
21 #define CONFIG_OMAP_GPIO
22 /* Common ARM Erratas */
23 #define CONFIG_ARM_ERRATA_454179
24 #define CONFIG_ARM_ERRATA_430973
25 #define CONFIG_ARM_ERRATA_621766
27 #define MACH_TYPE_OMAP3_TAO3530 2836
29 #define CONFIG_SDRC /* Has an SDRC controller */
31 #include <asm/arch/cpu.h> /* get chip and board defs */
32 #include <asm/arch/omap.h>
35 #define V_OSCK 26000000 /* Clock output from T2 */
36 #define V_SCLK (V_OSCK >> 1)
38 #define CONFIG_MISC_INIT_R
40 #define CONFIG_CMDLINE_TAG
41 #define CONFIG_SETUP_MEMORY_TAGS
42 #define CONFIG_INITRD_TAG
43 #define CONFIG_REVISION_TAG
46 * Size of malloc() pool
48 #define CONFIG_SYS_MALLOC_LEN (4 << 20)
49 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
56 * NS16550 Configuration
58 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
60 #define CONFIG_SYS_NS16550_SERIAL
61 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
62 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
65 * select serial console configuration
67 #define CONFIG_CONS_INDEX 3
68 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
70 /* allow to overwrite serial and ethaddr */
71 #define CONFIG_ENV_OVERWRITE
72 #define CONFIG_BAUDRATE 115200
73 #define CONFIG_GENERIC_MMC
76 #define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */
77 #define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */
78 #define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */
79 #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
80 #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
82 /* commands to include */
83 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
84 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
85 #define MTDIDS_DEFAULT "nand0=nand"
86 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
87 "1920k(u-boot),128k(u-boot-env),"\
90 #define CONFIG_CMD_NAND /* NAND support */
92 #define CONFIG_SYS_NO_FLASH
93 #define CONFIG_SYS_I2C
94 #define CONFIG_SYS_I2C_OMAP34XX
95 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
96 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
97 #define CONFIG_I2C_MULTI_BUS
102 #define CONFIG_TWL4030_POWER
103 #define CONFIG_TWL4030_LED
108 #define CONFIG_NAND_OMAP_GPMC
109 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
111 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
112 /* to access nand at */
115 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
117 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
118 /* Environment information */
120 #define CONFIG_EXTRA_ENV_SETTINGS \
121 "loadaddr=0x82000000\0" \
122 "console=ttyO2,115200n8\0" \
124 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
125 "tv_mode=omapfb.mode=tv:ntsc\0" \
126 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
127 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
128 "extra_options= \0" \
130 "mmcroot=/dev/mmcblk0p2 rw\0" \
131 "mmcrootfstype=ext3 rootwait\0" \
132 "nandroot=ubi0:rootfs ubi.mtd=4\0" \
133 "nandrootfstype=ubifs\0" \
134 "mmcargs=setenv bootargs console=${console} " \
135 "mpurate=${mpurate} " \
138 "rootfstype=${mmcrootfstype} " \
139 "${extra_options}\0" \
140 "nandargs=setenv bootargs console=${console} " \
141 "mpurate=${mpurate} " \
143 "${network_setting} " \
144 "root=${nandroot} " \
145 "rootfstype=${nandrootfstype} "\
146 "${extra_options}\0" \
147 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
148 "bootscript=echo Running bootscript from mmc ...; " \
149 "source ${loadaddr}\0" \
150 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
151 "mmcboot=echo Booting from mmc ...; " \
153 "bootm ${loadaddr}\0" \
154 "nandboot=echo Booting from nand ...; " \
156 "nand read ${loadaddr} 280000 400000; " \
157 "bootm ${loadaddr}\0" \
159 #define CONFIG_BOOTCOMMAND \
160 "if mmc rescan ${mmcdev}; then " \
161 "if run loadbootscript; then " \
164 "if run loaduimage; then " \
166 "else run nandboot; " \
169 "else run nandboot; fi"
172 * Miscellaneous configurable options
174 #define CONFIG_SYS_LONGHELP /* undef to save memory */
175 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
177 /* turn on command-line edit/hist/auto */
178 #define CONFIG_CMDLINE_EDITING
179 #define CONFIG_COMMAND_HISTORY
180 #define CONFIG_AUTO_COMPLETE
182 /* Print Buffer Size */
183 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
184 sizeof(CONFIG_SYS_PROMPT) + 16)
185 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
186 /* Boot Argument Buffer Size */
187 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
189 #define CONFIG_SYS_ALT_MEMTEST 1
190 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
192 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */
193 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
195 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
197 #define CONFIG_SYS_TEXT_BASE 0x80008000
200 * OMAP3 has 12 GP timers, they can be driven by the system clock
201 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
202 * This rate is divided by a local divisor.
204 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
205 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
210 * The stack sizes are set up in start.S using the settings below
212 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
215 * Physical Memory Map
217 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
218 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
219 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
220 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
223 * FLASH and environment organization
226 /* **** PISMO SUPPORT *** */
227 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
228 #define CONFIG_SYS_FLASH_BASE NAND_BASE
230 /* Monitor at start of flash */
231 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
232 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
234 #define CONFIG_ENV_IS_IN_NAND 1
235 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
236 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
238 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10)
239 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
240 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
242 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
243 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
244 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
245 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
246 CONFIG_SYS_INIT_RAM_SIZE - \
247 GENERATED_GBL_DATA_SIZE)
249 #define CONFIG_OMAP3_SPI
254 * Currently only EHCI is enabled, the MUSB OTG controller
259 #define CONFIG_USB_EHCI
260 #define CONFIG_USB_EHCI_OMAP
261 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162
263 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
264 #define CONFIG_USB_HOST_ETHER
265 #define CONFIG_USB_ETHER_SMSC95XX
267 #define CONFIG_USB_ETHER
268 #define CONFIG_USB_ETHER_RNDIS
269 #define CONGIG_CMD_STORAGE
271 /* Defines for SPL */
272 #define CONFIG_SPL_FRAMEWORK
273 #define CONFIG_SPL_NAND_SIMPLE
275 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
276 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
278 #define CONFIG_SPL_BOARD_INIT
279 #define CONFIG_SPL_NAND_BASE
280 #define CONFIG_SPL_NAND_DRIVERS
281 #define CONFIG_SPL_NAND_ECC
282 #define CONFIG_SPL_OMAP3_ID_NAND
283 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
285 /* NAND boot config */
286 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
287 #define CONFIG_SYS_NAND_PAGE_COUNT 64
288 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
289 #define CONFIG_SYS_NAND_OOBSIZE 64
290 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
291 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
293 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
294 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
296 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
298 #define CONFIG_SYS_NAND_ECCSIZE 512
299 #define CONFIG_SYS_NAND_ECCBYTES 3
300 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
302 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
303 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
305 #define CONFIG_SPL_TEXT_BASE 0x40200800
306 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
307 CONFIG_SPL_TEXT_BASE)
310 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
311 * older x-loader implementations. And move the BSS area so that it
312 * doesn't overlap with TEXT_BASE.
314 #define CONFIG_SYS_TEXT_BASE 0x80008000
315 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
316 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
318 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
319 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
321 #endif /* __CONFIG_H */