include/configs/tegra30-common.h

   1 /*
   2  *  (C) Copyright 2010-2012
   3  *  NVIDIA Corporation <www.nvidia.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _TEGRA30_COMMON_H_
   9 #define _TEGRA30_COMMON_H_
  10 #include "tegra-common.h"
  11
  12 /* Cortex-A9 uses a cache line size of 32 bytes */
  13 #define CONFIG_SYS_CACHELINE_SIZE       32
  14
  15 /*
  16  * Errata configuration
  17  */
  18 #define CONFIG_ARM_ERRATA_743622
  19 #define CONFIG_ARM_ERRATA_751472
  20
  21 /*
  22  * NS16550 Configuration
  23  */
  24 #define V_NS16550_CLK           408000000       /* 408MHz (pllp_out0) */
  25
  26 /*
  27  * Miscellaneous configurable options
  28  */
  29 #define CONFIG_STACKBASE        0x82800000      /* 40MB */
  30
  31 /*-----------------------------------------------------------------------
  32  * Physical Memory Map
  33  */
  34 #define CONFIG_SYS_TEXT_BASE    0x8010E000
  35
  36 /*
  37  * Memory layout for where various images get loaded by boot scripts:
  38  *
  39  * scriptaddr can be pretty much anywhere that doesn't conflict with something
  40  *   else. Put it above BOOTMAPSZ to eliminate conflicts.
  41  *
  42  * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
  43  *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
  44  *
  45  * kernel_addr_r must be within the first 128M of RAM in order for the
  46  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  47  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
  48  *   should not overlap that area, or the kernel will have to copy itself
  49  *   somewhere else before decompression. Similarly, the address of any other
  50  *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
  51  *   this up to 16M allows for a sizable kernel to be decompressed below the
  52  *   compressed load address.
  53  *
  54  * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
  55  *   the compressed kernel to be up to 16M too.
  56  *
  57  * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
  58  *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
  59  */
  60 #define CONFIG_LOADADDR 0x81000000
  61 #define MEM_LAYOUT_ENV_SETTINGS \
  62         "scriptaddr=0x90000000\0" \
  63         "pxefile_addr_r=0x90100000\0" \
  64         "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
  65         "fdt_addr_r=0x82000000\0" \
  66         "ramdisk_addr_r=0x82100000\0"
  67
  68 /* Defines for SPL */
  69 #define CONFIG_SPL_TEXT_BASE            0x80108000
  70 #define CONFIG_SYS_SPL_MALLOC_START     0x80090000
  71 #define CONFIG_SPL_STACK                0x800ffffc
  72
  73 /* For USB EHCI controller */
  74 #define CONFIG_EHCI_IS_TDI
  75 #define CONFIG_USB_EHCI_TXFIFO_THRESH   0x10
  76 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
  77
  78 #endif /* _TEGRA30_COMMON_H_ */