include/configs/theadorable.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
   4  */
   5
   6 #ifndef _CONFIG_THEADORABLE_H
   7 #define _CONFIG_THEADORABLE_H
   8
   9 /*
  10  * High Level Configuration Options (easy to change)
  11  */
  12
  13 /*
  14  * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
  15  * for DDR ECC byte filling in the SPL before loading the main
  16  * U-Boot into it.
  17  */
  18 #define CONFIG_SYS_TCLK         250000000       /* 250MHz */
  19
  20 /*
  21  * Commands configuration
  22  */
  23
  24 /*
  25  * The debugging version enables USB support via defconfig.
  26  * This version should also enable all other non-production
  27  * interfaces / features.
  28  */
  29
  30 /* I2C */
  31 #define CONFIG_SYS_I2C
  32 #define CONFIG_SYS_I2C_MVTWSI
  33 #define CONFIG_I2C_MVTWSI_BASE0         MVEBU_TWSI_BASE
  34 #define CONFIG_I2C_MVTWSI_BASE1         MVEBU_TWSI1_BASE
  35 #define CONFIG_SYS_I2C_SLAVE            0x0
  36 #define CONFIG_SYS_I2C_SPEED            100000
  37
  38 /* USB/EHCI configuration */
  39 #define CONFIG_EHCI_IS_TDI
  40 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
  41
  42 /* SPI NOR flash default params, used by sf commands */
  43 #define CONFIG_SF_DEFAULT_SPEED         27777777 /* for fast SPL booting */
  44 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_3
  45
  46 /* Environment in SPI NOR flash */
  47 #define CONFIG_ENV_OFFSET               (1 << 20) /* 1MiB in */
  48 #define CONFIG_ENV_SIZE                 (64 << 10) /* 64KiB */
  49 #define CONFIG_ENV_SECT_SIZE            (256 << 10) /* 256KiB sectors */
  50 #define CONFIG_ENV_OVERWRITE
  51
  52 #define PHY_ANEG_TIMEOUT        8000    /* PHY needs a longer aneg time */
  53
  54 #define CONFIG_PREBOOT
  55
  56 /* Keep device tree and initrd in lower memory so the kernel can access them */
  57 #define CONFIG_EXTRA_ENV_SETTINGS       \
  58         "fdt_high=0x10000000\0"         \
  59         "initrd_high=0x10000000\0"
  60
  61 /* SATA support */
  62 #define CONFIG_SYS_SATA_MAX_DEVICE      1
  63 #define CONFIG_LBA48
  64
  65 /* Enable LCD and reserve 512KB from top of memory*/
  66 #define CONFIG_SYS_MEM_TOP_HIDE         0x80000
  67
  68 /* FPGA programming support */
  69 #define CONFIG_FPGA_STRATIX_V
  70
  71 /*
  72  * Bootcounter
  73  */
  74 /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
  75 #define BOOTCOUNT_ADDR                  0x1000
  76
  77 /*
  78  * mv-common.h should be defined after CMD configs since it used them
  79  * to enable certain macros
  80  */
  81 #include "mv-common.h"
  82
  83 /*
  84  * Memory layout while starting into the bin_hdr via the
  85  * BootROM:
  86  *
  87  * 0x4000.4000 - 0x4003.4000    headers space (192KiB)
  88  * 0x4000.4030                  bin_hdr start address
  89  * 0x4003.4000 - 0x4004.7c00    BootROM memory allocations (15KiB)
  90  * 0x4007.fffc                  BootROM stack top
  91  *
  92  * The address space between 0x4007.fffc and 0x400f.fff is not locked in
  93  * L2 cache thus cannot be used.
  94  */
  95
  96 /* SPL */
  97 /* Defines for SPL */
  98 #define CONFIG_SPL_TEXT_BASE            0x40004030
  99 #define CONFIG_SPL_MAX_SIZE             ((128 << 10) - 0x4030)
 100
 101 #define CONFIG_SPL_BSS_START_ADDR       (0x40000000 + (128 << 10))
 102 #define CONFIG_SPL_BSS_MAX_SIZE         (16 << 10)
 103
 104 #ifdef CONFIG_SPL_BUILD
 105 #define CONFIG_SYS_MALLOC_SIMPLE
 106 #endif
 107
 108 #define CONFIG_SPL_STACK                (0x40000000 + ((192 - 16) << 10))
 109 #define CONFIG_SPL_BOOTROM_SAVE         (CONFIG_SPL_STACK + 4)
 110
 111 /* SPL related SPI defines */
 112 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x1a000
 113 #define CONFIG_SYS_U_BOOT_OFFS          CONFIG_SYS_SPI_U_BOOT_OFFS
 114
 115 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
 116 #define CONFIG_DDR_FIXED_SIZE           (2 << 20)       /* 2GiB */
 117
 118 #endif /* _CONFIG_THEADORABLE_H */